JPH08107175A - Lead frame and semiconductor device manufacturing method - Google Patents

Lead frame and semiconductor device manufacturing method

Info

Publication number
JPH08107175A
JPH08107175A JP23868594A JP23868594A JPH08107175A JP H08107175 A JPH08107175 A JP H08107175A JP 23868594 A JP23868594 A JP 23868594A JP 23868594 A JP23868594 A JP 23868594A JP H08107175 A JPH08107175 A JP H08107175A
Authority
JP
Japan
Prior art keywords
semiconductor chip
inner lead
bonding wire
lead frame
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23868594A
Other languages
Japanese (ja)
Inventor
Hiroteru Miyamoto
博輝 宮本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP23868594A priority Critical patent/JPH08107175A/en
Publication of JPH08107175A publication Critical patent/JPH08107175A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To improve the electric connection of resin molded inner leads to a semiconductor chip through bonding wires by forming openings through the inner leads. CONSTITUTION: The electric connection of a semiconductor chip 1 to inner leads 2a is made through openings 8 formed at central parts of the leads. Pads 6 are formed below the openings 2 and bonding wires 3 are formed, extending from the pads 6 to the surfaces of the leads 2a, thus connecting the wires 3 to the surfaces of the leads 2a through the openings 8. There is no need of purposely connecting the wires 3 to the surfaces of the leads 2a, so far as connected to the side faces of the openings 8. Thus, the wires 3 can be housed in the openings 8, this allowing the wires 3 to be very short.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体チップと電気的接
続をとるためのリードフレームに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for making electrical connection with a semiconductor chip.

【０００２】[0002]

【従来の技術】電子機器の機能は電子回路によって構成
されるが、その電子回路をより効果的動作させるために
半導体チップとパッケージがある。パッケージは半導体
チップの性能を最大限に引き出す手段であるといって過
言ではない。パッケージにおける機能は次の四項目に大
別できる。2. Description of the Related Art The function of an electronic device is constituted by an electronic circuit, and there are a semiconductor chip and a package for operating the electronic circuit more effectively. It is no exaggeration to say that the package is a means to maximize the performance of the semiconductor chip. The functions in the package can be broadly divided into the following four items.

【０００３】（１） 電気的接続 （２） チップ保護 （３） 熱放散 （４） 実装 本発明は半導体チップをパッケージするにあたり、上記
（１）に示す電気的接続に関する機能を最大限に生かす
ものである。この機能はシステム内で半導体チップを電
気的に相互に接続することである。半導体チップを動作
させるためには、外部からの電源を供給する必要があ
る。この電源は、システムからパッケージを通して半導
体チップへ供給される。半導体チップを用いて信号の処
理をするためには、外部との信号のやりとりが必要であ
る。半導体チップに外部から信号を与え処理の結果を取
り出す電気的接続により、半導体チップとの信号のやり
とりを可能にするのもパッケージである。パッケージの
形態は種々のものがあり、従来技術としてＤＩＰ（Dual
In ‐Line Package） を次に示す。図７はＤＩＰとそ
の内部を斜視的に示したものである。ＤＩＰの中央には
半導体チップ１が搭載されており、その電気的入出力は
ボンディングワイヤ３により接続されたリードフレーム
２により行われる。成形樹脂４は半導体チップ１を外部
環境から保護するためのもので、半導体チップ１とボン
ディングワイヤ３を完全に覆うように形成されている。
リードフレーム２は成形樹脂４中に埋設している部分と
露出している部分とで成っており、前者をインナーリー
ド部、後者をアウターリード部と称し、それぞれ２ａ、
２ｂで示す。次に、半導体チップ１とボンディングワイ
ヤ３の拡大したものを図８に示す。フレームベッド部５
上には半導体チップ１が搭載されており、半導体チップ
１上にはパッド部６を介してボンディングワイヤ３が接
続されている。このボンディングワイヤ３のもう一方は
ボンディングリード接合部７を介してインナーリード部
２ａに接続されている。図９にボンディングワイヤ３の
形成状態を示す。これは図８においてＢ―Ｂ方向から観
察した場合の図である。従来技術によればボンディング
ワイヤ３は、半導体チップ１とインナーリード部２ａを
接合する際、ボンディングワイヤ３のネックダメージの
発生を避けるため、緩やかな弧を描く様にループを張
る。この場合、半導体チップ１に形成されているパッド
部６とインナーリード部２ａに形成されているボンディ
ングリード接合部７は同じ平面上になく、パッド部６の
方が高い位置に存在する。従って、低ループボンディン
グの場合でもある程度のループ高さが必要となる。しか
しながらボンディングワイヤ３を弧状に形成すると、樹
脂封止する際に樹脂にボンディングワイヤが押されルー
プの形状が変化するいわゆるワイヤー流れが発生する。
ワイヤー流れが大きくなるとボンディングワイヤが断線
したり、近接するボンディングワイヤ同士で接触し絶縁
不良を起こす。(1) Electrical connection (2) Chip protection (3) Heat dissipation (4) Mounting In the present invention, when packaging a semiconductor chip, the function relating to the electrical connection shown in (1) above is maximized. Is. Its function is to electrically connect the semiconductor chips together in the system. In order to operate the semiconductor chip, it is necessary to supply power from the outside. This power is supplied from the system to the semiconductor chip through the package. In order to process a signal using a semiconductor chip, it is necessary to exchange the signal with the outside. It is also a package that enables signals to be exchanged with a semiconductor chip by an electrical connection that gives a signal to the semiconductor chip from the outside and retrieves the processing result. There are various package forms, and as a conventional technique, DIP (Dual
In-Line Package) is shown below. FIG. 7 is a perspective view of the DIP and its inside. A semiconductor chip 1 is mounted at the center of the DIP, and its electrical input / output is performed by a lead frame 2 connected by a bonding wire 3. The molding resin 4 is for protecting the semiconductor chip 1 from the external environment, and is formed so as to completely cover the semiconductor chip 1 and the bonding wires 3.
The lead frame 2 is composed of a portion embedded in the molding resin 4 and an exposed portion. The former is referred to as an inner lead portion and the latter is referred to as an outer lead portion.
2b. Next, an enlarged view of the semiconductor chip 1 and the bonding wire 3 is shown in FIG. Frame bed part 5
A semiconductor chip 1 is mounted on the semiconductor chip 1, and a bonding wire 3 is connected to the semiconductor chip 1 via a pad portion 6. The other end of the bonding wire 3 is connected to the inner lead portion 2a via the bonding lead joint portion 7. FIG. 9 shows the formation state of the bonding wire 3. This is a view when observed from the BB direction in FIG. According to the conventional technique, when bonding the semiconductor chip 1 and the inner lead portion 2a, the bonding wire 3 is looped so as to draw a gentle arc in order to avoid the neck damage of the bonding wire 3. In this case, the pad portion 6 formed on the semiconductor chip 1 and the bonding lead joint portion 7 formed on the inner lead portion 2a are not on the same plane, and the pad portion 6 exists at a higher position. Therefore, a certain loop height is required even in the case of low loop bonding. However, if the bonding wire 3 is formed in an arc shape, a so-called wire flow occurs in which the bonding wire is pushed by the resin when the resin is sealed and the shape of the loop changes.
If the wire flow becomes large, the bonding wires will be broken or the adjacent bonding wires will come into contact with each other, resulting in insulation failure.

【０００４】[0004]

【発明が解決しようとする課題】上記したように従来技
術を用いた半導体チップとインナーリード部との電気的
接続は、ボンディングワイヤを弧状に張ることにより行
っていた。その結果、樹脂封入時にボンディングワイヤ
の断線やワイヤー流れなどが発生し、電気的接続を保て
なくなっていた。本発明は上記欠点を除去し、半導体チ
ップとインナーリード部との電気的接続が良好となるリ
ードフレームを提供することを目的とする。As described above, the electrical connection between the semiconductor chip and the inner lead portion using the conventional technique has been performed by stretching the bonding wire in an arc shape. As a result, the bonding wire is broken or the wire flows when the resin is filled, and the electrical connection cannot be maintained. An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a lead frame in which the electrical connection between the semiconductor chip and the inner lead portion is good.

【０００５】[0005]

【課題を解決するための手段】上記目的を達成するため
に、第１の発明では、半導体チップ上に形成されたパッ
ド部と、ボンディングワイヤにより接続され、かつ樹脂
封止される複数のインナーリード部を有するリードフレ
ームにおいて、前記インナーリード部に開口部が形成さ
れていることを特徴とするリードフレームを提供し、第
２の発明では、リードフレームのインナーリード部に開
口部を形成する工程と、前記インナーリード部が半導体
チップ上のパッド部上に位置するように、前記リードフ
レームを前記半導体チップ上に載置する工程と、前記パ
ッド部と前記インナーリード部間に、前記開口部内を通
してボンディングワイヤを形成する工程と、前記半導体
チップ、前記インナーリード部、前記ボンディングワイ
ヤを樹脂封止工程を有することを特徴とする半導体装置
の製造方法を提供する。In order to achieve the above object, according to the first invention, a plurality of inner leads which are connected to a pad portion formed on a semiconductor chip by a bonding wire and are resin-sealed. And a step of forming an opening in the inner lead portion of the lead frame, the lead frame having an opening is formed in the inner lead portion. A step of placing the lead frame on the semiconductor chip so that the inner lead portion is located on a pad portion on a semiconductor chip, and bonding between the pad portion and the inner lead portion through the opening. A step of forming a wire and a step of resin-sealing the semiconductor chip, the inner lead portion, and the bonding wire To provide a method of manufacturing a semiconductor device characterized in that it comprises.

【０００６】[0006]

【作用】本発明はリードフレームと半導体チップとの電
気的接続を行う際に、リードフレームのインナーリード
部の所定箇所に予め開口部を形成しておき、この開口部
にボンディングワイヤを形成するというものである。ボ
ンディングワイヤの端部の一方は半導体チップ上のパッ
ド部に接続し、もう一方の端部はインナーリード部の表
面に接続する。この時、ボンディングワイヤはインナー
リード部の開口部を通過して形成する。パッド部とイン
ナーリード部表面の間隔は非常に短いため、ここに形成
されるボンディングワイヤも必然的に短くなり、また露
出部分も減少する。その結果、樹脂封止する際に樹脂に
よってボンディングワイヤが受ける圧力が減少し、ワイ
ヤー流れによるボンディングワイヤの断線や絶縁不良を
回避することができる。According to the present invention, when the lead frame and the semiconductor chip are electrically connected, an opening is formed in advance at a predetermined position of the inner lead portion of the lead frame, and a bonding wire is formed in this opening. It is a thing. One end of the bonding wire is connected to the pad portion on the semiconductor chip, and the other end is connected to the surface of the inner lead portion. At this time, the bonding wire is formed by passing through the opening of the inner lead portion. Since the distance between the pad portion and the surface of the inner lead portion is very short, the bonding wire formed here is inevitably short, and the exposed portion is also reduced. As a result, the pressure applied to the bonding wire by the resin at the time of resin sealing is reduced, and it is possible to avoid disconnection of the bonding wire and insulation failure due to wire flow.

【０００７】[0007]

【実施例】第１の発明を図面を参照して説明する。図１
に本発明のリードフレームを斜視的に示す。この図はパ
ッケージ前の半導体チップ１とリードフレーム２を示し
たものでもあり、本発明の特徴は半導体チップ１上の所
定箇所に直接リードフレーム２を載置していることにあ
る。具体的にはリードフレーム２におけるインナーリー
ド部２ａの全面とアウターリード部２ｂの一部が半導体
チップ１上に接触しており、インナーリード部２ａの中
央部に図示せぬ開口部を形成し、これにボンディングワ
イヤ３を形成することにより、半導体チップ１とアウタ
ーリード２ｂを電気的に接続している。図２は半導体チ
ップとインナーリード部との接合部を拡大したもので、
図１中○で囲んだ部分の拡大図である。半導体チップ１
とインナーリード部２ａとの電気的接続は、インナーリ
ード部２ａの中央部に形成された開口部８によって行わ
れている。この開口部８の下部には図示せぬパッド部が
形成されており、このパッド部からボンディングワイヤ
３をインナーリード２ａの表面にかけて形成している。
図３は半導体チップとインナーリード部との接合部の断
面を示したもので、図２中Ａ―Ａの断面である。半導体
チップ１上のパッド部６にはボンディングワイヤ３が形
成されており、かつこのボンディングワイヤ３は開口部
８を通ってインナーリード部２ａの表面に接続してい
る。この時、ボンディングワイヤ３は、開口部８の側面
に接触させていれば、わざわざインナーリード部２ａの
表面に接続させる必要がない。DESCRIPTION OF THE PREFERRED EMBODIMENTS The first invention will be described with reference to the drawings. FIG.
The perspective view of the lead frame of the present invention is shown in FIG. This figure also shows the semiconductor chip 1 and the lead frame 2 before the package, and the feature of the present invention is that the lead frame 2 is directly mounted on a predetermined position on the semiconductor chip 1. Specifically, the entire surface of the inner lead portion 2a and a part of the outer lead portion 2b in the lead frame 2 are in contact with each other on the semiconductor chip 1, and an opening (not shown) is formed in the center of the inner lead portion 2a. By forming the bonding wire 3 on this, the semiconductor chip 1 and the outer lead 2b are electrically connected. FIG. 2 is an enlarged view of the joint portion between the semiconductor chip and the inner lead portion.
It is an enlarged view of the part enclosed with (circle) in FIG. Semiconductor chip 1
The inner lead portion 2a is electrically connected to the inner lead portion 2a through an opening 8 formed in the central portion of the inner lead portion 2a. A pad portion (not shown) is formed under the opening portion 8, and the bonding wire 3 is formed from the pad portion to the surface of the inner lead 2a.
FIG. 3 shows a cross section of the joint between the semiconductor chip and the inner lead portion, which is taken along the line AA in FIG. A bonding wire 3 is formed on the pad portion 6 on the semiconductor chip 1, and the bonding wire 3 is connected to the surface of the inner lead portion 2a through the opening 8. At this time, the bonding wire 3 need not be purposely connected to the surface of the inner lead portion 2a as long as it is in contact with the side surface of the opening 8.

【０００８】次に他の実施例を示す。図４はインナーリ
ード部に切り欠きを設けた場合のリードフレームと半導
体チップとの接合部を示している。前述の実施例の場合
はインナーリード部に開口部を形成し、そこにボンディ
ングワイヤを通過させていたが、図４に示す実施例では
インナーリード部２ａには開口部の代わりに切り欠き部
９を形成している。そして、この切り欠き部９を通して
ボンディングワイヤ３を形成することにより、半導体チ
ップ１上のパッド部６とインナーリード部２ａ間を電気
的に接続している。図５は切り欠き部の形状を示すイン
ナーリード部の上面図で、図４を上方から観察したもの
である。図より、切り欠き部９がコ状に形成されてお
り、またボンディングワイヤ３の端部をインナーリード
部２ａの表面に接続していることが判る。ところで、切
り欠き部９の向きは如何なる方向でもよく、図に示す下
向きの他に、左向き、上向き、斜め向きであっても本発
明の効果を十分に得ることができる。図６にインナーリ
ード部と半導体チップとの接合部の断面を示す。この図
は図５中Ａ−Ａの断面を示したものである。図３と比較
すると、インナーリード部２ａとパッド部６との間隔が
大きくなっているが、図３に示す程度に近接させても何
等支障はない。Next, another embodiment will be described. FIG. 4 shows a joint portion between the lead frame and the semiconductor chip when the inner lead portion is provided with a notch. In the case of the above-described embodiment, the inner lead portion is formed with the opening and the bonding wire is passed therethrough. However, in the embodiment shown in FIG. 4, the inner lead portion 2a is provided with the notch 9 instead of the opening. Is formed. By forming the bonding wire 3 through the cutout portion 9, the pad portion 6 on the semiconductor chip 1 and the inner lead portion 2a are electrically connected. FIG. 5 is a top view of the inner lead portion showing the shape of the cutout portion, which is an observation of FIG. 4 from above. From the figure, it can be seen that the notch 9 is formed in a U shape and the end of the bonding wire 3 is connected to the surface of the inner lead 2a. By the way, the direction of the cutout portion 9 may be any direction, and the effect of the present invention can be sufficiently obtained even if the cutout portion 9 is oriented downward, leftward, upward, or diagonally. FIG. 6 shows a cross section of a joint portion between the inner lead portion and the semiconductor chip. This figure shows a cross section taken along the line AA in FIG. Although the distance between the inner lead portion 2a and the pad portion 6 is larger than that in FIG. 3, there is no problem even if they are brought close to each other as shown in FIG.

【０００９】次に、第２の発明として開口部を有するリ
ードフレームを用いた半導体チップのパッケージ方法に
ついて述べる。図１は第１の発明のリードフレームを斜
視的に示したもので、この時、半導体チップ１上にリー
ドフレーム２を載置する前に、リードフレーム２のイン
ナーリード部２ａの中央部に予め開口部８を形成してお
く。またこの開口部８は必ず貫通させておくべきもので
あり、その径の大きさは後の工程でこの開口部８に形成
するボンディングワイヤの径と同等かまたはそれ以上に
する必要がある。次に、図１に示すように半導体チップ
１にリードフレーム２を載置する工程に入る訳である
が、このとき半導体チップ１上に形成されたパッド部６
上に、インナーリード部２ａが乗るようにし、しかも開
口部８の底部にパッド部６の表面が位置するようにす
る。その後、図２、図３に示すようにパッド部６とイン
ナーリード部２ａの表面をボンディングワイヤ３により
接続する。その際、ボンディングワイヤ３を極力短くす
るために、開口部８の近傍にボンディングワイヤ３を形
成する。そして最後に樹脂を封止する。尚、本第２の発
明においては、インナーリード部に切り欠きを設ける場
合であっても同様の工程を経ることは言うまでもない。Next, a semiconductor chip packaging method using a lead frame having an opening will be described as a second invention. FIG. 1 is a perspective view of a lead frame of the first invention. At this time, before mounting the lead frame 2 on the semiconductor chip 1, the inner lead portion 2a of the lead frame 2 is preliminarily formed in a central portion thereof. The opening 8 is formed in advance. The opening 8 must be penetrated through, and its diameter must be equal to or larger than the diameter of the bonding wire formed in the opening 8 in a later step. Next, as shown in FIG. 1, the process of mounting the lead frame 2 on the semiconductor chip 1 is started. At this time, the pad portion 6 formed on the semiconductor chip 1
The inner lead portion 2a is placed on the upper portion, and the surface of the pad portion 6 is positioned at the bottom of the opening 8. Thereafter, as shown in FIGS. 2 and 3, the surfaces of the pad portion 6 and the inner lead portion 2a are connected by the bonding wire 3. At that time, in order to make the bonding wire 3 as short as possible, the bonding wire 3 is formed in the vicinity of the opening 8. Finally, the resin is sealed. In the second aspect of the invention, it goes without saying that the same steps are performed even when the notch is provided in the inner lead portion.

【００１０】[0010]

【発明の効果】以上のように、本発明を用いると、半導
体チップとインナーリード部との電気的接続において、
開口部を有するインナーリード部を用いることにより、
ボンディングワイヤをこの開口部に格納することがで
き、従って、ボンディングワイヤを非常に短くするする
ことができ、かつボンディングワイヤを弧状に張る必要
がない。その結果、樹脂封止時にボンディングワイヤの
断線やワイヤー流れなどがなくなり、電気的接続が良好
となる。As described above, according to the present invention, in the electrical connection between the semiconductor chip and the inner lead portion,
By using the inner lead part having an opening,
The bonding wire can be stored in this opening, so that the bonding wire can be very short and it is not necessary to stretch it. As a result, breaking of the bonding wire and wire flow at the time of resin sealing are eliminated, and electrical connection is improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施例を示すリードフレームを示す斜
視図。FIG. 1 is a perspective view showing a lead frame showing an embodiment of the present invention.

【図２】本発明の実施例を示すインナーリード部と半導
体チップの接合部を示す拡大図。FIG. 2 is an enlarged view showing a joint portion between an inner lead portion and a semiconductor chip showing an embodiment of the present invention.

【図３】本発明の実施例を示すインナーリード部と半導
体チップとの接合部の断面図。FIG. 3 is a sectional view of a joint portion between an inner lead portion and a semiconductor chip showing an embodiment of the present invention.

【図４】本発明の実施例を示すインナーリード部に切り
欠きを設けた場合のリードフレームと半導体チップとの
接合部の断面図。FIG. 4 is a sectional view of a joint portion between a lead frame and a semiconductor chip when a notch is provided in an inner lead portion according to an embodiment of the present invention.

【図５】本発明の実施例を示す切り欠き部を有するイン
ナーリード部の上面図。FIG. 5 is a top view of an inner lead portion having a cutout portion according to an embodiment of the present invention.

【図６】本発明の実施例を示す切り欠き部を有するイン
ナーリード部と半導体チップとの接合部の断面図。FIG. 6 is a cross-sectional view of a joint portion between an inner lead portion having a cutout portion and a semiconductor chip according to an embodiment of the present invention.

【図７】従来例を示すＤＩＰとその内部を示す斜視図。FIG. 7 is a perspective view showing a conventional DIP and its inside.

【図８】従来例を示す半導体チップとボンディングワイ
ヤを示す拡大図。FIG. 8 is an enlarged view showing a semiconductor chip and a bonding wire showing a conventional example.

【図９】従来例を示すボンディングワイヤの形成状態を
示す図。FIG. 9 is a diagram showing a forming state of a bonding wire showing a conventional example.

【符号の説明】[Explanation of symbols]

１ 半導体チップ１ ２ リードフレーム ２ａ インナーリード部 ２ｂ アウターリード部 ３ ボンディングワイヤ ４ 成形樹脂 ５ フレームベッド部 ６ パッド部 ７ ボンディングリード接合部 ８ 開口部 ９ 切り欠き部 1 Semiconductor Chip 1 2 Lead Frame 2a Inner Lead 2b Outer Lead 3 Bonding Wire 4 Molding Resin 5 Frame Bed 6 Pad 7 Bonding Lead Joint 8 Opening 9 Notch

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップ上に形成されたパッド部
と、ボンディングワイヤにより接続され、かつ樹脂封止
される複数のインナーリード部を有するリードフレーム
において、 前記インナーリード部に開口部が形成されていることを
特徴とするリードフレーム。1. A lead frame having a plurality of inner lead portions connected to a pad portion formed on a semiconductor chip by a bonding wire and sealed with a resin, wherein an opening is formed in the inner lead portion. Lead frame characterized by 【請求項２】リードフレームのインナーリード部に開口
部を形成する工程と、 前記インナーリード部が半導体チップ上のパッド部上に
位置するように、前記リードフレームを前記半導体チッ
プ上に載置する工程と、 前記パッド部と前記インナーリード部間に、前記開口部
内を通してボンディングワイヤを形成する工程と、 前記半導体チップ、前記インナーリード部、前記ボンデ
ィングワイヤを樹脂封止工程を有することを特徴とする
半導体装置の製造方法。2. A step of forming an opening in an inner lead portion of a lead frame, and mounting the lead frame on the semiconductor chip so that the inner lead portion is located on a pad portion on the semiconductor chip. A step of forming a bonding wire between the pad part and the inner lead part through the opening, and a step of resin-sealing the semiconductor chip, the inner lead part, and the bonding wire. Manufacturing method of semiconductor device.
JP23868594A 1994-10-03 1994-10-03 Lead frame and semiconductor device manufacturing method Pending JPH08107175A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23868594A JPH08107175A (en) 1994-10-03 1994-10-03 Lead frame and semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23868594A JPH08107175A (en) 1994-10-03 1994-10-03 Lead frame and semiconductor device manufacturing method

Publications (1)

Publication Number Publication Date
JPH08107175A true JPH08107175A (en) 1996-04-23

Family

ID=17033785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23868594A Pending JPH08107175A (en) 1994-10-03 1994-10-03 Lead frame and semiconductor device manufacturing method

Country Status (1)

Country Link
JP (1) JPH08107175A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5238816A (en) * 1989-07-24 1993-08-24 Asahi Kasei Kogyo Kabushiki Kaisha Omega carboxyalcohol oxidase enzyme
KR100472309B1 (en) * 1997-07-22 2005-05-27 삼성전자주식회사 Metal Tool for Beam Lead Bonding

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5238816A (en) * 1989-07-24 1993-08-24 Asahi Kasei Kogyo Kabushiki Kaisha Omega carboxyalcohol oxidase enzyme
KR100472309B1 (en) * 1997-07-22 2005-05-27 삼성전자주식회사 Metal Tool for Beam Lead Bonding

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