JPH08106791A - Method of driving semiconductor memory - Google Patents

Abstract

PURPOSE: To obtain a method which allows the reading of memory contents of a NOR type non-volatile memory with a lower voltage and a lower power consumption. CONSTITUTION: Source wires S1-Sm are arranged parallel with word wires W1-Wm with respect to a memory array where NOR type non-volatile memory cells (T11)-(Tmn) are arranged in a matrix. When memory contents of the memory cells are read out, potentials of bit wires B1-Bn are set lower than that of a selected source wire. By this method, the lowering of the threshold voltage of the memory cells attributed to a drain voltage of a transistor is checked to prevent erroneous reading owing to action of a non-selection memory cell. This also eliminates charging or discharging by reading memory cells arranged on a common word wire in a batch thereby enabling the lowering of power consumption and further allows the expanding of the margin of variations in the threshold voltage of the memory cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having an array structure composed of a plurality of memory cells functioning as a non-volatile memory and a driving method thereof.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory device equipped with a nonvolatile memory, as disclosed in, for example, Japanese Unexamined Patent Publication No. Hei5-28778, Japanese Unexamined Patent Publication Hei-4-356797 and Japanese Unexamined Patent Publication Hei4-15953, There is known one in which a source decoder is connected to a source line connected to the source of a memory cell that constitutes a memory cell. Below, FIG.
28 to 28, a conventional semiconductor memory device equipped with a nonvolatile memory cell will be described. FIG. 24 is a block circuit diagram of a conventional semiconductor memory device. 101 is a memory cell array, 102 is a row decoder circuit, 103
Is a column decoder circuit, and 104 is a source decoder circuit. FIG. 25 is a circuit diagram showing a part of a memory cell array 101 of a conventional semiconductor memory device. Where T11 to Tmn
Is a non-volatile memory transistor, W1 to Wm are word lines, B1 to Bn are bit lines, S1 to Sm are source lines, S
A1 to SAn are sense amplifiers, ST1 to STn are column selecting transistors, RD1 to RDm are row decoders, SD
1 to SDm are source decoders. As shown in FIG. 25, each of the memory transistors T11 to Tmn is composed of a source, a drain, and a gate, and a capacitance portion (floating gate) is arranged below the gates of the transistors T11 to Tmn to form a nonvolatile memory cell. . The memory cell array 101 is configured by arranging memory cells having the transistors T11 to Tmn therein in a matrix of m rows and n columns. The gates of the transistors T11 to T1n arranged in the first row are word lines W1 and the gates of the transistors T21 to T2n arranged in the second row are word lines W2.
In addition, the gates of the transistors Tm1 to Tmn arranged in the m-th row are connected to the word line Wm, respectively. The sources of the transistors T11 to T1n arranged in the first row are the source lines S1 to the transistors T21 to T1n arranged in the second row.
The source of T2n is connected to the source line S2, and the sources of the transistors Tm1 to Tmn arranged in the m-th row are connected to the source line Sm. Further, the drains of the transistors T11 to Tm1 arranged in the first column are on the bit line B1, the drains of the transistors T12 to Tm2 arranged in the second column are on the bit line B2, and the transistors T1n to Tn in the nth column are arranged. T
The drains of mn are connected to the bit lines Bn, respectively. That is, word lines W1 to Wm and bit lines B1 to Bm
N which arranges the memory transistors T11 to Tmn at the intersection of n
It is an OR type configuration. Here, the word lines W1 to Wm and the source lines S1 to Sm extend in the same direction, and the word lines W1 to Wm.
m is connected to the row decoder circuit 102 in which the row decoders RD1 to RDm are set high, the source lines S1 to Sm are connected to the source decoder circuit 104 in which the source decoders SD1 to SDm are arranged, while the bit lines B1 to Bn are connected. The word lines W1 to Wm and the source lines S1 to Sm extend in a direction orthogonal to each other and are connected to the column decoder circuit 103 via sense amplifiers SA1 to SAn. As will be described later, in the paths P11 to Pmn from one portion of each bit line B1 to Bn to each source line S1 to Sm via each memory transistor T11 to Tmn, the potential of the gate is equal to or more than the threshold voltage. When the potential between the source and the source is equal to or higher than a predetermined value, a current flows if the memory state of the capacitor is "1", and no current flows if the memory state of the capacitor is "0".

Next, referring to FIG. 25, a conventional data reading method of a semiconductor memory device will be described. E
In a nonvolatile semiconductor memory device represented by EPROM, writing and erasing are performed by electrically changing the threshold value of a memory transistor. Generally, a state in which the memory cell is at a threshold voltage higher than the read power supply voltage Vcc is a “0” state, and the memory cell is in the read power supply voltage Vcc
The state where the threshold voltage is lower than cc is called "1" state,
I will call it so.

A conventional read method will be described for the case of reading a memory cell having a transistor T22 therein (hereinafter, referred to as a memory cell (T22)). First,
The selected word line W2 is read out from the power source voltage Vcc (for example, 5
V) and set the non-selected word lines W1 and W3 to the ground potential Vss.
(For example, 0 V). At the same time, the selected source line S2 is set to the ground potential Vss, and the non-selected source lines S1 and Sm are floated while being kept at the read intermediate potential Vrm (for example, 1V) or the read intermediate potential Vrm. Further, the selected bit line B2 is set to Vrm via the sense amplifier, and the non-selected bit lines B1 and Bn are made floating while keeping the ground potential Vss or the ground potential Vss. In reality, since the sense amplifier is connected to the bit line, the potential of the bit line is Vrm
However, it is assumed that the voltage is constant for simplicity of explanation. In addition, although the non-selected source line and the non-selected bit line may be floated in some cases, the non-selected source line is set to the read intermediate potential Vrm and the non-selected bit line is set to Vss for simplicity of description. If the memory cell (T22) is in the "0" state, no current flows through the memory cell (T22), and no current flows through the bit line B2. If the memory cell (T22) is in the "1" state, a current flows from the bit line B2 through the memory cell (T22) to the source line S2. Data is read by detecting the presence / absence of a current in the bit line B2 with a sense amplifier. In a conventional semiconductor memory device equipped with a non-volatile memory cell, for example, as shown in FIG. 19, an unselected memory cell (T12) connected to the same bit line B2 as the memory cell (T22) has an excessively low threshold voltage. Even if the depletion is weak in the voltage state,
Since the potential of the source line S1 is Vrm and the same potential as that of the bit line B2, it is difficult for current to flow from the bit lines B2 to S1 and the unselected memory cells (T12) are not strongly depleted unless they are deselected memory cells. (T12) is not erroneously read, and the read margin is wide. Similarly, when the source line S1 is set to a floating state, a through current does not flow from the bit line B2 to the source line S1 so that the unselected memory cell (T12) is not erroneously read and the read margin is wide.

[0005]

However, in the conventional semiconductor memory device having the non-volatile memory cell as shown in FIG. 25, the memory cell of the memory cell is controlled even if the write and erase operations are controlled by performing the verify operation. It is conceivable that the variation of the characteristics is large and the memory cell is depleted (threshold voltage is 0 V or less). That is, as the semiconductor memory device becomes highly integrated, the threshold value varies to some extent due to variations in the impurity concentration and variations in the dimensions of each part in the manufacturing process of the semiconductor memory device, and errors in dimensions and the like increase, resulting in variations. Tends to increase.

Further, the threshold voltage of a non-volatile memory transistor (in particular, a non-volatile memory transistor having a stack type floating gate) has a characteristic that it changes depending on the drain voltage. This is shown in Figure 2.
7, FIG. 28 and the basic equation of capacitance-potential will be used for description. FIG. 27 schematically shows a cross section of a transistor having a stack type floating gate structure. FIG.
(A) and (b) show drain current Id-gate voltage Vg characteristics of a prototype nonvolatile memory transistor having a stack floating gate structure and a normal MOS transistor, respectively. In FIG. 27, 61 is a floating gate, 62 is a control gate, 63 is a drain, 64 is a source, 1 is a semiconductor substrate, and an insulating film is omitted for convenience. Cc is a floating gate-control gate capacitance, Cd is a floating gate-drain capacitance, Cs is a floating gate-source capacitance, Cb is a floating gate-semiconductor substrate capacitance, Vcg is an applied voltage to the control gate 62, and Vfg is The potential of the floating gate 61, Vd is the drain voltage, Vs is the source voltage, and Vb is the semiconductor substrate 1.
Is the potential of. As shown in FIG. 28B, a normal MO
The drain voltage Vd of the S transistor is 0.1 V and 2.0 V.
The threshold voltage VTfg as seen from the floating gate is constant with almost no dependence on the drain voltage so that there is almost no difference in the threshold voltage between and. On the other hand, as shown in FIG. 27, the floating gate 61 is capacitively coupled with the drain 63, and when the voltage Vd is applied to the drain 63, the potential Vfg of the floating gate 61 is as shown in the following capacitance-potential basic relational expression. , Rd Vd only (rd
= Cd / Ct). Also, the control gate 62
The threshold voltage VTcg seen from above is lowered by rd Vd / r due to the drain voltage Vd. As a result, as shown in FIG. 28A, in the nonvolatile memory transistor having the stack type floating gate structure, the drain voltage Vd
The threshold voltage is lower by about 0.3 V (usually 0.2 to 0.4 V) in the case of 2.0 V than in the case of 0.1 V.

(Capacitance-potential basic relational expression) Ct = Cc + Cd + Cs + Cb r = Cc / Ct, rd = Cd / Ct, rs = Cs / Ct,
rb = Cb / Ct Vcg = (Vfg-rd Vd-rs Vs-rb Vb) / r That is, Vfg = rVcg + rd Vd + rs Vs + rb Vb VTcg0 = (VTfg-rs Vs-rvVg / rsVt-rbbbb / bbbb) r As described above, the threshold value of each nonvolatile memory cell arranged in the memory cell array varies depending not only on the uneven distribution of the impurity concentration in the manufacturing process but also on the voltage application state to each part. , As a whole, it is distributed within a certain range. FIG. 26 schematically shows a threshold voltage distribution state in each such nonvolatile memory cell. The horizontal axis represents the threshold value of the nonvolatile memory, and the vertical axis represents the frequency. NO
In order to prevent erroneous reading from occurring in the R-type memory cell array, the threshold voltage is controlled to a high level by a verify operation or the like, and the threshold value of each memory cell is set in advance to a high threshold state (“0”). (State), solid lines AB in FIG.
In the low threshold state (“1” state), the solid line C in FIG.
It is set so that the distribution states shown in FIGS. In the read operation, as already explained,
Since the threshold voltage is lowered (0.2 to 0.4 V) depending on the drain voltage Vd, the threshold voltage of the memory cell has a distribution state shown by broken lines A'to B'and C'to D '.

On the other hand, in the low threshold state, depending on the sensitivity of the sense amplifier and the transconductance of the memory cell, the read current flowing when the minimum value Vccmin of the read voltage Vcc is applied to the control gate of the memory cell. In order to secure (about 50 μA or more), the threshold value of the memory cell must be lower than Vccmin by about 1.0 V (see point B ′ in FIG. 26). Further, in the NOR type memory cell array, the sum of leak currents of the non-selected memory cells connected to one bit line is read current (about 50 μA or more) so as to prevent erroneous reading by the non-selected memory cells. The threshold voltage of the memory cell in the low threshold state must be about 0.5 V or more (see point A'in FIG. 26). Is, for example, Vcc
Is 3.0 V and Vccmin is 2.7 V, the potential difference between points A'and B in FIG. 26 must be 1.2 V or less, and the decrease in threshold due to drain voltage is 0.2 to 0.4 V.
Assuming that, the width of the threshold distribution (A to B) due to the verify operation or the like must be 1.0 V or less. The above numerical values are the minimum necessary numerical values, and it is necessary to consider the control margin of the verify operation in the actual non-volatile memory. Therefore, the control of the threshold voltage distribution state of the nonvolatile memory is required to be particularly strict in the low threshold state. Moreover, when highly integrated,
The operating voltage of the semiconductor memory device tends to be lowered in order to reduce power consumption in terms of the need to suppress heat generation. Therefore, when the read voltage Vcc becomes lower, it becomes necessary to tighten the control of the threshold distribution more and more. For example, when the read voltage Vcc is about 3.0 V, even a decrease in the threshold value due to the drain voltage cannot be ignored.
Due to the overlapping reasons, the probability of excessive depletion in some memory cells of the semiconductor memory device is increasing.

On the other hand, the memory cell in the high threshold state is turned off even when the maximum value Vccmax of the read voltage Vcc is applied.
Must be in a state. Therefore, the leak current must be sufficiently smaller than the read current (about 50 μA or more) and must be higher than Vccmax by about 0.5 V or more (see point C ′ in FIG. 26). Memory cells in the high threshold state have no other strict limiting conditions, so
In the case of considering only the read operation, the higher the threshold voltage is, the more advantageous it is, and the control margin of the threshold voltage is increased.

Considering the write operation and the improvement in the number of times of writing and erasing, it is preferable to make the threshold voltage as low as possible even in the high threshold state. But,
If only the read operation is considered, it is not necessary to lower the threshold value. Since the present invention is concerned with read operations, it is assumed here that memory cells in the high threshold state are more advantageous at higher threshold voltages.

In the conventional method for reading a semiconductor memory device having a nonvolatile memory cell as shown in FIG.
Since the read intermediate potential is applied to the selected bit line connected to the drain of the memory cell, the threshold voltage of the non-selected memory cell connected to the selected bit line is also lowered, resulting in excessive depletion. The possibility arises. In particular, in the memory cell (T12) and memory cell (Tm2) shown in FIG. 25, the read intermediate potential is applied not only to the drain but also to the source, and the threshold voltage seen from the floating gate rises due to the substrate bias effect. But,
The substrate bias effect is about 0 when the read intermediate potential is 1.0 V.
It is about 1 V, and is canceled by the decrease in the threshold voltage due to the source voltage Vs, and the threshold voltage seen from the control gate is further decreased.

Due to the above reasons, for example, when the non-selected memory cell (T12) connected to the selected bit line B2 shown in FIG. 25 is excessively depleted, the memory cell (T22) in the low threshold state is ), A current flows through the bit line B2 and the potential of the bit line B2 drops slightly. At that time, a current flows from the source line S1 of the read intermediate potential to the bit line B2 through the memory cell (T12), and the potential of the bit line B2 is returned to the read intermediate potential. If the potential of the bit line B2 does not change, the sense amplifier SA2 connected to the bit line B2 determines that the memory cell (T22) in the low threshold state is in the high threshold state, resulting in an erroneous read. There is a risk. In addition, it is difficult to improve the mutual conductance necessary for speeding up reading.

A first object of the present invention is to prevent erroneous reading by preventing a threshold voltage drop in a non-selected memory cell during reading.

A second object of the present invention is to reduce power consumption by preventing charging / discharging of non-selected source lines during reading.

A third object of the present invention is to speed up the reading operation while preventing erroneous reading and reducing power consumption.

[0016]

In order to achieve each of the above objects, the present application employs the means shown in the inventions of claims 1 to 11.

Specifically, the means taken by the invention of claim 1 is as follows.
A memory cell array in which non-volatile memory cells each having at least a transistor including a gate, a source, and a drain and a capacitor are arranged in a matrix, and a plurality of transistors connected to the gates of the respective transistors arranged in the row direction of the memory cell array. Word lines, a plurality of bit lines connected to the drains of the transistors arranged in the column direction of the memory cell array, and a plurality of sources connected to the sources of the transistors arranged in the row direction of the memory cell array. Line, a decoder circuit for selecting the word line, a decoder circuit for selecting the bit line, and a decoder circuit for selecting the source line. At least one source line of the plurality of source lines is selected by the decoder circuit, and A word line of the same address as the nonvolatile memory cell connected to the source line is selected by the decoder circuit, the potential of the selected word line is set to a predetermined potential, and the potential of the bit line is set to a first potential. Then
A second voltage in which the potential of the selected source line is higher than the first potential
This is a method of setting the potential and reading the stored contents of at least one memory cell connected to the selected source line and the selected word line.

The measures taken by the invention of claim 2 are as follows:
In the invention described above, when the stored content of the memory cell is read out, the first potential is set to substantially the ground potential.

The means taken by the invention of claim 3 is the method of claim 1.
Alternatively, in the second aspect of the invention, when the stored content of the memory cell is read, the potential of the non-selected source line is set to the first potential.

The means taken by the invention of claim 4 is defined by claim 1.
Alternatively, in the second aspect of the invention, when the stored content of the memory cell is read, the potential of the non-selected source line is set to a floating state.

According to a fifth aspect of the present invention, in the invention of the first, second, third or fourth aspect, all the above-mentioned means connected to the selected source line when reading the stored contents of the memory cell. This is a method of collectively reading the nonvolatile memory cells.

According to a sixth aspect of the present invention, in the method of the first, second, third or fourth aspect of the present invention, when the stored content of the memory cell is read, the potential of the non-selected bit line is set to a floating state. is there.

According to a seventh aspect of the present invention, in the invention of the first, second, third, fourth or fifth aspect, the potential of the selected source line is set at the time of reading in the write verify operation or the erase verify operation. This is a method of setting the potential lower than the potential of the selected source line in the read operation.

According to the present invention of claim 8, in the invention of claim 1, 2, 3, 4, 5, 6 or 7, the non-volatile memory cell has a capacitance between the source and the capacitance section. This is a method of using a non-volatile memory cell formed so that the coupling ratio is higher than the capacitive coupling ratio between the drain and the capacitance section.

According to a ninth aspect of the present invention, in the invention of the first, second, third, fourth, fifth, sixth or seventh aspect, as the memory transistor in the non-volatile memory cell,
This is a method of using a memory transistor in which the capacitor portion has a split gate structure.

According to a tenth aspect of the present invention, in the invention of the ninth aspect, the capacitor portion of the memory transistor having the split gate structure is provided with a region overlapping with the source region of the memory transistor. Is the way.

According to the invention of claim 11, in the invention of claim 1, 2, 3, 4, 5, 6 or 7, the threshold voltage of the memory cell in the "1" state is set negative in advance. Incidentally, this is a method in which all the word lines are set to the ground potential when the stored contents of the memory cells are read out.

[0028]

With the above construction, the following actions are obtained in the invention of each claim.

According to the invention of claim 1 or 2, in the semiconductor memory device having the memory cell array structure in which the non-volatile memory cells are arranged in a matrix, when the stored contents of the memory cells are read, the potential of the bit line is selected. Since the potential is set lower than the potential of the source line, a decrease in the threshold voltage depending on the drain voltage is suppressed in each unselected memory cell connected to the selected bit line. Therefore, erroneous reading due to the error motion of the non-selected memory cell is suppressed.

According to the invention of claim 3, in addition to the operation of the invention of claim 1, since the non-selected source line is equal to the potential of the bit line, even if the non-selected memory cell is depleted, the bit line from the non-selected source line is changed. Almost no current flows to. Therefore, erroneous reading is surely prevented.

In the fourth aspect of the invention, since the non-selected source line is held in the floating state when the stored contents are read out, charging / discharging of the source line is suppressed, and the power consumption is reduced accordingly.

According to the fifth aspect of the invention, since all the memory cells on the selected source line are read out at once, the voltage is applied only to the selected source line and the selected word line at the time of starting reading, and the voltage is applied to the selected source line and the selected word line. The power consumption is extremely low, and the power consumption will be further reduced.

According to the sixth aspect of the invention, since the potential of the non-selected bit line becomes floating at the time of reading the memory cell, power consumption due to charge / discharge on the bit line is suppressed.

According to the invention of claim 7, the threshold voltage is controlled to be higher during the verify operation by lowering the source voltage during the verify operation during the read operation than during the normal read operation. The threshold is controlled lower. Therefore, the threshold voltage of the non-selected memory cell remains high, but the selected memory cell can be set to the threshold voltage suitable for the read operation, and the threshold value of the "1" state at the time of verify is set. The upper limit of the voltage can be set high, and a large threshold design margin of the semiconductor memory device can be secured.

According to the invention of claim 8, since the structure is such that the threshold voltage is greatly reduced by the source voltage,
The source voltage can be set to a high voltage so that soft write does not occur, and the read operation can be speeded up by increasing the mutual conductance of the memory cell.

According to the ninth or tenth aspect of the invention, since the nonvolatile memory cell is configured to use the memory transistor having the split gate structure and the floating gate provided on the source side, the capacitance coupling ratio of the floating gate on the source side is The capacitance coupling ratio on the drain side is substantially zero, and the threshold voltage drop due to the source voltage can be increased.

According to the eleventh aspect of the present invention, since the read voltage is set to the ground voltage and the stored content of the memory cell is read, the potential of the word line does not fluctuate during the read and the power consumption is further reduced. It

[0038]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) The first embodiment of the present invention will be described below.
A method for driving a semiconductor memory device according to an embodiment will be described with reference to FIGS.
Will be described with reference to. The block circuit diagram of the semiconductor memory device according to this embodiment is the same as the block circuit diagram of the conventional nonvolatile semiconductor memory device shown in FIG. The structure itself of the memory cell array of the semiconductor memory device shown in FIG. 1 is the same as the structure of the memory cell array of the conventional nonvolatile semiconductor memory device shown in FIG.
That is, the memory cells having the respective transistors T11 to Tmn are arranged in a matrix of m rows and n columns, the memory cells (T11) to (Tmn), the word lines W1 to Wm, the bit lines B1 to Bn, and the sources. The lines S1 to Sm, the column selecting transistors ST1 to STn, the sense amplifiers SA1 to SAn, the row decoders RD1 to RDm, the column decoders, and the source decoders SD1 to SDm are similar to the structure shown in FIG. Is the same. The sense amplifiers are arranged on all the bit lines B1 to Bn.

The reading method in this embodiment will be described with reference to FIG. Here, the memory cells (T2) connected to the common word line W2 and source line S2 are connected.
It is assumed that 1) to (T2m) are collectively read, and it is assumed that the memory cells (T11) and (T12) are depleted. The potential of the selected word line W2 is set to the read power supply voltage Vcc (for example, 5V), and the potential of the non-selected word lines W1, ..., Wm is set to the ground potential Vss (for example, 0V). At the same time, the potential of the selected source line S2 is set to the read intermediate potential Vrm (for example, 1 V), and the potential of the non-selected source lines S1, ..., Sm is set to the ground potential Vss. Further, the potentials of all the bit lines B1 to Bn are set to the ground potential Vss via the sense amplifier. In reality, since the sense amplifiers are connected to the bit lines B1 to Bn, the potentials of the bit lines B1 to Bn slightly fluctuate from the ground potential Vss. It is assumed that the potentials B1 to Bn are constant voltages (ground potential Vss).

When the potentials of the respective parts in the read operation are set as described above, for example, if the memory cell (T22) is in the "0" state (high threshold state), the memory cell (T2
2) does not operate and does not carry current. In addition, the memory cell (T1
2) has excessive depletion, but bit line B2
And the non-selected source line S1 have the same potential (ground potential Vss)
Therefore, no current flows in the memory cell (T12). Therefore, no current flows through the bit line B2, and it can be detected that the memory cell (T22) is in the "0" state. on the other hand,
For example, if the memory cell (T21) is in the "1" state (low threshold value state), the memory cell (T21) operates and a current flows, and a current flows in the bit line B1 and the memory cell (T21) is "1". "It can detect that it is in a state. Here, although the memory cell (T11) is depleted, the current flowing by operating the memory cell (T21) does not flow out to the source line S1 via the path P11 in which the memory cell (T11) is arranged. The threshold voltage of the memory cell (T11) is controlled to some extent.

Therefore, in the read method of this embodiment, the memory cells (T21) to (T2m) can be read in a lump by applying the read potential only to the word line W2 and the source line S2. In that case, compared with the read operation of the conventional semiconductor memory device in which the nonvolatile memory cells are arranged, when the read frequency is high or the read operation at the time of verification, the number of wirings to be charged / discharged is small, so that the power consumption can be reduced.

Further, since the bit line and the non-selected source line are set to the ground potential Vss, there is no threshold drop due to the drain voltage in the non-selected memory cell, and there is an error due to the threshold drop due to the drain voltage. No read occurs.

In the above read operation, the read intermediate potential Vrm is applied to the selected source line, so that the threshold voltage of the selected memory cell is lowered by the source voltage. However, if the selected memory cell is in the "1" state, there is no problem, and rather the operating current of the memory cell increases and the reading speed becomes faster. Furthermore, the read intermediate potential Vrm applied to the source
If the value is set to be slightly higher than that in the above embodiment, the mutual conductance of the memory cell can be increased and the reading speed can be increased. On the other hand, if the selected memory cell is in the “0” state (high threshold state), the threshold voltage of the selected memory cell may decrease due to the source voltage and current may flow. It is possible to set the lower limit of the threshold voltage of the cell to a sufficiently high value so that current does not flow even if the threshold voltage is lowered by the source voltage. It is known that in the NOR type non-volatile memory, the threshold voltage in the “0” state has a lower limit but not an upper limit in particular, and there is a margin in characteristic variation.

Further, in the read method of the above-mentioned embodiment, the batch read for reading the data of all the memory cells connected to the selected word line is performed, but it is also possible to read one memory cell. . For example, when reading from the memory cell (T22), each word line W1
.About.Wm and the potentials of the source lines S1 to Sm are the potentials shown in FIG. 1, and the potential of the selected bit line B2 is, for example, the ground potential Vss.
(0 V) while unselected bit lines B1, B3 to Bn
It suffices to turn off between the voltage supply source and the voltage supply source to make the potential floating. Also in that case, unlike the conventional read method, the potential of the selected bit line B2 is as low as the ground potential Vss, so that the reduction of the threshold voltage is suppressed and "erroneous read can be prevented. As in the example, when performing batch reading of the selected word line, there is no wasteful charging / discharging, and there is an advantage that power consumption can be reduced.

The lower limit of the threshold voltage of the memory cell in the "0" state is set to be sufficiently high so that current does not flow even if the threshold voltage is lowered by the source voltage. If the potential of the selected source line is set so as to increase the threshold voltage drop of the selected memory cell due to the source voltage, the operating current of the memory cell in the “1” state (low threshold state) increases and the reading speed is increased. You can Such a condition can be realized by increasing the capacitive coupling ratio between the floating gate and the source and increasing the source voltage to such an extent that soft write does not occur. As a structure for increasing the capacitive coupling ratio between the floating gate and the source, there is a structure as shown in FIG. 2 or 3. 2 and 3, 1 is a semiconductor substrate, 2 is a gate insulating film, 3
Is a floating gate electrode, 4 is a capacitive insulating film, 5 is a gate electrode, 8 is a drain region, and 9 is a source region.
In the example shown in FIG. 2, the source region 9 and the drain region 8 are asymmetrical, and the source region 9 largely overlaps the region directly below the floating gate 3.
Further, in the example shown in FIG. 3, it has a split gate structure, and the floating gates 3 are located deviated to the source region 9 side.

The lower limit of the threshold voltage of the memory cell in the "0" state may not be set sufficiently high depending on the condition of the write / erase operation, in which case the threshold of the selected memory cell by the source voltage may be set. The decrease in value is not preferable. Therefore, if the structure in which the capacitive coupling ratio between the floating gate and the source region is set to almost 0 is applied, the threshold voltage of the memory cell is hardly reduced by the source voltage. For that purpose, as shown in FIG. 4, an offset region 29 of the same conductivity type as that of the semiconductor substrate 1 may be provided between the source region 9 and the region immediately below the floating gate electrode 3. However, in the figure, 28 is a sidewall.

Although not shown, the floating gate may be located on the drain side in a split gate structure as shown in FIG.

In the driving method of the first embodiment, the potential of the selected source line is read out and the intermediate potential Vrm (for example, 1 V).
However, the potential of the selected source line may be the read power supply voltage Vcc.

Further, in the driving method of the first embodiment, the potential of the selected bit line is set to the ground potential Vss via the sense amplifier.
However, when the sense amplifier requires the reference potential, the potential of the selected bit line may be set higher than the ground potential Vss and lower than the potential of the selected source line.

Although the nonvolatile memory of this embodiment provided with a floating gate was used, MNOS
A non-volatile memory transistor of a type in which electrons are injected into an insulating film on a channel region of a MOS transistor typified by a (metal nitride oxide semiconductor) type memory cell to change the threshold voltage may be used.

Next, the verifying method in this embodiment will be described with reference to FIG. FIG. 5 is a schematic diagram of the threshold voltage distribution of the memory cell, where the horizontal axis shows the threshold value of the nonvolatile memory and the vertical axis shows the frequency. Generally, in a NOR type non-volatile memory, verification is performed in a write or erase operation that transits to a "1" state. Here also, a case will be described in which verification is performed in the operation in which the memory cell transits to the "1" state.

Generally, in the verify operation, a pulse is applied so that the memory cell gradually transitions under a bias condition in which the memory cell transits to the "1" state, and each time a desired memory cell is detected by the sense amplifier, the "1" state is detected. Check that If the desired memory cell is in the "1" state, the write or erase operation is completed, and the desired memory cell is in the "1" state.
If it is not in the state, the pulse is applied again, and the detection of the desired memory cell by the sense amplifier is repeated. In this embodiment, detection of a desired memory cell by the sense amplifier is
Although the same reading method as that already described with reference to FIG. 1 is performed, the voltage of the selected source line is made as low as possible (for example, 0.5 V) at the time of verification so that it can be detected by the sense amplifier. By the verification of the present embodiment, the distribution of the threshold voltage of the memory cell becomes as shown by the solid lines A to B and C to D in FIG. That is, the lower limit potential of the “1” state is the potential of the point A, the upper limit potential is the potential of the point B, the lower limit potential of the “0” state is the potential of the point C, and the upper limit potential is the potential of the point D. It is set.

On the other hand, the source voltage in the normal read is set to the read intermediate potential Vrm (1V) higher than the read source voltage at the time of verify, as shown in FIG. As already shown in FIGS. 27 and 28 and the capacitance-potential basic relational expression, when the source voltage is increased, the threshold voltage of the memory cell is lowered. At that time, as shown by broken lines A'-B 'and C'-D' in FIG. 5, the threshold voltage distribution of each memory cell has a lower limit potential of the point A'in the "1" state in normal reading. Potential, the upper limit potential is the potential at point B ', "0"
The lower limit potential of the state is the potential at the point C ′, and the upper limit potential is the potential at the point D ′. Here, only the selected memory cells have the distribution shown by the broken line in FIG. 5, and the unselected memory cells remain in the distribution state shown by the solid line. The lower limit potential of the threshold voltage in the "1" state is set to prevent unselected memory cells from being erroneously read, and the upper limit potential of the threshold voltage in the "1" state is set to secure the read current of the selected memory cell. It is set. In view of this condition, the distribution of the threshold voltage in the "1" state in the conventional NOR type nonvolatile memory must be controlled between point A and point B'as shown by the dotted line in FIG. On the other hand, in the verification of this embodiment, control may be performed between the points A and B on the solid line in FIG.
That is, in FIG. 26, the voltage between 0 and A'must be 0.5 V or more, but in this embodiment, the voltage between 0 and A should be 0.5 V or more, even if the potential at the point A'becomes negative. Good.
Therefore, there is an advantage that the margin can be increased.

The threshold voltage is set excessively high so that the operating current does not flow even at the lower limit potential (potential at the point C ′) of the threshold voltage in the “0” state in normal reading.

Further, in the reading in the above verification method, the potential of the selected source line is set to 0.5 V, for example, but it is not limited to this.

Further, in the reading in the verify method, the potential of the selected bit line is set to Vss via the sense amplifier, but when the sense amplifier requires the reference potential, the potential of the selected bit line is set to the ground potential Vss.
It may be made larger and smaller than the potential of the selected source line.

In this embodiment, the nonvolatile memory provided with the floating gate was used.
A non-volatile memory transistor of a type in which electrons are injected into an insulating film on a channel region of a MOS transistor typified by a (metal nitride oxide semiconductor) type memory cell to change the threshold voltage may be used.

(Second Embodiment) Next, a second embodiment of a method for floating the potential of the non-selected source line at the time of reading will be described with reference to FIGS. 6 to 9. However, FIGS. 7 and 8 are a circuit diagram and a timing chart for explaining the read operation in the second embodiment, but FIGS. 6 and 7 show the first embodiment in order to make a comparison with the second embodiment. 6A and 6B are a circuit diagram and a timing chart for explaining a read operation, that is, an operation in the case where the potential of the non-selected source line is not floated. The block circuit diagram of the semiconductor memory device according to this embodiment is the same as the block circuit diagram of the conventional nonvolatile semiconductor memory device shown in FIG. The overall structure of the memory cell array portion of the semiconductor memory device according to the present embodiment is the same as the structure shown in FIG. 1 according to the first embodiment, and the description thereof will be omitted.

FIG. 6 shows the memory cells (T11) and (T21) in the memory cell array shown in FIG. 1, the bit line B1,
Source lines S1 and S2, source decoders SD1 and SD2,
FIG. 3 is a circuit diagram showing details of a sense amplifier SA1 and a dummy cell (Td) portion. Source decoder SD1, SD2
Inside, MOS transistors TR1m and TR1m for supplying the read intermediate potential Vrm to the source lines S1 and S2, respectively.
TR2m and MOS transistors TR1s and TR2s for supplying the ground potential Vss to the source lines S1 and S2 are arranged. Then, the MOS transistors TR1s, TR
Signals SDO1 and SDO2 are supplied to the gate of 2s, and signals XDEC1 and XDEC2 are supplied to the gates of the MOS transistors TR1m and TR2m, respectively. Note that this structure is simplified in order to explain the timing of the potential applied to the source line and is not limited to such a structure.

NB is a bit line node and is connected to the bit line B1 via a selection transistor ST1a controlled by a signal YSG. ND is a dummy bit line node, and is connected to the dummy bit line DBL via a selection transistor ST1b controlled by a signal YSG. TRdm is a MOS transistor for supplying the read intermediate potential to the drain of the dummy cell (Td) and is controlled by the signal DXDEC. TRdr is a MOS transistor for supplying the ground potential to the source of the dummy cell (Td) and is controlled by the signal RESET.

Next, the read operation in the first embodiment will be described with reference to the timing chart of FIG. FIG. 7 shows a change in each signal when the memory cell (T11) is read, then the memory cell (T21) is read, and then the memory cell (T11) is read again. As a preliminary operation, the signal YSG is set to High, the signal RESET is set to High for a short time while the selection transistors ST1a and ST1b are kept conductive, and the potentials of the bit node NB and the dummy bit line node DB are reset to the ground potential Vss. To do. Next, at the time of reading, the memory cell (T
11) to (Tm1) are selected and the potential of the non-selected source line is set to the ground potential Vss, while the potential of the selected source line is set to the read intermediate potential Vrm. For example, when reading the memory cell (T11), the signal SD01 is set to Low.
Then, after the signal SDO2 is set to High, the signal XDEC1 is set to Low and the signal XDEC2 is held at High. At the same time that the signal XDEC1 is set to Low, the selected word line W1 is set to High and the non-selected word line W2 is held at Low. At this time, if the selected memory cell (T11) is in the "1" state (low threshold state), the bit line node N
The potential of B fluctuates (about 200 mV) and is in the "0" state "
In the (high threshold state), the potential of bit line node NB does not change. At the same time, the dummy cell (Td) holds the dummy cell bit line node ND at the reference potential. Then, in consideration of the timing when the potential difference between the bit line node NB and the dummy cell bit line node ND exceeds a certain level, the signal YSG is set to Low in order to disconnect the connection between the bit line B1 and the sense amplifier SA1.
The potential of the selected word line W1 is set to Low, and the signal XDEC1 is set to H.
The signal SDO1 is set to Low. Shortly thereafter. To activate the sense amplifier SA1, the signal ISAE goes low.
ow, thereby amplifying the potential difference between the bit line node NB and the dummy cell bit line node ND. The same applies to the case of selecting and reading the memory cell (T21), and the description thereof will be omitted.

Next, FIG. 8 shows the memory cells (T11) and (T21) in the memory cell array in the second embodiment, the bit line B1, the source lines S1 and S2, and the source decoder SD1.
, SD2, sense amplifier SA1 and dummy cell (Td
3] is a circuit diagram showing in detail the part of FIG. In the source decoders SD1 and SD2, there are source lines S1 and S2, respectively.
Although the MOS transistors TR1m and TR2m for supplying the read intermediate potential Vrm are arranged at, the MOS transistors TR1s and TR2s for supplying the ground potential Vss to the source lines S1 and S2 are not arranged. That is, the potential of the non-selected source line is set to be floating.

Next, the read operation in the second embodiment will be described with reference to FIG. FIG. 9 shows a change in each signal when the memory cell (T11) is read, the memory cell (T21) is read next, and then the memory cell (T11) is read again. As a preliminary operation, signal YSG
Is set to High, and the signal RESET is set to High for a short time while the selection transistors ST1a and ST1b are kept conductive.
The bit node NB and the dummy bit line node DB
And the potentials of and are reset to the ground potential Vss. Next, at the time of reading, any one of the memory cells (T11) to (Tm1) is selected and the potential of the non-selected source line is set to the ground potential V.
Meanwhile, the potential of the selected source line is set to the read intermediate potential Vrm while being set to ss. For example, when reading the memory cell (T11), the signal XDEC1 is set to Low and the signal XDEC2 is set.
Is held at High. At the same time that the signal XDEC1 is set to Low, the selected word line W1 is set to High and the non-selected word line W2 is held at Low. At this time, the selected memory cell (T11) is in the "1" state (low threshold state)
Then, the potential of the bit line node NB fluctuates (about 200 mV
If it is "0" state (high threshold state), the potential of the bit line node NB does not change.At the same time, the dummy cell (Td) causes the dummy cell bit line node N
D is held at the reference potential. Then, in consideration of the timing when the potential difference between the bit line node NB and the dummy cell bit line node ND exceeds a certain level, the connection between the bit line B1 and the sense amplifier SA1 is cut off.
The signal YSG is set to Low, the potential of the word line W1 is set to Low, and the signal XDEC1 is set to High. Immediately after that, in order to activate the sense amplifier SA1, the signal ISAE is set to Low,
As a result, the potential difference between the bit line node NB and the dummy cell bit line node ND is amplified. Memory cell (T21)
The same applies when selecting and reading.

Next, the read operation of the first embodiment and the second embodiment will be compared. In the reading method of the first embodiment, the potentials of all the source lines are reset to the ground potential by the MOS transistors TR1s, TR2s, etc., so that the source lines are charged and discharged, and the power is consumed accordingly.

On the other hand, in the second embodiment, the potentials of the non-selected source lines are all held in the floating state,
In principle, charging / discharging of the source line does not occur. However, if, for example, one or more depleted memory cells are connected to the source line S2, the charge on the source line S2 is discharged to the bit line through the depleted memory cells at reset and the ground potential It is reset to Vss. Therefore, when the memory cell on the source line S2 is read again, the source line S2 must be read from the ground potential Vss and charged to the intermediate potential Vrm, and the power is additionally consumed correspondingly. However, for example, when all the memory cells connected to the source line S1 are not depleted, the charge of the source line S1 is not discharged to the bit line at the time of resetting, and it is assumed that the potential is lowered to some extent due to a leak current or the like. Is also read out and held at the intermediate potential Vrm. Therefore, when the memory cell on the source line S1 is read again, the charge and discharge of the source line are extremely small, so that the power consumption can be reduced.

(Third Embodiment) Next, a semiconductor memory device and a method of driving the same according to a third embodiment will be described with reference to FIGS. The block circuit diagram of the semiconductor memory device according to this embodiment is the same as the block circuit diagram of the conventional nonvolatile semiconductor memory device shown in FIG. FIG. 10 shows the memory cell array portion of the semiconductor memory device in this embodiment, and the basic structure is the same as the structure shown in FIG. 1 in the first embodiment. That is, memory cells each including the transistors T11 to Tmn are arranged in m rows and n.
The memory cells (T11) are arranged by being arranged in a matrix of columns.
(Tmn), word lines W1 to Wm, bit lines B1 to Bn,
Source lines S1 to Sm, column select transistors ST1 to
STn, sense amplifiers SA1 to SAn, row decoder R
D1 to RDm, column decoder, source decoder SD1
The structure and arrangement of SDm to SDm are shown in FIG.
It has the same structure as shown in.

Here, as a feature of this embodiment, in addition to the configuration shown in FIG. 1, a current from the source line side to the transistor side is applied between the sources of the transistors T11 to Tmn and the source lines S1 to Sm. Diode D11 that allows only distribution ~
Dmn are arranged respectively. By the diodes D11 to Dmn, the currents flowing from the sources of the transistors T11 to Tmn in the drain direction (forward direction) in the paths P11 to Pmn are substantially equal to the operating currents of the transistors T11 to Tmn, and the drains to the sources of the transistors T11 to Tmn. Direction (reverse direction)
A current characteristic is obtained in which the current flowing through is almost cut off or reduced. That is, this diode D
11 to Dmn are different-direction resistance portions whose resistance values change depending on the direction of the current. However, although the different direction resistance part does not necessarily have the function as a diode that the current value in the reverse direction is almost completely cut off, it may include the one in which the reverse direction current value is smaller than that in the forward direction. In the following examples, all are expressed as diodes for convenience.

Next, the reading method in this embodiment will be described with reference to FIG. Here, the case of collectively reading the word line W2, that is, the memory cells (T21) to (T2m) will be described, and it is assumed that the memory cells (T11) and (T12) are depleted. The potential of the selected word line W2 is read out and the power supply voltage Vcc
(For example, 5V), and the potentials of the non-selected word lines W1 and Wm are set to the ground potential Vss (for example, 0V). At the same time, the potential of the selected source line S2 is set to the read intermediate potential Vrm (for example, 1 V), and the potentials of the non-selected source lines S1 and Sm are set to the ground potential Vss. Further, the potentials of the bit lines B1 to Bn are set to the ground potential Vss via the sense amplifier.
In reality, since the sense amplifiers are connected to the bit lines B1 to Bn, the potentials of the bit lines B1 to Bn slightly fluctuate from the ground potential Vss. It is assumed that the potentials B1 to Bn are constant voltages (ground potential Vss). For example, memory cell (T22)
If is "0", the memory cell (T22) does not operate and no current flows. Although the memory cell (T12) is excessively depleted, no current flows through the memory cell (T12) because the potentials of the bit line B2 and the source line S1 are the same and Vss. Therefore, no current flows through the bit line B2, and it can be detected that the memory cell (T22) is in the "0" state. On the other hand, for example, if the memory cell (T21) is in the "1" state, the memory cell (T21) operates and a current flows, a current flows through the bit line B1, and the memory cell (T2)
It can detect that 1) is in the "1" state.

Here, the memory cell (T11) is depleted, but in this embodiment, unlike the first embodiment,
The diode D11 prevents the current flowing in the bit line B1 from operating the memory cell (T21) from flowing out to the source line S1 via the memory cell (T11). Further, since the potentials of the non-selected source line S1 and all bit lines are equal to Vss, it is difficult for current to flow. Diode D11
Although a small amount of leak current flows even with a reverse bias, the method of collectively reading all the memory cells connected to the word line of the embodiment can suppress the above leak current and reduce power consumption.

As described above, the word line W2 and the source line S
Memory cells (T21) to (T2m) can be read in a lump by applying a read potential only to 2.
When the reading frequency is high or in the reading operation at the time of verification, the number of wirings charged and discharged is smaller than that of the conventional nonvolatile semiconductor memory device, and the power consumption can be reduced.

Since the bit line and the non-selected source line are at the ground potential, the threshold voltage is not lowered by the drain voltage in the non-selected memory cell, and erroneous reading due to the threshold voltage reduction by the drain voltage is not caused. Absent.

The read intermediate potential is applied to the selected source line, and the threshold voltage of the selected memory cell is lowered by the source voltage. The threshold voltage decrease of the selected memory cell due to the source voltage may be positively utilized to increase the read operation speed, and the threshold voltage decrease of the selected memory cell due to the source voltage may be prevented. Can be applied similarly to the first embodiment. These have already been described in the first embodiment, and description thereof will be omitted.

Next, a method for reading the word line with the potential of the word line kept at the ground potential Vss in this embodiment will be described. The read method is the read method shown in FIG. 10 in which the potentials of all the word lines W1 to Wm are grounded to the ground potential Vss (for example, 0 V), and the drawings are omitted. If the threshold voltage of the memory cell in the “1” state of this embodiment is set to a negative value in advance, the memory transistor sets the word line potential to the ground potential Vss (for example, 0V),
In the reading method shown in FIG. 10, the potentials of all the word lines W1 to Wm are set to the ground potential Vss (for example, 0V) because current is passed in the "1" state and current is not passed in the "0" state. Even if the state of the memory cell is detected by detecting the bit line current, the data can be read. That is, the potential of the selected source line S2 is read out and the intermediate potential Vrm (for example, 1
V), the potentials of the non-selected source lines S1, ..., Sm are set to the ground potential Vss, and the potentials of the bit lines are set to the ground potential Vss via the sense amplifier to select the memory cell selected by the source line. It is possible to read (T21) to (T2m) in a batch. Therefore, the word line potential does not fluctuate during reading, and further lower power consumption and lower power supply voltage can be achieved.

In the reading method of the third embodiment, the potential of the selected source line is read out and the intermediate potential Vrm (for example, 1 V).
However, the potential of the selected source line is the read power supply voltage Vcc.
It may be.

Although the potential of the bit line is set to the ground potential Vss via the sense amplifier in the reading method of the third embodiment, the potential of the selected bit line is grounded when the sense amplifier requires the reference potential. It may be set higher than the potential Vss and lower than the read intermediate potential Vrm.

In the read operation in the above embodiment, the read intermediate potential is applied to the selected source line, and the threshold voltage of the selected memory cell is lowered by the source voltage. The threshold voltage decrease of the selected memory cell due to the source voltage may be positively utilized to increase the read operation speed, and the threshold voltage decrease of the selected memory cell due to the source voltage may be prevented. Can be applied similarly to the first embodiment. These have already been described in the first embodiment, and description thereof will be omitted.

There are various structures of the semiconductor memory device having the different direction resistance portion in the present embodiment. Hereinafter, the structural example and the manufacturing process thereof will be described.

FIGS. 11A to 11C and FIGS. 12A to 12C.
(C) shows a manufacturing process of the memory cell according to the first structural example. In the step shown in FIG. 11A, a tunnel SiO2 film 2, a floating gate 3, a capacitance insulating film 4, a control gate 5 and a protective SiO2 film are formed on a P-type semiconductor substrate 1 to form a stack type floating gate structure. To form. In the step shown in FIG. 11B,
After coating the resist 7 on the entire surface of the substrate, a region for forming a diode is opened, P + ion implantation is performed, and a low concentration n
-Forming layer 9. In the step shown in FIG. 11C, after the resist 10 is applied, the region where the diode is to be formed is left open and As + ions are implanted to form a high-concentration n + layer 21. In the step shown in FIG. 12A, a SiO2 film 22 is deposited as a protective film by the CVD method. FIG.
In the step shown in (b), the resist 23 is applied to open the region where the diode is to be formed, and the SiO2 film 22 is etched back by an anisotropic etching method to leave the sidewall 24 on the gate side wall in the region where the diode is to be formed. .
In the step shown in FIG. 12C, the tungsten silicide film 25 is patterned to form a Schottky diode. The tungsten silicide film 25 may be patterned as a wiring layer or as a contact buried layer. The Schottky diode formed through the above steps functions as the different-direction resistance portion.

Next, FIGS. 13A to 13D show manufacturing steps of the memory cell according to the second structural example. FIG.
In the step shown in FIG. 3 (a), a tunnel SiO2 film 2, a floating gate 3, a capacitance insulating film 4, a control gate 5 and a protective SiO2 film are formed on a P type semiconductor substrate 1 to form a stack type floating gate structure. Form. In the step shown in FIG. 13B, a resist 25 is applied, and an opening is formed by leaving As + in a region where a diode is to be formed.
Ion implantation is performed to form a high concentration n + layer 27. FIG.
In the step shown in (c), a side wall 28 is formed by depositing a SiO2 film and etching it back. FIG.
In the step shown in (d), As @ + ion implantation is performed to form a high concentration n @ + layer 30. In FIG. 13D, the n + layer 30 is offset from the floating gate, and the magnitude of the offset is controlled by the film thickness of the sidewall 28. The offset region 29 shown in FIG. 13D functions as a different-direction resistance portion. The example of the memory cell shown in FIG. 13D does not have a clear diode structure, but the same characteristics as those of the diode can be obtained. FIG. 14 is a simulation of the electrical characteristics of the offset transistor shown in FIG. The vertical axis is the operating current of the transistor,
The horizontal axis represents the gate (floating gate) voltage, the solid line represents the characteristics when the n + layer adjacent to the offset region 29 has a high potential (forward direction), and the dotted line represents the offset region 29.
The characteristics of the case where the n + layer 30 adjacent to and are made low potential (reverse direction) are shown. The gate length is 0.5 μm, the offset amount is 0.2 μm, and the drain-source voltage is 1 V. From the figure, it can be seen that the current values in the forward direction and the reverse direction are different by two digits or more.

FIGS. 15A to 15C show manufacturing steps of the memory cell according to the third structural example. In the step shown in FIG. 15A, a stack type floating gate structure is formed as in the manufacturing steps of the first and second structure examples. FIG.
In the step shown in (b), a resist 31 is applied, and an opening is formed leaving a region for forming a diode.
F2 + ion implantation was performed and p deeply entered under the gate
Form the layer 33. It is desirable that the BF2 + ion implantation is performed at a large inclination angle, and 45 degrees 60 KeV 6E12 atoms / cm2 seems to be suitable, but the condition is not limited to this.
In the step shown in FIG. 15C, As + ion implantation is performed to form a high concentration n + layer 30. As shown in FIG. 15C, first, the p-layer 33 is formed and the high-concentration n + layer 30 is made to recede, so that the region between the p-layer 33 and the high-concentration n + layer 30 functions as a diode.

It should be noted that the concentration of the p layer 33 is increased and the n + layer 3 is
0 may be offset with respect to the gate. FIG.
The example of the memory cell is characterized in that the side wall process is not required as compared with the example of the memory cell of FIG. FIG.
15 is a simulation of electrical characteristics of a memory cell having the structure of FIG. The vertical axis represents the operating current of the transistor, and the horizontal axis represents the gate (floating gate).
It is the voltage, and the solid line shows the forward characteristic and the dotted line shows the reverse characteristic. Gate length is 0.5 micron and p layer 33
Has a concentration of 1E18 atoms / cm3, is not in an offset state, and has a drain-source voltage of 1V. It can be seen that the current values in the forward direction and the reverse direction are different by one digit or more.

17 (a) to 17 (c) and FIG. 18 (a),
(B) shows a manufacturing process of the memory cell according to the fourth structural example. In the steps shown in FIGS. 17A to 17C,
Similar to the steps shown in FIGS. 12A to 12C, P + ions are implanted into a region where a stack type floating gate structure is formed and a PN diode is formed to form a low concentration n- layer 9, As + in the area where no diode is formed
Ions are implanted to form a high concentration n + layer 21.
Then, in a step shown in FIG. 18A, Si is used as a protective film.
The O2 film 22 is deposited by the CVD method. Next, the SiO2 film 22 is etched back in the region where the PN diode is formed, and the sidewall 24 is left on the side wall of the gate in the region where the PN diode is formed. After that, as shown in FIG. 18B, a resist 31 is applied, a region for forming a PN diode is opened, and BF2 + ion implantation is performed to form a p-layer 61.
To form. As a result, a PN diode functioning as a different-direction resistance portion is formed between the p layer 61 and the n− layer 9.

In the memory cell described above, the diode is formed in the region corresponding to the source region of the conventional stack type floating gate structure memory cell transistor, and the area of the memory cell is not increased.

Although the nonvolatile memory of this embodiment provided with a floating gate was used, MNOS
A non-volatile memory transistor of a type that changes the threshold voltage by injecting electrons into an insulating film on a channel region of a MOS transistor, which is typified by a (metal nitride oxide semiconductor) type memory cell, may be used.

(Fourth Embodiment) A method of driving a semiconductor memory device according to the fourth embodiment will be described below with reference to FIGS. The block circuit diagram of the semiconductor memory device according to this embodiment is the same as the block circuit diagram of the conventional nonvolatile semiconductor memory device shown in FIG.
FIG. 19 shows a memory cell array portion of a semiconductor memory device in this embodiment, which is an improvement of the structure of the memory cell array shown in the first embodiment for high integration. In the present embodiment, as shown in FIG. 19, for example, the drains of two memory cells (T21a) and (T21b) are connected to a common bit line B1 via a common wiring, and the memory cell (T21a) Of the memory cell (T
The sources of 21b) are respectively connected to the source line S3. That is, a pair of memory cells (T21a), (T21b
Source is connected to individual source lines S2 and S3, while the drains of the memory cells (T21a) and (T21b) are connected to a common bit line B1. Further, no memory cell is arranged in the region adjacent to the pair of memory cells (T21a) and (T21b). And bit line B2
On the other hand, each pair of memory cells (T12a), (T12b) and (T32a), (T32b) are arranged with an interval of 2 bits. The source of the memory cell (T12b) is connected to the common source line S2 with the memory cell (T21a). The other pair of memory cells (T32a), (T32b)
The same applies to the connection state of.

As a result of the above, two lines are placed between the source lines S1 and S2.
The two word lines W1a and W1b are arranged between the source lines S2 and S3, and the two word lines W2a and W2b are arranged, and the bit lines B1 to B3.
Are arranged so as to be orthogonal to the word line and the source line.
Then, in the area on the matrix formed by these wirings, 2
A set of bit memory cells (T) are arranged in a checkered pattern. The gate of each memory cell (T) is connected to a word line, and NOR type memory cells are arranged. The word lines W1a, W1b to W3a and W3b are row decoders, the source lines S1 to S3 are source decoders, and the bit lines B1 to B3 are column select transistors ST1 to ST3 via sense amplifiers SA1 to SA3.
It is connected to SA3 and to the column decoder.

In the structure shown in FIG. 20, the structure shown in FIG.
In the checkered memory cell array structure shown in FIG. 3, an example is shown in which the different-direction resistance portion as described in the third embodiment is provided on the source side of the memory transistor forming each memory cell. In this example, diodes D12a, D12b, D are provided between the source lines S1, S2, ... And the memory transistors.
21a, ... Are arranged, but a diode may be arranged between each drain and the memory transistor.

Next, the memory cell (T) in this embodiment
The structure of will be described. 21A is a sectional view showing the structure in the bit line direction, and FIG. 21B is a plan view corresponding thereto. Further, FIG. 22 shows the patterning of the floating gate in a plan view. FIG. 23
Shows a structural sectional view of the memory cell alone in the word line direction.
In each figure, 51 is element isolation, 52 is source wiring, 5
3 is a protective insulating film, 54 is an interlayer insulating film, 55 is a bit wiring, 56 is a source line contact, 57 is a bit line contact, 58 is an active region, and 59 is a floating gate after patterning. As shown in FIG. 18, a rectangular active region 58 whose long side is 5 times the design rule L and whose short side is the design rule L is formed so as to be folded, and the floating gate 59 is formed so that the long side of the active region 58 is long side. Patterning in a linear direction. As shown in FIG. 21B, the control gate 5, which is a word line, is patterned at equal intervals by lines and spaces according to the design rule to etch the capacitive insulating film 4, the floating gate 59, and the tunnel SiO2 film 2 in a self-aligned manner. . The source 30 is formed by ion implantation, and after formation, the SiO2 film 22 is formed.
Is deposited. The SiO2 film 22 is etched back to form a side wall 28, and an offset drain 27 is formed by ion implantation. The bit contact 57 is exposed by oversize, the wiring material and the SiO2 film 53 are deposited, and the source wiring 52 is patterned. The interlayer film 54 is deposited, the bit contact 57 is exposed by oversize, the interlayer film 54 is etched back, and the bit contact 5 is formed.
Open 7 A wiring material is deposited and the bit wiring 55 is patterned. As shown in the plan view of FIG. 21B, the channel width direction of the memory cell is rate-controlled by the bit line design rule and the alignment margin of the mask of the bit contact 57. As shown in FIG. 23, the floating gate 3 is asymmetric with respect to the active region in the structural cross section of the memory cell alone in the word line direction. This is due to the fact that the floating gate 59 is linearly patterned in the long side direction of the active region 58, and the smaller the design rule is, the more linear the patterning is, the more advantageous it is for miniaturization.

The layout shown in FIG. 21 and the like assumes that the mask alignment margin is half the design rule, and the cell area is 11 times the square of the design rule, but the mask alignment margin is the exposure technique. It does not have to be limited to half of the design rules.

The memory cell shown in FIG. 21 and the like uses the floating gate memory cell (second structure example in the third embodiment) having the structure shown in FIG. 13 (d) having the built-in offset region. However, the present invention is not limited to this, and the memory cells having the structures shown in the first, third, and fourth structural examples may be used.

Further, in the present embodiment, the active region 58 has a rectangular shape, but it may be partially deformed depending on the exposure technique or the like.

Further, in this embodiment, the floating gate 59, the control gate 5, and the source wiring 52 are included.
Is linear, but may be partially deformed according to the need of the exposure technique.

Although the source wiring 52 is made of a wiring material in this embodiment, it may be formed of a diffusion layer.

Next, the reading method of the present embodiment will be described with reference to FIG. In the present embodiment, the reading method uses the same voltage relationship as in the first embodiment. FIG.
Alternatively, as shown in FIG. 20, for example, two word lines W
Read the potential of 1b and W2a power supply voltage (for example, 5 V)
In addition, the potentials of the unselected word lines W1a and W2b to W3b are set to the ground potential (for example, 0 V), the potential of the source line S2 is set to the read intermediate potential (for example, 1 V), and the unselected source lines S1 and
All the memories connected to the word lines W1b and W2a by setting the potentials of S3 to S4 to the ground potential (for example, 0 V) and all the bit lines to the ground potential (for example, 0 V) via the sense amplifier. Read cells all at once.

As in the structure of FIG. 20, in the case of a memory cell array having a structure in which a diode is provided as in the third embodiment, the word line potential is kept at the ground potential as in the third embodiment. You may read it.

Further, if the threshold voltage is controlled so that no memory cell to be depleted is generated, one word line may be read out at once as in the first embodiment.

Although the nonvolatile memory of this embodiment provided with a floating gate was used, MNOS
A non-volatile memory transistor of a type that changes the threshold voltage by injecting electrons into an insulating film on a channel region of a MOS transistor, which is typified by a (metal nitride oxide semiconductor) type memory cell, may be used.

[0099]

As described above, according to the invention of claim 1 or 2, in the semiconductor memory device having the memory cell array structure in which the non-volatile memory cells are arranged in a matrix, the stored contents of the memory cells are read out. At this time, since the potential of the bit line is set lower than the potential of the selected source line, it is possible to prevent erroneous reading due to error in non-selected memory cells as much as possible.

According to the third aspect of the present invention, the potential of the non-selected source line is set to be equal to the potential of the bit line, so that erroneous reading in the memory cell connected to the selected bit line can be surely prevented. You can

According to the fourth aspect of the present invention, the power consumption can be reduced by suppressing the charging / discharging of the source line.

According to the fifth aspect of the invention, when the memory contents of the memory cells are read out, the memory cells on the selected source line are collectively read out. Therefore, the number of readings can be reduced and the charging / discharging of the source line can be avoided. Can be
Therefore, the power consumption can be significantly reduced.

According to the sixth aspect of the invention, the potential of the non-selected bit line is set to be floating when the stored contents of the memory cell are read out, so that power consumption due to charging / discharging on the bit line is suppressed. be able to.

According to the invention of claim 7, the source voltage of the read operation at the time of verify is made lower than the source voltage of the normal read operation, so that a large threshold design margin of the semiconductor memory device is secured. be able to.

According to the eighth aspect of the present invention, since the threshold voltage is greatly reduced due to the source voltage, the transconductance of the memory cell can be increased and the read operation can be speeded up.

According to the ninth or tenth aspect of the invention, since the memory transistor having the split gate structure and the floating gate provided on the source side is used for the non-volatile memory cell, the floating gate has a large capacitance coupling ratio on the source side. The capacitive coupling ratio on the side can be made almost zero, and thus the amount of decrease in the threshold voltage due to the source voltage can be increased.

According to the eleventh aspect of the present invention, the read voltage is set to the ground voltage and the stored contents of the memory cell are read. Therefore, it is possible to eliminate the fluctuation of the potential of the word line during the read. Therefore, power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram for explaining a configuration and a read operation of a semiconductor memory device according to a first embodiment.

FIG. 2 is a sectional view of a memory cell having an asymmetrical source / drain structure according to the first embodiment.

FIG. 3 is a cross-sectional view of a memory cell having a split gate structure according to the first embodiment.

FIG. 4 is a cross-sectional view of a memory cell having the offset structure of the first embodiment.

FIG. 5 is a schematic diagram of threshold voltage distribution of the memory cell of the first embodiment.

FIG. 6 is an electric circuit diagram showing a detailed structure of a memory cell array of the semiconductor memory device of the first embodiment.

FIG. 7 is a timing chart showing changes in signals at various parts in the reading method according to the first embodiment.

FIG. 8 is an electric circuit diagram showing a detailed structure of a memory cell array of the semiconductor memory device of the second embodiment.

FIG. 9 is a timing chart showing changes in signals of various parts in the reading method according to the first embodiment.

FIG. 10 is an electric circuit diagram for explaining a configuration and a reading method of a memory cell array of a third embodiment.

FIG. 11 is a cross-sectional view showing a structural change in the process up to forming the n + layer in the process of manufacturing the memory cell according to the first structural example of the third example.

FIG. 12 is a cross-sectional view showing a structural change in the steps of forming the Schottky diode after forming the SiO 2 film in the step of manufacturing the memory cell according to the first structural example of the third example.

FIG. 13 is a cross-sectional view showing a structural change in a manufacturing process of an offset structure memory cell according to a second structure example of the third embodiment.

FIG. 14 is a result of simulating electric characteristics of an offset structure memory cell according to a second structure example of the third embodiment.

FIG. 15 is a cross-sectional view showing a structural change in the manufacturing process of the memory cell according to the third structural example of the third example.

FIG. 16 is a diagram showing simulation results of voltage-current characteristics of a memory cell according to a third structural example of the third example.

FIG. 17 is a cross-sectional view showing a structural change in the process up to forming the n + layer in the process of manufacturing the memory cell according to the fourth structural example of the third example.

FIG. 18 is a cross-sectional view showing a structural change in the process of manufacturing the memory cell according to the fourth structural example of the third embodiment and forming the PN diode after forming the SiO 2 film.

FIG. 19 is an electric circuit diagram for explaining the configuration and the read operation of the memory cell array of the fourth embodiment.

FIG. 20 is an electric circuit diagram for explaining a configuration and a read operation of a memory cell array provided with a diode according to a fourth embodiment.

FIG. 21 is a cross-sectional view and a plan view showing the structure of the memory cell of the fourth embodiment.

FIG. 22 is a plan view showing a patterned state of a floating gate of a memory cell of a semiconductor memory device according to a fourth example.

FIG. 23 is a cross-sectional view showing the structure of a single memory cell in the semiconductor memory device of the fourth embodiment in the word line direction.

FIG. 24 is a block diagram showing an overall configuration of a conventional semiconductor memory device.

FIG. 25 is an electric circuit diagram for explaining a configuration and a read operation of a memory cell array of a conventional semiconductor memory device.

FIG. 26 is a threshold voltage distribution diagram of memory cells of a conventional semiconductor memory device.

FIG. 27 is a sectional view showing a state of capacitive coupling of memory cells of a conventional semiconductor memory device.

FIG. 28 is a characteristic diagram showing electrical characteristics of a conventional semiconductor memory device.

[Explanation of symbols]

 1 semiconductor p substrate 2 tunnel SiO2 film 3 floating gate 4 capacitance insulating film 5 control gate 11 memory transistor 12 word line 13 bit line 14 source line 17 diode 18 sense amplifier 24, 28 side wall 104 source decoder circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 29/788 29/792 H01L 27/10 434 29/78 371 (72) Inventor Toshiki Mori Osaka Prefecture 1006 Kadoma, Kadoma-shi, Matsushita Electric Industrial Co., Ltd. (72) Inventor Ichiro Nakao 1006 Kadoma, Kadoma-shi, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (11)

[Claims] 1. A memory cell array in which non-volatile memory cells each having a transistor including at least a gate, a source, and a drain and a capacitor section are arranged in a matrix, and gates of the transistors arranged in a row direction of the memory cell array. Connected to a plurality of word lines, a plurality of bit lines connected to the drains of the transistors arranged in the column direction of the memory cell array, and a source of the transistors arranged in the row direction of the memory cell array. Of a plurality of source lines, a decoder circuit for selecting the word line, a decoder circuit for selecting the bit line, and a decoder circuit for selecting the source line. In the driving method, at least one source line of the plurality of source lines is connected to the decoder circuit. Select the word line of the same address as the nonvolatile memory cell connected to the selected source line by the decoder circuit, set the potential of the selected word line to a predetermined potential, and set the potential of the bit line to A second potential higher than the first potential, the potential of the selected source line being set to the first potential;
A method of driving a semiconductor memory device, comprising: setting a potential and reading the stored contents of at least one memory cell connected to the selected source line and the selected word line. 2. The method of driving a semiconductor memory device according to claim 1, wherein the first potential is set to substantially a ground potential when reading the stored contents of the memory cell. 3. The method for driving a semiconductor memory device according to claim 1, wherein the potential of the non-selected source line is set equal to the first potential when reading the stored contents of the memory cell. Driving method of semiconductor memory device. 4. The method for driving a semiconductor memory device according to claim 1, wherein the potential of a non-selected source line is set to a floating state when the stored content of the memory cell is read. Driving method. 5. The method for driving a semiconductor memory device according to claim 1, 2, 3 or 4, wherein all the nonvolatile memories connected to the selected source line when reading the stored contents of the memory cells. A method for driving a semiconductor memory device, which comprises reading out cells all at once. 6. The method for driving a semiconductor memory device according to claim 1, 2, 3 or 4, wherein the potential of a non-selected bit line is set to a floating state when reading the stored contents of the memory cell. Driving method of semiconductor memory device. 7. The method of driving a semiconductor memory device according to claim 1, 2, 3, 4, or 5, wherein when a read is performed in a write verify operation or an erase verify operation, the potential of the selected source line is set to the read operation. 2. A method for driving a semiconductor memory device, wherein the potential is set lower than the potential of the selected source line in. 8. The method of driving a semiconductor memory device according to claim 1, 2, 3, 4, 5, 6 or 7, wherein the capacitive coupling ratio between the source and the capacitance section is the nonvolatile memory cell. A method of driving a semiconductor memory device, comprising using a nonvolatile memory cell formed so as to have a ratio larger than a capacitive coupling ratio between the drain and the capacitance section. 9. The method of driving a semiconductor memory device according to claim 1, 2, 3, 4, 5, 6 or 7, wherein a capacitance portion has a split gate structure as the memory transistor in the nonvolatile memory cell. A method for driving a semiconductor memory device, which uses a memory transistor. 10. The method of driving a semiconductor memory device according to claim 9, wherein the capacitance portion of the memory transistor having the split gate structure has a region overlapping with a source region of the memory transistor. Driving method of semiconductor memory device. 11. The method according to claim 1, 2, 3, 4, 5, 6 or 7.
In the method for driving a semiconductor memory device described above, the threshold voltage of a memory cell in a low threshold state is set to a negative value in advance, and when reading the stored contents of the memory cell, all word lines are grounded. A method for driving a semiconductor memory device, comprising: