JPH08102199A - Number of simultaneous test pieces increase circuit of memory integrated circuit device and its test method - Google Patents

Abstract

PURPOSE: To increase the number of memory integrated circuits capable of connecting to a set of I/O pins of a tester and to enhance the test efficiency by transmitting its output when the outputs of plural devices to be tested coincide with each other, and transmitting the output made to be in a high impedance state when they disagree to one pin of the tester. CONSTITUTION: The outputs of plural memory ICs 1a-1d are inputted to three terminals switches 4a-4d of a tester IO pin-corresponding unit circuit 20 to be inputted to an exclusive OR circuit 7 through a usually off terminal 4a-A, etc., and the output of the circuit 7 becomes L when one or more among the inputs 5a-5d are noncoincident. Then, a high impedance driver circuit 11 becomes enable, and an AND circuit 10 is opened through an inverter 9, and the output of the IC 1a is transmitted to one I/O pin of the tester in the state of high impedance, and the noncoincidence is detected. On the other hand, when they agree with each other, the outputs of the ICs 1a-1d are transmitted to the same I/O pin successively, and this is detected. By such a constitution, the number of pieces of ICs to be tested can be increased, and the test efficiency can be enhanced essentially.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit for a memory integrated circuit device, and more particularly to a function test in a memory test system (for a wafer test and a package test) used for conducting an electrical test of a memory integrated circuit device. And a test method for optimally controlling the number of simultaneous tests.

[0002]

2. Description of the Related Art The test time of a memory integrated circuit device, especially the time required for a functional test, has become longer with the recent increase in the capacity of the memory integrated circuit device. Therefore, on the memory test system side, by increasing the number of memory integrated circuit devices that can be tested at the same time (referred to as "same measurement"),
It has become necessary to avoid a drop in processing capacity.

As a means for increasing the number of measurements, a conventional memory test system has generally adopted the following method. In addition, the realization of the same number of measurements is the system, that is, the memory tester,
Although it depends on the total performance such as a wafer prober or an auto handler and peripheral jigs and tools such as a test board, only the memory tester and the test board related to the subject of the present invention will be described below. The test mode is a board that electrically connects the test head of the memory tester and the device under test, and is equipped with the device under test, a circuit for testing, and the like.

Basically, it is the data input / output pins (abbreviated as "memory I / O pins") of the memory integrated circuit device to be tested that determine the same counting capability of the memory tester.
And the number of data input / output pins (abbreviated as “tester I / O pins”) of the memory tester.
This will be described below based on a specific example.

When performing a functional test of the memory integrated circuit device, first, data in the memory integrated circuit device is written. This is possible because the tester I / O pins are in output mode and the memory I / O pins are in input mode. Next, the written data is read to determine whether the value is the expected value. Lead is I / O of tester
This is possible because the pins are in input mode and the memory I / O pins are in output mode.

By repeating this operation for all the cells in the memory integrated circuit device while changing the data to be written and the addressing order, the quality of the functional test is judged.

In this way, the I / O pin of the tester and the I / O pin of the memory are connected to test the function of the memory integrated circuit device.
Assuming that the number of pins is 128 and the number of I / O pins of the memory integrated circuit device for performing the function test is 4, the same measurement number of this memory tester is 128/4, which is 32. That is, a maximum of 32 memory integrated circuit devices can be tested simultaneously.

In recent years, memory integrated circuit devices tend to increase in capacity and the number of I / O pins in the memory increases.

The increase in the number of I / O pins of the memory integrated circuit device means that the number of I / O pins of the tester assigned to one memory integrated circuit device increases. For example, the I / O pins of the memory are increased. If the number of is increased from four to eight, the same number of measurements of the tester will be half, which is 16.

As described above, in the case of the conventional memory tester, in order to double the same measurement or to prevent the same measurement from being halved when the number of I / O pins of the memory integrated circuit device to be tested is doubled, Doubling the number of tester I / O pins is required.

[0011]

However, doubling the number of I / O pins of a tester actually means that another tester (a different model or a higher model with a large total number of I / O pins) is used. This means development and introduction.

The history of the development and introduction of the conventional memory tester is exactly the development of a new memory tester in order to cope with the large capacity and multi-bit of the memory integrated circuit device. For example, in the case of a memory integrated circuit device in which the number of measurements is doubled and the number of I / O pins is doubled, it is possible to avoid lowering the processing capacity by not reducing the number of measurements. , This caused a huge capital investment and development fund.

The present invention has been made in view of the above problems, and the present invention provides a circuit and a circuit for doubling the number of simultaneous measurements of a memory integrated circuit device without increasing the total number of I / O pins of a tester. It is an object of the present invention to provide a test method for optimally controlling measurement.

[0014]

The present invention effectively utilizes a memory tester having a limited number of I / O pins,
In order to increase the number of measurements of the memory integrated circuit device and improve the test processing capability, the following configuration is adopted.

In other words, in order to achieve the above object, the present invention is a circuit for simultaneously testing a plurality of devices under test with one tester, wherein the same output pin of each device under test is used. When all of the outputs of the devices match, the output of the output pin is transmitted as an output signal to one pin of the tester, and at least one of the outputs from the same output pins of the plurality of devices under test is transmitted. When the output signals are different from each other, the output signal is set to a high impedance state and the output signal is transmitted to one pin of the tester, thereby providing a simultaneous test number increasing circuit for a memory integrated circuit device.

In the present invention, the circuit is connected so that the data applied from one pin of the tester is simultaneously supplied to the same input pin of each of the plurality of devices under test.

Further, the present invention is preferably an exclusive OR circuit which inputs output signals from the same output pin of a plurality of devices under test, and an inverter circuit which inputs the output of the exclusive OR circuit. A logical product circuit that receives an output of the inverter circuit and an output signal from the output pin of any one device under test in the device under test group; and an output of the logical product circuit as an input. A high-impedance driver circuit for inputting the output of an exclusive OR circuit as a signal for output control, and a circuit for increasing the number of simultaneous tests of a memory integrated circuit device.

Further, according to the present invention, preferably, a switch for switching a connection state between each output pin of a plurality of devices under test and the exclusive OR circuit, and a connection state between an output of the high impedance driver circuit and a memory pin. There is provided a simultaneous test number increasing circuit for a memory integrated circuit device, comprising: a switch for switching the switch and a control unit for switching the switch group according to a pass / fail status of a test result of the memory integrated circuit device.

In the present invention, the simultaneous test number increasing circuit may be used as a unit circuit and a plurality of sets may be provided.

In another aspect, the present invention includes a table showing the relationship between the number of devices under test (referred to as "the same measurement number") to be simultaneously tested by one tester and the yield and the test efficiency. A method for testing a memory integrated circuit device by optimally controlling the same number of measurements, (a) testing a predetermined number of devices under test for the same number of measurements, and (b) performing these tests. From the results, calculate the yield, (c)
With respect to the calculated yield, the same measure that maximizes the test efficiency is derived from the table, and the same measure is changed thereafter, and the control is performed so as to optimize the test efficiency. A method of testing a memory integrated circuit device is provided.

[0021]

According to the present invention, the device under test and the tester I
By arranging the circuit with the above configuration between the / O pins,
It is possible to increase the number of input / output terminals of the memory integrated circuit device that can be connected to one set of I / O pins of the tester multiple times, and the number of input / output terminals of the memory integrated circuit device increases multiple times. Even if the test time is increased, the test efficiency is still improved.

Further, according to the present invention, when a defect occurs in any one of the devices during a plurality of simultaneous tests, one pin of the tester is associated with one terminal of the device under test to detect the defective device. It is possible to specify.

According to the test method of the present invention, in the test of the memory integrated circuit device, the tester optimally controls the same measurement by referring to the yield so as to maintain the test efficiency at the maximum value. Therefore, the optimization of the test time (test cycle) is achieved.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

[0025]

First Embodiment A first embodiment of the present invention will be described with reference to the drawings and tables. FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention.

The unit circuit 20 corresponding to the tester I / O pin will be described with reference to FIG.

The input / output terminals 2a to 2d of the same numbers of the respective memory integrated circuit devices 1a to 1d to be tested are connected to the common terminals of the three terminal switches 4a to 4d via the coaxial wirings 3a to 3d.

The normal-open terminal sides of the three-terminal switches 4a-4d are connected to the input side of the exclusive OR circuit 7. The output 8 of the exclusive OR circuit 7 is the inverter circuit 9
Is connected to the input terminal of

The output 15 of the inverter circuit 9 is connected to one input terminal of the logical product circuit 10, and the other input terminals of the logical product circuit 10 are connected to the exclusive OR circuit 7 by the three-terminal switches 4a to 4a. Line 5a on the side of the 4d normal open terminal
5d to 5d are branched from one of them and connected to the other input end of the AND circuit 10 as an AND circuit input line 13.

The output 16 of the AND circuit 10 is input to a high impedance driver circuit (referred to as "HiZ driver circuit") 11 whose output is controlled to have a high impedance.
The output 8 of the exclusive OR circuit 7 is input to the inverter circuit 9 and branched and input to the high impedance control terminal 18 of the HiZ driver circuit 11 as a line 14.

The four normally closed terminals of the three-terminal switches 4a to 4d are connected to each other and are connected to the normally closed terminal 12-B of the three-terminal switch 12 on the output side. Normally open terminal 1 of 3-terminal switch 12
The output line 17b of the HiZ driver circuit 11 is provided at 2-A.
Is connected. Common terminal 12-C of the three-terminal switch 12
Are connected to I / O pins of a memory tester (not shown).

FIG. 2 is a diagram showing wiring between a memory integrated circuit device which is a device under test and a memory tester in one embodiment of the present invention.

With reference to FIG. 2, the connection state between the unit circuit 20 corresponding to the tester I / O pin, each memory integrated circuit device and the I / O pin of the tester will be described.

3 in the unit circuit 20 corresponding to the tester I / O pin
The common terminal 12-C of the terminal switch 12 is connected to a set of I / O pins including a driver 25 and a comparator 26 in the test head 27.

Thus, a plurality of memory integrated circuit devices 1a
Input / output terminals of 1d are connected to a set of I / O pins of the memory tester. In FIG. 1 and FIG. 2, four memory integrated circuit devices 1a to 1d are connected as the device under test, but it goes without saying that the number is not limited to four.

When the memory integrated circuit device has a plurality of input / output terminals in the same device, the input / output terminals having the same numbers are connected to different tester I / O pin corresponding unit circuits as described above. It That is, referring to FIG. 2, for example, the input / output terminals 2a of the memory integrated circuit devices 1a to 1d are used.
-1 to 2d-1 are connected to the unit circuit 20 corresponding to the tester I / O pin, and the input / output terminals 2a-2 to 2d-2 are connected to the tester I / O.
It is connected to the O-pin corresponding unit circuit 22. Note that FIG.
Although the number of input / output terminals of the memory integrated circuit devices 1a to 1d is shown as two, that is, bit 1 and bit 2, of course, this may be any number, and actually 1, 4, 8, 9 and the like. ing.

3 in the unit circuit 20 corresponding to the tester I / O pin
All of the terminal switches 4a to 4d and the three-terminal switch 12 have a relay structure, and the switches 4a to 4d, the relay driving units 21a to 21d, and the three-terminal switches 12 and 23 are configured as a pair, respectively. Each of the relay drive units 21a to 21d and the three-terminal switches 12 and 23
Are connected to external control terminals of a memory tester (not shown) via external control lines 24a to 24e.

The operation of this embodiment will be described below with reference to FIG. 1 and Table 1. Table 1 is a table showing combinations of connection states of the three-terminal switches 4a to 4d and 12 in the tester I / O pin corresponding unit circuit 20 shown in FIG.

By the way, in the functional test of the memory integrated circuit device, there is only one input / output terminal of the memory integrated circuit device to be tested for one set of I / O pins of the memory tester, that is, the I / O of the tester. One-to-many connection is possible between the test items that the pins and the input / output terminals of the memory integrated circuit device must correspond to each other, and the I / O pins of the tester and the input / output terminals of the memory integrated circuit device. There are some test items.

This is determined by the relationship between the drive capability of the I / O pin of the tester or the accuracy of the comparator and the required accuracy of the test item.

First, in this embodiment, the I / O of the tester is used.
The state of connection to the test items when the pins and the input / output terminals of the memory integrated circuit device must be one-to-one will be described.

In this case, among the switch combinations shown in Table 1, there are four serial combinations from the bottom, which are called "serial mode".

For example, when comparing the output of one memory integrated circuit device with an expected value pattern, etc., only the memory integrated circuit device 1a has I / O pins (for example, the comparator 2) of the tester.
6), the common terminal 4a-C of the three-terminal switch 4a and the normally closed terminal 4a-B are connected (denoted as "B" in Table 1), and the remaining three-terminal switches 4b-
The common terminal in 4d is connected to the normally open terminal (denoted as "A" in Table 1). The common terminal 12-C in the output 3-terminal switch 12 is connected to the normally closed terminal 12-B. That is, the pin 2a of the memory integrated circuit device 1a has the three-terminal switch 4a and the input / output line 1
7a and 1-to-1 connection with the I / O pin of the tester through the 3-terminal switch 12.

By sequentially shifting the connection state, the input / output terminals of the memory integrated circuit devices 1b-1d are also connected to the I / O pins of the tester in a one-to-one relationship. Note that this one-to-one connection is abnormal when one of the plural memory integrated circuit devices connected in the one-to-many connection described later
It can also be used to detect the abnormal memory integrated circuit device.

Next, the case where the I / O pin of the tester and the input / output terminal of the memory integrated circuit device are one to many will be described.

First, there is a case where data is applied from one I / O pin (driver 25) of the memory tester to input data to the input / output terminals 2a to 2d of the memory integrated circuit devices 1a to 1d. This is because the same data is input to each of the memory integrated circuit devices 1a to 1d, and there is no problem in one-to-many connection.

The connection state of the three-terminal switches 4a to 4d and 12 in this case is a combination of "at the time of memory input" in the second row from the top of Table 1.

The other case is when four output data from the memory integrated circuit devices 1a to 1d can be determined at the same time. The connection state of the three-terminal switches 4a to 4d and 12 in this case is
It is a combination of stages of "simultaneous mode" in "at memory output" of Table 1. That is, the common terminals of the three-terminal switches 4a to 4d and 12 are all connected to the normally open terminal.

For example, the expected output from the input / output terminals 2a-2d of the memory integrated circuit devices 1a-1d is "H".
(High level), and each actual memory integrated circuit device 1
It is assumed that the outputs of a to 1d are all "H".

At this time, the output signals (= "H") from the input / output terminals 2a-2d of the memory integrated circuit devices 1a-1d are input to the exclusive OR circuit 7, and the output thereof is "L". , The output of the inverter circuit 9 is set to "H", and
Since the line 13 is also “H”, the output of the AND circuit 10 becomes “H”, and the comparator 26 of the I / O pin of the tester is passed from the HiZ driver 11 through the three-terminal switch 12.
(See FIG. 2).

That is, the information that all the memory integrated circuit devices 1a to 1d as the device under test have the same output and the output value is "H" is input to the I / O pin (comparator 26) of the tester. To be done. Then, in the memory tester, based on this data, the memory integrated circuit device 1
It is possible to recognize and determine that the outputs from all of a to 1d match the expected output value (expected value pattern), that is, normal.

It is assumed that the output becomes "L" (low level) in at least one of the four memory integrated circuit devices. At this time, the output of the exclusive OR circuit 7 becomes "H", the inverter circuit 9 becomes "L", and the output of the AND circuit 10 becomes "L", but HiZ is passed through the high impedance control line 14. It is input to the high impedance control terminal 18 of the driver circuit 11, and the output line 17b of the HiZ driver circuit 11 is in a high impedance (HiZ) state, that is, a high resistance state.

By detecting this state by the I / O pin (comparator 26) of the tester, it can be recognized that at least one or more abnormalities in the four memory integrated circuit devices are included.

The expected output is "H", whereas the outputs of the four memory integrated circuit devices are "L".
When it becomes, the output of the exclusive OR circuit 10 is set to “H”, and thus the I / O pin (comparator 26) of the tester
"L" is input to the memory tester, and all four are abnormal (defective: FAI) compared with the expected value pattern (= "H") in the memory tester.
L) can be recognized.

Even when the expected output (expected value pattern) is "L", similarly, in the memory tester, all the memory integrated circuit devices are normal or contain one or more abnormalities. It is possible to distinguish whether or not.

If there is one or more abnormalities, the mode shifts to the serial mode (the I / O pins of the memory and the I / O pins of the tester have a one-to-one correspondence) described above, and the memory integrated circuit devices 1a to 1a. By testing 1d one by one,
A memory integrated circuit device having an abnormality (failed) is specified.

By using the various operations described above according to various conditions such as the purpose of each test item, the accuracy, and the necessity / unnecessity of specifying a defective memory integrated circuit device, one I / O pin of the memory tester can be obtained. It is possible to improve the measurement efficiency by connecting and measuring a plurality of memory integrated circuit devices.

The connection state of each 3-terminal switch is set by designating it in the device program. The external control terminal of the memory tester (not shown) is turned on for each bit in consideration of whether each test item is in the simultaneous mode, the serial mode, or whether the defective memory integrated circuit device is specified after the simultaneous mode. Alternatively, it is turned off to control the relay drive units 21a to 21d and the three-terminal switches 12 and 23 via the external control lines 24a to 24e.

[0059]

Second Embodiment A second embodiment of the present invention will be described below with reference to Table 2 and FIG.

Prior to the description of this embodiment, the actual effect (processing capacity = shortening of measurement time per number of terminals) of the first embodiment will be simulated.

As a precondition, the number of memory integrated circuit devices to be tested is 1,000, and 80 out of the total test time.
% Is a test item that allows one-to-many connection between the I / O pin of the tester and the input / output terminal of the memory integrated circuit device, and the remaining 20%
Is a test item that requires one-to-one connection between the pins of the memory tester I / O and the input / output terminals of the memory integrated circuit device.

When an abnormality is detected in the one-to-many connection, it is necessary to identify the defective memory integrated circuit device.

The number of I / O pins of the tester is one / head, and the number of input / output terminals of the memory integrated circuit device to be measured is also one.

Further, for simplification, the memory tester has one head configuration and the handling time of the memory integrated circuit device is regarded as zero.

The yield of the memory integrated circuit device to be tested also affects. The memory integrated circuit device test yield is calculated here for each of the cases of 85%, 90%, 95%, 97% and 100%.

The number of input / output terminals of the memory integrated circuit device is 1,
Since the number of I / O pins of the tester is also 1, the conventional method can connect only one memory integrated circuit device at a time.

When the test time is 1, it is necessary to test 1,000 memory integrated circuit devices for 1,000 cycles, so 1,000 test times are required. In this case, the yield is considered to have little effect on the test time.

Under the above conditions, the test time when the circuit configuration of the first embodiment is applied is as follows.

First, the unit circuit 2 corresponding to the I / O pin of the tester
Consider a case where two memory integrated circuit devices are connected to 0.

In this case, since two memory chips can be tested at the same time, a test of 500 cycles is required to test 1,000 memory integrated circuit devices.

First, when the yield is 85% (150 defectives out of 1000), the number of cycles in which both are normal occurs at 425 cycles (= 500 × 0.
85).

On the other hand, it is the case of 350 cycles that the number of cycles in which both of them are normal occurs the least. That is, in the case of a yield of 85%, the least frequent occurrence due to uneven distribution or the like is when 150 defective memory integrated circuit devices are accumulated (continuously) on one device under test side. Therefore, the minimum frequency cycle in which both two are normal is 500−150 = 350 cycles.

First, let us calculate the case of 425 cycles. In a cycle in which both of them are normal, 80% of the tests are based on the 1-to-2 connection, so the test time ratio of the two memory integrated circuit devices is 0.8 + 0.2 × 2 = 1.2.

Since the remaining 75 cycles include one out of two abnormalities, it is necessary to repeat the test two more times in order to specify the defective memory integrated circuit device after testing once. is there.

Therefore, the test time ratio of the remaining 75 cycles is 3, and when these are combined, 1.2 × 425 + 3
× 75 = 735 cycles.

The efficiency calculated from the test time is 1000.
/735=1.36.

When the cycle in which both of them are normal is 350, 1.2 × 350 + 3 × 150 = 870
Therefore, the efficiency is 1000/870 = 1.15.

As described above, even if the yields are the same, the number of repeated tests is different depending on the distribution state of defective memory integrated circuit devices, resulting in a difference in efficiency.

Similarly, the yields 90%, 95%, 97
%, 100%, and when the number of input / output terminals of the memory integrated circuit device connected to the unit circuit 20 corresponding to the I / O pin of the memory tester is 4, 8, 16, 32, the efficiency (that is, processing capacity) ) Are summarized in Table 2
FIG. 3 is a graph showing this result.

As can be seen from FIG. 3 and Table 2, the efficiency greatly varies depending on the yield of the test target lot and the same measurement number of the memory tester. Then, as shown in FIG. 3, the higher the yield of the memory integrated circuit device, the more the test efficiency is improved with the increase in the number of measurements.

In the second embodiment of the present invention, in order to increase this efficiency as much as possible, the yield of the target lot is calculated and the optimum same measure is automatically determined.

For example, if the yield of the target lot is close to 100%, the same measure is maximized within the range that the memory test system can handle, and conversely, if the yield is 85% or less, the same measure is set to 4 or more. Since the efficiency can be 1 or less, the same survey control is performed by continuing the test with the same two surveys.

The optimum control of the same measurement is performed by the first
It is configured by using the circuit configuration described in the above embodiment and the standard function of a memory test system including a general memory tester and handling equipment.

The operation will be described below.

When the number of input / output terminals of the memory integrated circuit device that can be connected to the unit circuit 20 corresponding to the tester I / O pin is 4, first, for example, two memory testers and handling equipment can be measured in advance so that they can be measured simultaneously. Set to. At this time, leave the remaining two empty.

Then, the yield is judged by the memory tester at the stage when the test of several tens of cycles from the first several cycles of the lot is completed. In the tester, the device test program can count the devices under test, manage the yield, and the like, which can be handled in a known manner.

In accordance with this yield, it is judged whether to continue the same measurement for two pieces or change it to the same measurement for four pieces according to a preset standard (for example, a table storing Table 2 and the like). . This control can be realized by a device test program.

When changing to the same number of four, G
Using the communication means such as P-IB, the memory tester issues an instruction to change the same measurement number to the handling equipment. Control of the GP-IB or the like can also be normally performed in the device test program.

As a result, in the handling equipment, from the next time, the memory integrated circuit devices will be supplied to the two previously vacant units, and the test will be executed with the same four.

Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above embodiments, but includes various embodiments according to the principles of the present invention. For example, the present invention relates to a logic L such as a random logic having an input / output terminal.
It also applies to multiple simultaneous testing of SI.

[0091]

[Table 1]

[0092]

[Table 2]

[0093]

As described above, according to the simultaneous test number increasing circuit (Claim 1) in the function test of the memory integrated circuit device of the present invention, the memory integrated circuit which can be connected to one set of I / O pins of the tester. It is possible to increase the number of input / output terminals of the circuit device multiple times, and improve the test efficiency even if the test time is increased due to the increase of the number of input / output terminals of the memory integrated circuit device. It has an effect that it can be made.

The quantitative effects of the present invention are as shown in Table 2. The higher the test yield of the memory integrated circuit device is, the higher the test efficiency of the present invention is and the more reliable it is. I know there is.

This improvement in test efficiency leads to a reduction in the number of capital investment of the memory test system, and a great reduction in the equipment cost can be achieved. The improvement of the test efficiency according to the present invention reduces the test cost and realizes the cost reduction of the memory integrated circuit device.

Furthermore, according to a preferred aspect of the present invention (claims 3, 4, and 5), the above effects are more suitably realized by the simple circuit configuration. In particular, according to the preferred embodiment of the present invention, the practical value thereof is extremely high as it improves the test efficiency by avoiding the capital investment and the development investment of the new test system.

According to the test method of the present invention, in the test of the memory integrated circuit device, the tester controls the same measurement with reference to the yield so as to maintain the test efficiency at the maximum value. Time (test cycle) is what achieves optimization. The optimum control of the same measurement is easily realized by the function including the software included in the existing tester and the simultaneous test number increasing circuit of the present invention, which reduces the testing cost and manufactures the memory integrated circuit device. The cost is greatly reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing wiring between a memory and a tester according to an embodiment of the present invention.

FIG. 3 is a diagram showing a processing capacity by the same survey.

[Explanation of symbols]

1a-1d Memory integrated circuit device 2a-2d Input / output terminal (nth) 2a-1-2d-1 Input / output terminal of memory integrated circuit device (bit 1) 2a-2-2d-2 Input / output of memory integrated circuit device Terminal (bit 2) 3a to 3d Coaxial wiring 3a-1 to 3d-1 Coaxial wiring (for bit 1) 3a-2 to 3d-2 Coaxial wiring (for bit 2) 4a to 4d 3 terminal switch 4a-A Normal open terminal 4a-B Normally closed terminal 4a-C Common terminal 5a-5d Input line of exclusive OR circuit 6a-6d Input / output line 7 Exclusive OR circuit 8 Output line of exclusive OR circuit 9 Inverter circuit 10 AND circuit 11 High-impedance driver circuit (HiZ driver circuit) 12 3-terminal switch 12-A normally open terminal 12-B normally closed terminal 2-C common terminal 13 AND circuit input line 14 high impedance control signal 15 output circuit of inverter circuit 16 output line of AND circuit 17a input / output line 17b output line of high impedance driver circuit 18 high impedance control terminal 19 tester I / O pin connection line 20 Tester I / O pin corresponding unit circuit 21a to 23d Relay drive unit 22 Tester I / O pin corresponding unit circuit 23 Relay drive unit 24a to 24d External control line 25 Driver 26 Comparator 27 Test head

Claims (6)

[Claims] 1. A circuit for simultaneously testing a plurality of devices under test with one tester, wherein when outputs from the same output pin of each of the plurality of devices under test all match. The output of the output pin is transmitted as an output signal to one pin of the tester, and when at least one of the outputs from the same output pin of each of the plurality of devices under test is different, the output signal is set to a high impedance state. A circuit for increasing the number of simultaneous tests of a memory integrated circuit device, characterized in that this is transmitted to one pin of the tester. 2. The memory according to claim 1, wherein the memory is connected so that data applied from one pin of the tester is simultaneously supplied to the same input pin of each of the plurality of devices under test. Simultaneous test number increase circuit of integrated circuit device. 3. An exclusive OR circuit that receives output signals from the same output pin of a plurality of devices under test, an inverter circuit that receives an output of the exclusive OR circuit, and an output of the inverter circuit. And an output signal from the output pin of any one device under test in the device under test, and an output of the exclusive OR circuit with the output of the AND circuit as an input A circuit for increasing the number of simultaneous tests of a memory integrated circuit device, which comprises a high impedance driver circuit for inputting as a signal for output control. 4. A switch for switching a connection state between each output pin of a plurality of devices under test and the exclusive OR circuit, a switch for switching a connection state between an output of the high impedance driver circuit and a memory pin, and a memory integrated circuit. The simultaneous test number increasing circuit for a memory integrated circuit device according to claim 3, further comprising: a control unit that switches the switch group according to a pass / fail status of a test result of the circuit device. 5. A simultaneous test number increasing circuit for a memory integrated circuit device, comprising a plurality of sets of the simultaneous test number increasing circuit according to claim 3 or 4 as a unit circuit. 6. A tester includes a table showing the relationship between the number of devices under test (referred to as "equal measurement") to be simultaneously tested by one tester and the yield and test efficiency, and the same measurement is controlled optimally. A method for testing a memory integrated circuit device, comprising: (a) testing a predetermined number of devices under test for a predetermined number of measurements, (b) calculating a yield from these test results, and c) For the calculated yield, the same measurement that maximizes the test efficiency is derived from the table, and the subsequent same measurement is varied to perform control so as to optimize the test efficiency. Method for testing memory integrated circuit device.