JPH0799631B2 - Reference voltage generation circuit - Google Patents

Description

The present invention relates to a reference voltage generating circuit used in a memory device such as a ROM (read only memory) and a RAM (read / write memory).

[Conventional technology]

In the conventional circuit of this type, as shown in FIG. 3, the reference voltage generating circuit 16 has resistors 21 and 22 connected in series between the power supply terminal 20 and the ground, and a plurality of voltage dividing circuits are provided. A reference voltage is generated by continuously flowing a current to the ground through the resistors 21 and 22. In the read circuit 17, the reference voltage is compared with the read signal from the selected cell in the memory cell array 18, and "1" (high level), "0"
(Low level) is determined and output data 19 is generated.

[Problems to be solved by the invention]

In the conventional circuit described above, in the circuit 16, even when the reference voltage is not used for reading, the power supply 20 is connected to the resistors 21,2 in the circuit 16.
Current flows through 2 to the ground, which results in high power consumption and a temperature rise. So-called CM
Although the power consumption of the circuit has been reduced due to the OS, in the conventional configuration, the power consumption of the reference voltage generation circuit 16 accounts for an increase in the power consumption of the entire circuit.

It is an object of the present invention to provide a reference voltage generation circuit that consumes less power and is free from the risk of temperature rise.

[Means for solving problems]

The present invention has an opening / closing element in which a plurality of resistive elements are connected in series and is inserted in series in a circuit for dividing a power supply voltage, and a timing generation circuit for periodically generating a specific timing signal for controlling the opening / closing element. ing.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an essential part of a reference voltage generating circuit incorporated in a microcomputer according to an embodiment of the present invention. FIG. 2 shows the waveform of the timing signal 10 and the waveform of the reference voltage 5 relating to FIG.

The memory cell array 8 contains the instruction data, and the microcomputer repeats the operation of reading the instruction from the memory cell array 8 every one instruction cycle 13 and executing the instruction. In the microcomputer, in the instruction read period 12 of the instruction cycle 13, output data 1
Is used, and the output data 1 is not used in the instruction execution period 11. In the instruction read period 12, the read voltage 7 is read from the memory cell array 8 by the read voltage and the output data 1 is output.
It must be at level a in the figure.

In FIG. 1, the timing generation circuit 9 gives the waveform signal shown in FIG. 2 to the timing signal 10, so that the timing signal 10 becomes “1” (high level) in the instruction read period 12 and the switching element 3 becomes Turn on. Switching element 3 is ON
Then, a current flows from the power supply to GND through the resistors 4 and 6, the reference voltage 5 becomes a level, the read circuit 7 becomes readable, and the data of the memory cell 8 is read by the read circuit 7 and output data 1 is obtained. Is output. Further, since the output data 1 is not used during the instruction execution period 11, the reference voltage 5 does not need to be at the a level. Therefore, in the instruction execution period 11, the timing signal 10
"0" (low level) is output, and the switching element 3 is turned off. When the switching element 3 is turned off, the resistance 4 and the resistance 6
The current flowing from the power supply to GND is cut off. By repeating this operation for each instruction cycle, the current consumption of the microcomputer can be reduced and the power consumption can be reduced.

〔The invention's effect〕

As described above, according to the present invention, the switching element is inserted in the reference voltage generation circuit, the switching element is closed when the timing generation circuit uses the output signal of the memory, and the switching element is opened when the output signal of the memory is not used. By periodically applying such a signal to the switching element, it is possible to reduce the current flowing through the reference voltage generating circuit and reduce the power consumption of the circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration example according to an embodiment of the present invention, and FIG. 2 is a timing signal waveform diagram and a reference voltage waveform diagram of the circuit of FIG. FIG. 3 is a block diagram showing a conventional circuit. 1 ... Output data, 2 ... Reference voltage generating circuit, 3 ... Switching element, 4 ... Resistor, 5 ... Reference voltage, 6 ... Resistor, 7
...... Reading circuit, 8 ...... Memory cell, 9 ...... Timing generation circuit, 10 ...... Timing signal, 11 ...... Command execution period, 12 ...... Command reading period, 13 ...... 1 command cycle, 14 ...... Timing signal 10 waveform, 15 …… reference voltage 5 waveform, 16 …… reference voltage generating circuit, 17 …… reading circuit, 18 …… memory cell, 19 …… output data.

 ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-58-45680 (JP, A) JP-A-57-113263 (JP, A) JP-A-52-156520 (JP, A)

Claims (1)

[Claims] 1. A reference voltage generating circuit built in a computer having a memory cell array for storing instruction data, wherein the instruction data is obtained by comparing a read signal from a selected cell of the memory cell array with a reference voltage. In the reference voltage generating circuit for generating the reference voltage for generating, a resistive element series circuit having a plurality of resistive elements connected in series to divide a power supply voltage to generate the reference voltage, and the resistance And a timing signal for electrically connecting the switching element during a command read period for reading command data from the memory cell array and for shutting off the switching device during an execution period of the read command. And a timing generation circuit for supplying the switching element to the switching element. Reference voltage generating circuit according to symptoms.