JPH0799244A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0799244A
JPH0799244A JP24089493A JP24089493A JPH0799244A JP H0799244 A JPH0799244 A JP H0799244A JP 24089493 A JP24089493 A JP 24089493A JP 24089493 A JP24089493 A JP 24089493A JP H0799244 A JPH0799244 A JP H0799244A
Authority
JP
Japan
Prior art keywords
film
voltage
wiring
semiconductor device
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24089493A
Other languages
Japanese (ja)
Inventor
Yoshiaki Kato
良章 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP24089493A priority Critical patent/JPH0799244A/en
Publication of JPH0799244A publication Critical patent/JPH0799244A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To provide a semiconductor device having the sufficient electrostatic withstand voltage by increasing the withstand voltage at the intersecting part of wirings where two kinds of voltages are applied. CONSTITUTION:A polysilicon film 13 for cutting and reconnecting an Al film wiring 11 for applying the first voltage and an Al film wiring 12 for applying the second voltage are intersected through an insulating film 15. A polysilicon film 1 is provided at the intermediate part of the wirings through the insulating film 15. Thus, the concentration of the voltage at a pattern edge part is dispersed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は多層の導電膜をもつ半
導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer conductive film.

【0002】[0002]

【従来の技術】導電膜として2層のポリシリコン膜と1
層のAL膜(アルミニウム膜)を備えた半導体装置で
は、ポリシリコン膜は主にゲート電極として形成され、
AL膜はポリシリコンゲート電極やシリコン基板に所定
の電圧を加えるために配線として結線されている。
2. Description of the Related Art As a conductive film, a two-layer polysilicon film and one
In a semiconductor device having a two-layer AL film (aluminum film), the polysilicon film is mainly formed as a gate electrode,
The AL film is connected as a wiring to apply a predetermined voltage to the polysilicon gate electrode and the silicon substrate.

【0003】上記のような半導体装置では、ポリシリコ
ンゲート電極やシリコン基板に与えるべき多種類の電圧
すべてを、抵抗の低いAL膜で供給している。従来の技
術では、同電圧とならない2種類の配線を交差させる必
要が生じた場合以下のようにしていた。すなわち、交差
部において第1の電圧が加わるAL膜配線を切断後、ポ
リシリコン膜を用いて再結線し、第2の電圧が加わるA
L膜配線を第1の電圧が加わる前述のポリシリコン膜の
上部に絶縁膜を介して配置することで目的を達成してい
た。
In the semiconductor device as described above, all kinds of voltages to be applied to the polysilicon gate electrode and the silicon substrate are supplied by the AL film having a low resistance. In the conventional technique, the following is performed when it is necessary to intersect two types of wirings that do not have the same voltage. That is, after the AL film wiring to which the first voltage is applied is cut at the intersection, reconnection is performed using a polysilicon film, and the second voltage A is applied.
The purpose has been achieved by arranging the L film wiring on the above-mentioned polysilicon film to which the first voltage is applied via the insulating film.

【0004】以下、図面を用いて説明する。図3は従来
の半導体装置の配線模式図である。図3において、8は
第1の電圧が加わる配線で、9は第2の電圧が加わる配
線である。図4(a)は図3での配線の交差部を示した
平面図、図4(b)は(a)におけるZ−Z′断面図で
ある。図4において、10はシリコン基板、11は第1
の電圧が加わるAL膜配線、12は第2の電圧が加わる
AL膜配線、13は第1の電圧が加わる配線を再結線す
るためのポリシリコン膜、14はコンタクトホール、1
5は絶縁膜である。
A description will be given below with reference to the drawings. FIG. 3 is a wiring schematic diagram of a conventional semiconductor device. In FIG. 3, 8 is a wiring to which a first voltage is applied, and 9 is a wiring to which a second voltage is applied. 4A is a plan view showing an intersection of the wirings in FIG. 3, and FIG. 4B is a sectional view taken along line ZZ ′ in FIG. In FIG. 4, 10 is a silicon substrate and 11 is a first
AL film wiring to which the voltage is applied, 12 is an AL film wiring to which the second voltage is applied, 13 is a polysilicon film for reconnecting the wiring to which the first voltage is applied, 14 is a contact hole, 1
Reference numeral 5 is an insulating film.

【0005】図4に示すように、従来の半導体装置の配
線の交差部においては、AL膜配線12はAL膜配線1
1を再結線しているポリシリコン膜13の上部を絶縁膜
15を介して配線されている。従来の技術では、以上の
ように2種類の配線を交差させ、多種類の電圧の供給を
行っていた。
As shown in FIG. 4, at the intersection of the wirings of the conventional semiconductor device, the AL film wiring 12 is the AL film wiring 1
The upper part of the polysilicon film 13 that reconnects 1 is wired via the insulating film 15. In the conventional technique, two kinds of wirings are crossed as described above to supply various kinds of voltages.

【0006】[0006]

【発明が解決しようとする課題】しかしながら上記従来
の構成では、ポリシリコン膜13とAL膜配線12の間
の静電耐圧が不十分であった。静電気などの影響で瞬間
的に高い電圧が半導体装置に加わることがある。その対
策として、保護回路を設けて高電圧を逃がす構造をとる
ことが多い。ところがレイアウトの関係で充分な保護回
路を設けることができない場合がある。
However, in the above-mentioned conventional structure, the electrostatic breakdown voltage between the polysilicon film 13 and the AL film wiring 12 is insufficient. A high voltage may be momentarily applied to the semiconductor device due to the influence of static electricity or the like. As a countermeasure, it is often the case that a protection circuit is provided to release a high voltage. However, there are cases where a sufficient protection circuit cannot be provided due to the layout.

【0007】レイアウト的に保護回路の領域が充分でな
い場合にボンディングパッドの下に拡散層を設けること
があるが、この方法ではボンディングパッド下の酸化膜
が薄くなり、ワイヤーボンディング時の強度に問題が生
じるので危険である。充分な保護回路が設けられている
ときには静電耐圧の問題は無いが、そうでないときは従
来の技術では配線を交差させているところの静電耐圧が
不十分であった。
A diffusion layer may be provided under the bonding pad when the area of the protection circuit is insufficient in layout. However, this method causes a thin oxide film under the bonding pad, which causes a problem in strength during wire bonding. It is dangerous because it occurs. When a sufficient protection circuit is provided, there is no problem of electrostatic withstand voltage, but when it is not, the conventional technique has an insufficient electrostatic withstand voltage where the wiring intersects.

【0008】図5は図4(b)の部分拡大図である。図
5の○で囲んだ部分Aで局所的な高電圧が加わりやす
く、それにより絶縁破壊を起こしてAL膜配線12とポ
リシリコン膜13がショートするという問題点を有して
いた。この発明はかかる点に鑑み、配線の交差部分にお
いて充分な静電耐圧を有する半導体装置を提供すること
を目的とする。
FIG. 5 is a partially enlarged view of FIG. 4 (b). A local high voltage is apt to be applied to the portion A surrounded by a circle in FIG. 5, which causes dielectric breakdown and short-circuits the AL film wiring 12 and the polysilicon film 13. In view of the above point, the present invention has an object to provide a semiconductor device having a sufficient electrostatic breakdown voltage at the intersection of wirings.

【0009】[0009]

【課題を解決するための手段】この発明の半導体装置
は、第1の電圧が加わる第1の導電膜と第2の電圧が加
わる第2の導電膜との間の絶縁膜中に第3の導電膜を設
けたことを特徴とする。
According to another aspect of the present invention, there is provided a semiconductor device in which an insulating film between a first conductive film to which a first voltage is applied and a second conductive film to which a second voltage is applied is provided in a third insulating film. A feature is that a conductive film is provided.

【0010】[0010]

【作用】この発明の構成によれば、第1の電圧が加わる
第1の導電膜と第2の電圧が加わる第2の導電膜との間
に発生しようとする局所的な高電圧を、中間に位置した
第3の導電膜により空間的に分散させ、静電耐圧を上げ
ることができる。
According to the structure of the present invention, the local high voltage which is about to be generated between the first conductive film to which the first voltage is applied and the second conductive film to which the second voltage is applied is intermediate. It is possible to increase the electrostatic breakdown voltage by spatially dispersing it by the third conductive film located at.

【0011】[0011]

【実施例】図1(a)はこの発明の第1の実施例の半導
体装置の配線交差部の平面図、(b)はそのX−X′断
面図である。図1において、1はポリシリコン膜(第3
の導電膜)、10はシリコン基板、11は第1の電圧が
加わるAL膜配線、12は第2の電圧が加わるAL膜配
線(第2の導電膜)、13は第1の電圧が加わるAL膜
配線11を再結線するためのポリシリコン膜(第1の導
電膜)、14は第1の電圧が加わるAL膜配線11とポ
リシリコン膜13を結合するコンタクトホール、15は
絶縁膜である。
1A is a plan view of a wiring intersection portion of a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a sectional view taken along line XX '. In FIG. 1, 1 is a polysilicon film (third
Conductive film), 10 is a silicon substrate, 11 is an AL film wiring to which a first voltage is applied, 12 is an AL film wiring to which a second voltage is applied (second conductive film), and 13 is an AL film to which a first voltage is applied. A polysilicon film (first conductive film) for reconnecting the film wiring 11, 14 is a contact hole for connecting the AL film wiring 11 to which the first voltage is applied and the polysilicon film 13, and 15 is an insulating film.

【0012】この半導体装置は、第1の電圧が加わるポ
リシリコン膜13と第2の電圧が加わるAL膜配線12
との間に、絶縁膜15を介してポリシリコン膜1を設け
ている。ポリシリコン膜1は第1の電圧が加わるポリシ
リコン膜13を覆うように設けている。以上のように構
成されるこの半導体装置において、ポリシリコン膜1
が、第1の電圧の加わるポリシリコン膜13と第2の電
圧が加わるAL膜配線12との間で、例えばエッジ部な
ど局所的に電圧がかかり易い部分への電圧の集中を防止
する働きをするため、静電耐圧を上げることができる。
This semiconductor device has a polysilicon film 13 to which a first voltage is applied and an AL film wiring 12 to which a second voltage is applied.
And the polysilicon film 1 is provided with the insulating film 15 interposed therebetween. The polysilicon film 1 is provided so as to cover the polysilicon film 13 to which the first voltage is applied. In this semiconductor device configured as described above, the polysilicon film 1
However, between the polysilicon film 13 to which the first voltage is applied and the AL film wiring 12 to which the second voltage is applied, the function of preventing the concentration of the voltage on a portion where a voltage is easily applied locally, such as an edge portion, is prevented. Therefore, the electrostatic breakdown voltage can be increased.

【0013】図2(a)はこの発明の第2の実施例の半
導体装置の配線交差部の平面図、(b)はそのY−Y′
断面図である。図2において、2はポリシリコン膜(第
3の導電膜)であり、その他図1に対応する部分には同
一符号を付している。この半導体装置では、図1のポリ
シリコン膜1に代えて、ポリシリコン膜2を、第1の電
圧が加わるポリシリコン膜13と第2の電圧が加わるA
L膜配線12との間に位置し、ポリシリコン膜13のエ
ッジ部を特に覆うように設けている。
FIG. 2A is a plan view of a wiring intersection portion of a semiconductor device according to a second embodiment of the present invention, and FIG. 2B is its YY 'section.
FIG. In FIG. 2, 2 is a polysilicon film (third conductive film), and other parts corresponding to those in FIG. 1 are denoted by the same reference numerals. In this semiconductor device, instead of the polysilicon film 1 of FIG. 1, the polysilicon film 2 is replaced by a polysilicon film 13 to which a first voltage is applied and an A to which a second voltage is applied.
It is provided between the L film wiring 12 and the polysilicon film 13 so as to cover the edge portion of the polysilicon film 13.

【0014】以上のように構成されるこの実施例の半導
体装置においても、ポリシリコン膜2がポリシリコン膜
13のエッジ部を覆っているため、そのエッジ部に集中
する電圧を分散する働きをするため、静電耐圧を上げる
ことができる。なお、この第1,第2の実施例における
ポリシリコン膜1,2は、電圧的にフローティングであ
るが、これが接地されていても良いことは言うまでもな
い。
Also in the semiconductor device of this embodiment configured as described above, since the polysilicon film 2 covers the edge portion of the polysilicon film 13, it functions to disperse the voltage concentrated on the edge portion. Therefore, the electrostatic breakdown voltage can be increased. Although the polysilicon films 1 and 2 in the first and second embodiments are floating in terms of voltage, it goes without saying that they may be grounded.

【0015】また、第2の実施例におけるポリシリコン
膜2は2片に分かれているが、これが一部でつながって
いても良いことは言うまでもない。また、第1,第2の
実施例ともに、導電膜はAL膜、ポリシリコン膜を用い
ているが、これは他の導電膜でも良いことは言うまでも
ない。なお、上記実施例において、業界で一般的に行わ
れている静電耐圧テストである100pF−0Ωで評価
したとき、配線交差部の静電耐圧が50Vであったもの
が200V以上に向上した。これは特に、充分な保護回
路が設けられない半導体装置に対して、実用的効果が大
きい。
Further, the polysilicon film 2 in the second embodiment is divided into two pieces, but it goes without saying that they may be connected in part. Further, although the AL conductive film and the polysilicon film are used as the conductive film in both the first and second embodiments, it goes without saying that this may be another conductive film. In the above example, when the electrostatic breakdown voltage test, which is generally performed in the industry, was evaluated at 100 pF-0Ω, the electrostatic breakdown voltage at the wiring intersection was 50 V, but was improved to 200 V or more. This is particularly effective for a semiconductor device in which a sufficient protection circuit is not provided.

【0016】[0016]

【発明の効果】この発明の半導体装置は、第1の電圧が
加わる第1の導電膜と第2の電圧が加わる第2の導電膜
との間に発生しようとする局所的な高電圧を、中間に位
置した第3の導電膜により空間的に分散させ、静電耐圧
を上げることができる。
According to the semiconductor device of the present invention, a local high voltage to be generated between the first conductive film to which the first voltage is applied and the second conductive film to which the second voltage is applied, It is possible to increase the electrostatic withstand voltage by spatially dispersing the third conductive film located in the middle.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)はこの発明の第1の実施例の半導体装置
の配線交差部の平面図、(b)はそのX−X′断面図で
ある。
FIG. 1A is a plan view of a wiring intersection portion of a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a sectional view taken along line XX ′ of FIG.

【図2】(a)はこの発明の第2の実施例の半導体装置
の配線交差部の平面図、(b)はそのY−Y′断面図で
ある。
FIG. 2A is a plan view of a wiring intersection portion of a semiconductor device according to a second embodiment of the present invention, and FIG. 2B is a sectional view taken along the line YY ′.

【図3】従来の半導体装置の配線模式図である。FIG. 3 is a wiring schematic diagram of a conventional semiconductor device.

【図4】(a)は従来の半導体装置の配線交差部の平面
図、(b)はそのZ−Z′断面図である。
FIG. 4A is a plan view of a wiring intersection portion of a conventional semiconductor device, and FIG. 4B is a ZZ ′ sectional view thereof.

【図5】図4(b)の部分拡大図である。5 is a partially enlarged view of FIG. 4 (b).

【符号の説明】[Explanation of symbols]

1,2 ポリシリコン膜(第3の導電膜) 12 AL膜配線(第2の導電膜) 13 ポリシリコン膜(第1の導電膜) 15 絶縁膜 1, 2 Polysilicon Film (Third Conductive Film) 12 AL Film Wiring (Second Conductive Film) 13 Polysilicon Film (First Conductive Film) 15 Insulating Film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 第1の電圧が加わる第1の導電膜と、こ
の第1の導電膜の上部に絶縁膜を介し前記第1の導電膜
に交差して位置した第2の電圧が加わる第2の導電膜と
を備えた半導体装置であって、 前記第1の導電膜と前記第2の導電膜との間の前記絶縁
膜中に第3の導電膜を設けたことを特徴とする半導体装
置。
1. A first conductive film, to which a first voltage is applied, and a second voltage, which is located above the first conductive film so as to intersect with the first conductive film via an insulating film. A semiconductor device comprising a second conductive film, wherein a third conductive film is provided in the insulating film between the first conductive film and the second conductive film. apparatus.
JP24089493A 1993-09-28 1993-09-28 Semiconductor device Pending JPH0799244A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24089493A JPH0799244A (en) 1993-09-28 1993-09-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24089493A JPH0799244A (en) 1993-09-28 1993-09-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0799244A true JPH0799244A (en) 1995-04-11

Family

ID=17066272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24089493A Pending JPH0799244A (en) 1993-09-28 1993-09-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0799244A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005093887A (en) * 2003-09-19 2005-04-07 Fujitsu Ltd Semiconductor device and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005093887A (en) * 2003-09-19 2005-04-07 Fujitsu Ltd Semiconductor device and method for manufacturing the same

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