JPH0799032A - Vacuum micro-display - Google Patents

Abstract

PURPOSE:To eliminate the deterioration and the removal of a phosphor layer formed on the anode of the electron receiving element of a vacuum micro- display, owing to a high electric field. CONSTITUTION:An electron receiving element at the upper side which has a glass substarte la, an anode 2, a dielectric layer 8, and a phosphor layer 3; and an electron discharge element at the lower side which has a glass substarte 1b, a cathode 4, an insulating layer 5, a gate electrode 6, and an emitter 7 on the cathode 4; are opposed each other, and they are vacuum sealed so as to produce a vacuum micro-display.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a so-called vacuum microdisplay in which micron-sized micro vacuum tubes are integrated on the same substrate by utilizing a microfabrication technique in semiconductors.

[0002]

2. Description of the Related Art With the spread of semiconductor devices, the vacuum tube technology has been forgotten, but in recent years, this vacuum tube technology has been attracting attention. This is the development and application of so-called vacuum microdisplays. Less than,
First, an outline of the background art related to the present invention will be described. At present, the following devices can be used with this vacuum microdisplay technology. Electromagnetic environment device Thermal power, Nuclear power, Automobile, Aircraft, Rocket, Satellite electronics Microwave, Millimeter wave device Millimeter / submillimeter wave, Radio astronomy, Array device, Satellite communication, Array radar beam application Multi-electron beam lithography, Electron beam analyzer Optoelectronics Optical coupling device, high-speed photodetection, laser-modulated electron beam Ultra-high-speed device LSI, three-dimensional electronics Image device TV, monitor, display

This vacuum microdisplay is one in which micron-sized micro vacuum tubes are integrated on the same substrate by utilizing the fine processing technology cultivated in many years of research on semiconductor devices. That is, as shown in a schematic side view of one screen (one chip) of a conventional display in FIG. 5, an electron acceptor having a glass substrate 1a, an anode electrode 2, and a phosphor layer 3, a glass substrate 1b, and a cathode electrode. 4, an insulating layer 5, a gate electrode 6, and an electron-emitting device having an emitter 7 on the cathode electrode 4 are opposed to each other,
Vacuum-sealed by anodic bonding, gate electrode 6
The electron is extracted from the emitter 7 and is emitted to the anode electrode 2. And the gate electrode 6
The amount of electrons emitted from the emitter 7 can be controlled by controlling the voltage applied to the.

In order to put this vacuum microdisplay into practical use, an electron-emitting device is currently being actively studied rather than an electron-receiving device. Broadly speaking, the technical issues of this device are the improvement of the characteristics of the emitter, the vacuum sealing technology, and the development of the phosphor. Emitter It is essential to develop an emitter that emits electrons with high efficiency and stability. The application range is greatly expanded by improving the characteristics of the emitter. So far, including field emission emitters,
The MIS structure, the PN diode, the Schottky junction, and the like have been energetically studied, and the field emission emitter has the highest field emission current density. In a normal semiconductor device, electrons move in a solid, and thus the operation speed is controlled by the mobility of electrons in the solid. On the other hand, the vacuum microdisplay is capable of operating at a very high speed as compared with a semiconductor device because electrons move in a vacuum, and has attracted attention as a charge transport medium that makes the most of the advantages of vacuum. In addition, along with the research on vacuum microdisplays, the development of emitters has been carried out, and those applied to flat displays have been announced. In any case, when commercializing a vacuum microdisplay, the display required unless the emitter of the electron-emitting device is perfect cannot be completed.

Vacuum Sealing Technology Regarding the vacuum sealing technology, it was recently announced that a technique called anodic bonding can be applied to a vacuum microdisplay.
This is a technique in which + is connected to a silicon wafer and − is connected to a glass substrate, and a DC number of 100 V is applied between them to bond them. The advantage is that the temperature does not rise and no gas is released.

Phosphor Recently announced, IVMC91 Technical D
According to igest P58 (1991), 1 × 10 ^-9
In the ultra-high vacuum chamber of Torr, the phosphor is Y ₂ S
Anode current of 90 μA / c using iO ₅ : Tb
m ² and anode voltage AC8KV, about 15000
Using this microchip, green light emission of 66700 cd / m ² was obtained. The grid voltage at this time is AC200V
Is. The disadvantages of these are that the anode voltage and grid voltage are very high, resulting in the deterioration and peeling of the phosphor. That is, there is no phosphor that can be used at medium voltage.
CRT (CRT) for high voltage, VFD for low voltage
Although it is in a (fluorescent display tube), a fluorescent material for an intermediate voltage of a vacuum microdisplay is not currently available. Basically, it is not impossible to use a fluorescent substance for a cathode ray tube, but it is not practical because the driving voltage becomes 20 to 30 KV or 100 KV. On the contrary, the fluorescent substance for the fluorescent display tube has a low voltage and is about 5 to 10 V, so that the field emission current density does not increase. So, the middle of the two, for example AC1
There is a demand for a phosphor that can be driven at around 00V.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the deterioration and peeling of the phosphor layer formed on the anode electrode of the electron receiving element of a vacuum microdisplay due to a high electric field.

[0008]

According to a first aspect of the present invention, an electron accepting element is provided in a vacuum microdisplay in which both an electron emitting element and an electron accepting element are opposed to each other and vacuum sealed by anodic bonding. The vacuum microdisplay is characterized in that a glass substrate, a cathode electrode, a dielectric layer, and a phosphor layer are laminated in this order. Claim 2 of the present invention
2. The vacuum microdisplay according to claim 1, wherein said means comprises a dielectric layer made of BaTiO ₃ . According to a third aspect of the present invention, the vacuum microdisplay according to the first aspect is characterized in that the dielectric layer is made of HfO ₂ . A fourth aspect of the present invention is the vacuum microdisplay according to the second aspect, wherein the phosphor layer is made of ZnO: Zn. A fifth aspect of the present invention is the vacuum microdisplay according to the second aspect, characterized in that the phosphor layer is made of Zn ₂ SiO ₄ : Mn ²⁺ . The means of claim 6 of the present invention is the vacuum microdisplay according to claim 3, wherein the phosphor layer is made of ZnO: Zn. The means of claim 7 of the present invention is the vacuum microdisplay according to claim 3, wherein the phosphor layer is composed of Zn ₂ SiO ₄ : Mn ²⁺ .

FIG. 1 shows a schematic side view of one screen (one chip) of the display of the present invention, and FIG. 2 shows a schematic diagram of the operating circuit of the present invention. In a typical example of an actual vacuum microdisplay, a large number of elements corresponding to the cathode are arranged vertically and horizontally, and the anode side is formed in a flat shape.
As shown in FIG. 1, as in the case of FIG. 5, the electron receiving element having the glass substrate 1a, the anode electrode 2, and the phosphor layer 3 on the upper side, and the glass substrate 1b, the cathode electrode 4, and the insulating layer 5 on the lower side. , An electron-emitting device having a gate electrode 6 and an emitter 7 on the cathode electrode 4 are opposed to each other and vacuum-sealed by anodic bonding. Electrons are extracted from the emitter 7 by the gate electrode 6 and Anode electrode 2
However, in the present invention, the dielectric layer 8 is laminated between the anode electrode 2 and the phosphor layer 3 of the electron receiving element.

A more specific description of the electron-emitting device [cathode side] and the electron-receiving device [anode side] and the operation of the present invention will be described below. Electron-emitting device [cathode side] The glass substrate 1b has a thickness sufficient to support this device, and a wiring layer (cathode electrode 4) is formed on the upper surface thereof. An emitter 7 and an insulating layer 5 are formed on this wiring layer, and a gate electrode 6 is formed on the insulating layer 5. The wiring layer on the glass substrate 1b is for supplying a voltage to the emitter 7, and ITO, ZnO: A
transparent conductive film such as l, Al, Au, W, Mo, Ti, T
a, Nb, Cr metal thin film, 0.02-1.0 μm
It is formed by forming the film to a thickness of a certain degree. The emitter 7 formed thereon is a conical metal made of a refractory metal such as W, Ta or Mo. Also, the insulating layer 5
Is a layer obtained by depositing SiO ₂ , Al ₂ O ₃ or the like to a thickness of about 0.5 to 3.0 μm, and the gate electrode 6 is made of Al, Au, W, Mo, Ti, Ta, Nb
It is configured by forming a metal thin film such as the above to a thickness of about 0.02 to 1.0 μm. The gate electrode 6 is located at almost the same height as the tip of the emitter 7.

Electron Accepting Element [Anode Side] On the lower surface of the glass substrate 1a, an anode electrode 2, a dielectric layer 8 and a phosphor layer 3 are formed. Anode electrode 2
Is a transparent conductive film of ITO, ZnO: Al, etc.
The dielectric layer 8 is formed to have a thickness of about 1.0 μm, and the dielectric layer 8 is made of Al ₂ O ₃ , SiO ₂ , HfO ₂ , BaTi.
O ₃ , PbTiO ₃ , SrTiO ₃ , Si ₃ N ₄ , Ta
₂ O ₅ , BaTa ₂ O ₆ , Sm ₂ O ₃ , Y ₂ O ₃ etc. are formed in a thickness of about 0.5 to 2.0 μm.
The phosphor layer 3 is made of ZnO: Zn, Zn ₂ SiO ₄ : Mn, or the like with a thickness of 20 to 50 μm.

Operation The electron receiving element and the electron emitting element are arranged so as to face each other as shown in FIG. 1, and the space between them is kept in a vacuum state. A vacuum microdisplay having such a structure operates similarly to a vacuum tube. That is, when the emitter 7 shown in FIG. 2 is a cathode, the anode electrode 2 is an anode, and the gate electrode 6 is a grid, a predetermined voltage is applied to each electrode, electrons can be extracted from the emitter 7 and emitted to the anode. ， The emission amount of this electron can be controlled by the voltage applied to the grid. In other words, when a constant voltage (Va) is applied between the anode electrode 2 and the cathode electrode 4 and the voltage is gradually applied to the gate electrode 6, electrons are emitted from the emitter 7. The amount of the emitted electrons depends on the applied voltage (V
It can be controlled by g). The electrons emitted from the emitter 7 collide with the phosphor layer 3, and the inner-shell electrons of the emission center, which have transitioned from the ground level to the excitation level, are radiatively relaxed to the ground level again to emit light. At this time, the dielectric layer 8 functions to regulate the voltage applied to the phosphor layer 3 and protect it from electrical breakdown. This light is emitted from the anode electrode 2 to the glass substrate 1a.
Observed through.

The dielectric layer 8 at this time is for the purpose of protecting the phosphor layer 3 from electrical breakdown. The condition of the dielectric layer 8 is
High dielectric strength, high dielectric constant, small tan δ (dielectric loss tangent, which is a measure of dielectric loss), and excellent adhesion to the phosphor layer 3, dense amorphous, and few pinhole defects That is. The film quality is evaluated by the maximum charge density (non-dielectric constant x dielectric strength (μC
/ Cm ² )). As a result of the evaluation, as the dielectric layer 8 used in the present invention, Al ₂ O ₃ , SiO ₂ , H
fO ₂ , BaTiO ₃ , PbTiO ₃ , SrTiO ₃ ,
_{Si 3 N 4, Ta 2 O} 5, BaTa 2 O 6, Sm
₂ O ₃ , Y ₂ O _3, etc. were good. Among these, the better ones were BaTiO ₃ and HfO ₂ . That is, as the dielectric constant of the dielectric layer 8 is larger, the electric field is effectively applied to the phosphor layer 3 (light emitting layer), and the voltage of the device can be lowered,
The deterioration of the phosphor layer 3 is small.

In the present invention, focusing on the embodiment,
Although explained with a flat pattern, segment display,
Dot display is also possible. In that case, the display pattern on the anode side is processed and formed by photolithography, and the position of the emitter on the cathode side is opposed to the display pattern. At that time, high brightness display can be performed by making several to several tens of emitters face each other in one segment or one pixel and increasing the integration degree of the emitters.

[0015]

Example An electron-emitting device was prepared as follows. On the glass substrate 1b, the wiring layer (cathode electrode 4
(For use), ITO, ZnO: Al, Al, Au, W,
One kind of Mo, Ti, Ta, Nb, Cr or the like is formed by a sputtering method. Then, an Si layer is formed on the wiring layer as an insulating layer.
One of O ₂ and Al ₂ O ₃ and Al for the gate electrode,
One of Au, W, Mo, Ti, Ta, and Nb is formed by the sputtering method. Then, a resist layer is formed on the gate electrode layer, and the resist layer is patterned by photolithography. That is, an opening is formed in a part of the resist layer and a part of the gate electrode layer is exposed. This opening is provided in the region where the emitter 7 is to be formed. Therefore, if the columnar emitter 7 is formed, the opening becomes a circular window, and if the square columnar emitter 7 is formed, the opening becomes a square window. Then, etching is performed using the patterned resist layer as a mask. A part of the gate electrode layer and a part of the insulating layer thereunder are removed. As a result, the insulating layer 5 and the gate electrode 6 are formed. Insulating layer 5 and gate electrode 6
Has a shape surrounding the emitter 7 formed later. It is preferable that the insulating layer is slightly over-etched when the insulating layer is etched so that the side surface of the insulating layer 5 is slightly recessed.

Next, the metal W, Mo, Ti, Ta, Nb, Au, A which later constitutes the emitter 7 is formed on the entire surface of this substrate.
g, Cu, etc. are deposited. Here, two types of emitter electrode material layers are formed. One is a layer deposited in the hole (emitter formation region) created by the etching in the previous stage, and the other is a layer deposited in the other region. It is desirable that the thickness of these emitter electrode layers is equal to or less than the sum of the thickness of the insulating layer 5 and the thickness of the gate electrode 6. Next, the formed resist layer is peeled off from the upper surface of the gate electrode 6. That is, the resist layer and the unnecessary emitter electrode material layer thereabove are removed. The remaining emitter electrode material constitutes the emitter 7. In this state, since it is in contact with the gate electrode 6, a slightly smaller resist layer is formed on the upper surface of the remaining emitter electrode material. In other words, a resist layer is formed so that only a part of the periphery of the remaining emitter electrode material can be etched.
Then, the resist layer is used as a mask to etch away the vicinity of the remaining emitter electrode material to form the emitter 7. A predetermined distance is maintained between the emitter 7 and the gate electrode 6 surrounding the emitter 7.

The conditions relating to the above will be shown. Wiring layer (for cathode electrode 4): ITO High frequency sputtering device target: In ₂ O ₃ : SnO ₂ = 95: 5
Purity 99.95% Substrate temperature: 180 to 300 ° C. Sputtering gas pressure: 8 × 10 ⁻⁴ to 2 × 10 ⁻³ Torr Sputtering gas: Ar (10 to 50 sccm (standard state cm ³ per minute)) Sputtering power: 400 to 700 W film thickness: 100 to 200 nm After sputtering, air baking was performed at 520 ° C. for 70 min. Insulating layer: SiO ₂ high frequency sputtering device Target: SiO ₂ purity 99.9% Substrate temperature: 150 to 230 ° C. Sputtering gas pressure: 3 × 10 ⁻³ Torr Sputtering power: 400 to 700 W Sputtering gas: Ar (18 sccm), He ( 12
sccm) Film thickness: 1 μm After sputtering, air baking was performed at 520 ° C. for 70 min. Gate electrode layer: Al DC sputtering device Target: Al purity 99,999% Substrate temperature: Room temperature (RT) Sputtering gas pressure: 3 × 10 ⁻³ Torr Sputtering gas: Ar (30 sccm) Sputtering current: 1A Film thickness: 0.5 μm

Resist layer Coating of resist: OFPR 8600 (30 cp) 3500 rpm 20 sec Exposure: Light source 436 nm Proximity gap 10 μm Development: NMD-3, room temperature, 60 sec Etching: For SiO ₂ : H ₂ O: HF: NH ₄ F = 46: 7: 4
7 (Capacity ratio) Temperature 40 ° C., 5 min For Al: H ₂ O: HNO ₃ : CH ₃ COOH: H
₃ PO ₄ = 83: 2: 10: 3 (capacity ratio) Temperature 43 ° C., 3 min Resist stripping: Organic solvent

Next, an electron receiving element was prepared as follows. A transparent conductive film for the anode electrode 2 was formed on the upper glass substrate 1a having a predetermined size in a certain area by a high frequency sputtering device. The conditions are as follows. Transparent conductive film (for anode electrode 2): ITO high frequency sputtering device target: In ₂ O ₃ : SnO ₂ = 95: 5
Purity 99.95% Substrate temperature: 180 to 300 ° C. Sputtering gas pressure: 8 × 10 ⁻⁴ to 2 × 10 ⁻³ Torr Sputtering gas: Ar (10 to 50 sccm (standard state cm ³ per minute)) Sputtering power: 400 to 700 W film thickness: 100 to 200 nm After sputtering, air baking was performed at 520 ° C. for 70 min.

Next, the transparent conductive film was etched to a predetermined size under the following conditions. Washing / drying: Freon washing Resist coating: OFPR 8600 (30 cp) 3500 rpm, 20 sec Exposure: Light source g-line (436 nm), proximity gap 10 μm, time 7 sec Development: NMD-3, room temperature, 60 sec Drying: 100 ° C., 30 min Etching: HCl: FeCl ₃ : H ₂ O = 2
3: 4: 20 (capacity ratio) Temperature 43 ° C, 4.5 min Resist stripping: Organic solvent cleaning, drying: Freon drying

Next, for the formation of the dielectric layer 8, a film was formed by a high-frequency sputtering device while masking under the following conditions using a dedicated jig. High-frequency sputtering device Target: HfO ₂ purity 99.99% Gas out: 170 ° C. 30 min Substrate: Room temperature Sputtering gas pressure: 8 × 10 ⁻⁴ to 2 × 10 ⁻³ Torr Sputtering gas: Ar: O ₂ = 20 to 30: 5 -10
sccm Sputtering power: 0.8 to 1.5 W Film thickness: 0.5 to 2.0 μm

Next, the phosphor layer 3 was formed. The following components were deposited on the above dielectric layer 8 of HfO ₂ by a screen printing method. As a method of forming this layer, another physical thin film forming method can be used. Component ratio Zn ₂ SiO ₄ : Mn ²⁺ (particle size: several microns) 70-8
0 wt% cyanoethyl pullulan / dimethylformamide solution (concentration 60%) 20 to 30 wt% A mixture of the above component ratios was homogenized with 0.5 to 1.
Mixing and stirring were performed for 0 h under the conditions of 1000 to 3000 rpm. This component ratio changes the mixing ratio of the phosphor and the cyanoethyl pullulan / dimethylformamide solution at a constant film thickness, and the vicinity of the point where the dielectric constant rises 10 to 30% from the vicinity where the dielectric constant sharply rises. The optimum mixing ratio was obtained. The film thickness was controlled to be 20 to 50 μm. The method was carried out by setting the emulsion thickness of the screen printing plate to, for example, 40 μm, setting the printing pressure, and the distance between the screen and the printed matter. The drying was performed at 150 to 200 ° C. for 60 minutes in N ₂ atmosphere.

FIG. 3 shows a vacuum microdisplay evaluation apparatus (IEEE T) for measuring the evaluation characteristics of the present invention.
RANS. ELECTRON DEVICES Vo
l. 38, No. 10, p. (Described in 2350). This measuring device is 10 ^-9 to 10 ^-10 Tor
The characteristics are measured in an atmosphere of a vacuum degree of r, the temperature is room temperature and normal humidity (variable from −150 to + 150 ° C.), the probe 19 is operated from the outside with the XYZ manipulator 17, and the electrode is brought into contact with the electrode. Apply voltage. The luminance at that time is externally measured by the luminance meter 20. Before measurement, the inner wall of the chamber is cleaned with a UV bake (lamp) 16 and the measurement electrode terminals are cleaned with an argon ion gun 12.

FIG. 4 shows the anode voltage in the operation measuring circuit shown in FIG. 2 for the vacuum microdisplay provided with the dielectric layer 8 according to the embodiment of the present invention and the vacuum microdisplay without the dielectric layer 8 of the prior art. AC for (Va)
The frequency is 10
The results of brightness (brightness) when a gate voltage (Vg) is changed in a vacuum degree of 3 × 10 ⁻⁹ Torr by applying a 0 Hz sine wave are shown. As shown in FIG. 4, it can be seen that there is a clear difference between the presence and absence of the dielectric layer 8.

[0025]

According to the present invention, the emission efficiency of electrons from the emitter side of a vacuum microdisplay is high, and the display does not generate heat as a whole. Moreover, it can be driven at a low voltage and the phosphor layer is electrically connected. It is possible to protect the display from destruction and emit high-intensity light, which allows the display to be made compact.

[Brief description of drawings]

FIG. 1 One screen (one chip) of a display of the present invention
FIG.

FIG. 2 shows a schematic diagram of an operating circuit of the invention.

FIG. 3 shows a schematic view of an apparatus for measuring evaluation characteristics of the present invention.

FIG. 4 is a diagram illustrating a gate voltage (V) of an example of the present invention and a conventional example.
The result of the change of brightness (brightness) when g) is changed is shown.

FIG. 5 shows a schematic side view of one screen (one chip) of a conventional display.

[Explanation of symbols]

 1 Glass Substrate 2 Anode Electrode 3 Phosphor Layer 4 Cathode Electrode 5 Insulating Layer 6 Gate Electrode 7 Emitter 8 Dielectric Layer

Claims (7)

[Claims] 1. In a vacuum microdisplay in which an electron-emitting device and an electron-accepting device are opposed to each other and vacuum-sealed, the electron-accepting device is layered in the order of a glass substrate, a cathode electrode, a dielectric layer, and a phosphor layer. A vacuum microdisplay characterized by the above. 2. The vacuum microdisplay according to claim 1, wherein the dielectric layer is made of BaTiO ₃ . 3. The vacuum microdisplay according to claim 1, wherein the dielectric layer is made of HfO ₂ . 4. The vacuum microdisplay according to claim 2, wherein the phosphor layer is made of ZnO: Zn. 5. The vacuum microdisplay according to claim 2, wherein the phosphor layer is made of Zn ₂ SiO ₄ : Mn ²⁺ . 6. The vacuum microdisplay according to claim 3, wherein the phosphor layer is made of ZnO: Zn. 7. The vacuum microdisplay according to claim 3, wherein the phosphor layer is made of Zn ₂ SiO ₄ : Mn ²⁺ .