JPH0798943A - Cd-rom device - Google Patents

Abstract

PURPOSE:To suppress the mis-fetch of data or reading impossibility to a minimum by performing the retrying of data by switching the rotating speed of a disk to unmultiplied speed when the data is set in an uncorrectable state and correction is applied to the data again during the reproduction of it. CONSTITUTION:A discrimination circuit 19 discriminates an operation to be executed at the next by a correction result, the present reproducing speed, and search information, and supplies a discriminated result to a system control circuit 6. The system control circuit 6 generates and outputs an instruction signal to generate a switching instruction signal for unmultiplied/four-fold speed and to search tracks (one, two, and three tracks) before N tracks with data readout target address based on the discriminated result of the discrimination circuit 19.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a CD device and a CD-ROM.
Relating to ROM device, CD-RO capable of playing back any integer multiple speed
M device.

[0002]

2. Description of the Related Art The main purpose of a CD-ROM device is to search for a target position in response to a command from an external device such as a host computer, read the target data from the data recorded on the disc, and perform CD correction and CD- Transferring to an external device via the ROM correction processing unit and I / F circuit. In recent years, the specifications for high-speed operation required for CD-ROM devices have become severer year by year. Techniques necessary for satisfying the requirements for those high-speed operations include high-speed search, high-speed reproduction (reading of data at 4 × speed, etc.), high-speed error detection / correction, and high-speed transfer to an external device. As shown in FIG. 4 (b), in the case of a conventional CD-ROM device that realizes high-speed reproduction such as quadruple speed, the RF signal detected through the pickup and head amplifier is compared with the normal 1 × speed reproduction in the time axis. The direction jitter is quite severe.

These are mainly because the absolute jitter amount is the same as in the case of the 1 × speed, but the relative jitter increases due to the high speed reproduction. For this reason, if a scratched disc or the like is played back at an arbitrary integer multiple speed, it is likely to be uncorrectable, and in many cases it will be uncorrectable again even if a retry of correction is performed. As a countermeasure, a correction circuit, especially a CD
-A possible method is to improve the correction capability of the ROM part.
In high-speed reproduction, the correction time is the inverse of an arbitrary integer multiple compared to 1 × speed, so it is very difficult to increase the correction capability in high-speed reproduction. Therefore, even at the time of high-speed reproduction, a method of reducing the number of corrections to lower the data error rate specification is even taken.

A conventional CD-ROM device is shown in FIG. The signal read from the disk 52 by the optical pickup 51 is input to the RF amplifier circuit 53. The RF amplifier circuit 53 extracts the focus error signal and the tracking error signal from the output of the optical pickup 51, supplies them to the servo control circuit 54, and outputs the level slice signal.
The amplified RF signal is supplied to the PLL circuit 55.

The level slice / PLL circuit 55 binarizes the RF signal to obtain an EFM signal. At the same time, in order to read this EFM signal, a PLL clock synchronized with the EFM signal is generated. The center frequency of the VCO of the PLL circuit is 1
It is 7.2872MHz, and this frequency is used as a reference at 4x speed, and at 1x speed, it is divided by ¼ to 4.3218M.
Hz is the standard. Switching is system control circuit 5
This is performed by the 1x / 4x speed switching instruction signal output from S6.

The binarized EFM signal is supplied to the CD sync detection circuit 57 and the CD signal processing circuit 58. The CD sync detection circuit 57 detects the CD sync signal using the PLL clock. The detected sync signal is the CD signal processing circuit 5
8 and the disk motor servo circuit 59. The disk motor servo circuit 59 compares the frequency of the CD sync signal having a time axis fluctuation with the X'TAL reference signal having no time axis fluctuation in frequency and phase, extracts an error component, converts the voltage into a voltage, and amplifies the disk motor 60. To control.

In the case of quadruple speed, C which is 29.4 KHz
Frequency and phase comparison is performed between the D synchronization signal and 29.4 KHz obtained by dividing the master clock of 33.8688 KHz by 1/1152. In the case of 1 × speed, the CD sync signal becomes the original 7.35 KHz, and 29.4 KHz obtained by dividing the master clock by 1/1152 is further divided by 1/4 to generate 7.35 KHz. Similarly, frequency and phase comparison is performed.

On the other hand, the CD signal processing circuit 58 performs data separation and EFM demodulation by using the CD synchronizing signal and the PLL clock, and writes the data in the RAM 61 by the PLL clock. By reading this data with the master clock, the time axis fluctuation due to the disk motor 60 is absorbed. At the same time, correction processing is performed, and the output signal is selected by the selector 6
The signal is supplied to the interpolating circuit 63, the CD-ROM sync detecting circuit 64, and the descramble circuit 65 via 2. The selector 62 is switched by an audio / ROM switching instruction signal output from the system control circuit 56.
When the instruction signal is audio, data is supplied to the interpolation circuit 63. The interpolation circuit 63 interpolates the data only when the data has an error flag, and outputs the output D
Data is converted from digital to analog by the A converter 66 and is output as a reproduced audio signal through an LPF (low pass filter) 66a.

On the other hand, when the instruction signal is ROM, the CD-R
Data is supplied to the OM synchronization detection circuit 64 and the descramble circuit 65. The CD-ROM sync detection circuit 64 detects the CD-ROM sync signal from the CD-ROM data and supplies it to the CD-ROM signal processing circuit 67. The descramble circuit 65 descrambles the CD-ROM data and supplies it to the CD-ROM signal processing circuit 67. The CD-ROM signal processing circuit 67 performs correction processing of CD-ROM data, writing of data to the buffer memory 68, and reading control. The correction result is supplied to the system control circuit 56. The data read from the buffer memory 68 is transferred to the host computer through the I / F control circuit 69. The system control circuit 56 is for searching, turning on / off the operation of each circuit CD-
It controls the operation of the entire ROM. 1x speed when playing audio discs, 4 when playing CD-ROM discs
A double speed switching instruction signal is output. If the result of the correction indicates that the correction cannot be made, a retry is performed. The 1 × / 4 × speed switching instruction signal is sent to the disk motor servo circuit 59, PLL.
It is supplied to the circuit 55 and the X TAL frequency dividing circuit 70. The search instruction signal is supplied to the servo control circuit 54.

FIG. 6 is a flow chart for explaining the retry operation when the conventional CD-ROM device cannot correct. The disk 52 is set in the CD-ROM device and reproduction is started (a to c). At this time, the system control circuit 56 resets the correction retry count N to 0 (b). The CD-ROM signal processing circuit 67 corrects the CD-ROM data read from the disk 52 for each block (d). Next, it is judged whether or not these corrections are completed, and if they are completed, the correction processing for the next block is performed (e, f). If the block cannot be corrected, the track before the track including the block is searched (e, g, h). Next, the system control circuit 56 performs an operation of adding 1 to the number N of correction retries, and performs a second correction operation again (i,
c, d).

It is judged whether the second correction is completed, and if it is completed, the correction process for the next block is performed (e, f).
If the block cannot be corrected, the track before the track including the block is searched for (e, g, h).
Next, the system control circuit 56 performs an operation of adding 1 to the number of correction retries N, and performs the third correction operation again (i, c, d).

It is judged whether or not the third correction is completed, and if it is completed, the correction process for the next block is performed (e, f).
If the block cannot be corrected, the track before the track including the block is searched for (e, g, h).
Next, the system control circuit 56 performs an operation of adding 1 to the number N of correction retries, and performs the fourth correction operation again (i, c, d).

It is judged whether or not the fourth correction is completed, and if it is completed, the correction processing of the next block is performed (e, f).
If the block cannot be corrected, the number of retries N becomes 3, and it is determined that the block cannot be corrected, and the process ends (g, j, k).

As described above, in the conventional CD-ROM device,
Since the correction is performed again at the same speed as the rotation speed that was reproduced at the beginning, there was a problem that data was lost or unreadable.

[0015]

As described above, according to the conventional CD-ROM device, the correction is performed again at the same rotation speed as the reproduction speed at the beginning, so that data may be missed or unreadable. There was a flaw.

In view of the above, the present invention eliminates the above-mentioned drawbacks and becomes uncorrectable during the reproduction of data. When correcting again, the rotational speed of the disk is slowed to make the influence of jitter relatively advantageous and retry is performed. The purpose is to minimize missed data and unreadable data.

[0017]

In order to achieve the above object, according to the present invention, there is provided a data reading means for performing high speed reproduction and variable speed reproduction of data recorded on a disc by an arbitrary positive multiple, and the data reading. Correction means for correcting the data read by the correction means and correction determination retry means for correcting again by the correction means, and the correction means corrects the data being read at an arbitrary rotation speed. When the correction determination retry unit executes the retry, the data reading unit changes the rotation speed to read the data that cannot be corrected again and perform a correction process.

[0018]

With the above-mentioned structure, when the data cannot be corrected during the data reading, the correction judgment retry means corrects the speed, and the high speed and variable speed reproducing means change the rotation speed of the disc to make a retry. The correction efficiency of can be improved.

[0019]

Embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a CD-ROM device according to an embodiment of the present invention. The signal read from the disc 2 by the optical pickup 1 is input to the RF amplifier circuit 3. The RF amplifier circuit 3 extracts the focus error signal and the tracking error signal from the output of the optical pickup 1, supplies them to the servo control circuit 4, and supplies the amplified RF signal to the level slice / PLL circuit 5.

The level slice / PLL circuit 5 binarizes the RF signal to obtain an EFM signal. At the same time, in order to read this EFM signal, a PLL clock synchronized with the EFM signal is generated. The center frequency of the VCO of the level slice / PLL circuit 5 is 17.2872 MHz, and this frequency is the standard at the 4 × speed, and the 1/4 frequency divided by 4.3218 MHz is the standard at the 1 × speed. The switching is performed by a 1x / 4x speed switching instruction signal output from the system control circuit 6.

The binarized EFM signal is supplied to the CD sync detection circuit 7 and the CD signal processing circuit 8. The CD sync detection circuit 7 detects the sync signal of the CD using the PLL clock. The detected synchronizing signal is supplied to the CD signal processing circuit 8 and the disc motor servo circuit 9. The disk motor servo circuit 9 compares the frequency of the CD sync signal having a time axis fluctuation with the X'TAL system reference signal having no time axis fluctuation, extracts an error component, converts it into a voltage, and amplifies it.
The disk motor 10 is controlled.

At 4 × speed, C is 29.4 KHz.
Frequency and phase comparison is performed between the D synchronization signal and 29.4 KHz obtained by dividing the master clock of 33.8688 KHz by 1/1152. In the case of 1 × speed, the CD sync signal becomes the original 7.35 KHz, and 29.4 KHz obtained by dividing the master clock by 1/1152 is further divided by 1/4 to generate 7.35 KHz. Similarly, frequency and phase comparison is performed.

On the other hand, the CD signal processing circuit 8 performs data separation and EFM demodulation by using the CD synchronizing signal and the PLL clock, and writes the data in the RAM 11 by the PLL clock. By reading this data with the master clock, the time axis fluctuation due to the disk motor 10 is absorbed.
At the same time, correction processing is performed, and the output signal is supplied to the interpolation circuit 13 or the CD-ROM synchronization detection circuit 14 and the descramble circuit 15 via the selector 12.

The selector 12 is switched by an audio / ROM switching instruction signal output from the system control circuit 6. When the instruction signal is audio, data is supplied to the interpolation circuit 13. The interpolating circuit 13 interpolates the data only when the data has an error flag, and the DA converter 16 converts the data from digital into analog and outputs it as a reproduced audio signal through an LPF (low pass filter) 16a.

On the other hand, when the instruction signal is ROM, CD-ROM
Data is supplied to the synchronization detection circuit 14 and the descramble circuit 15. In the CD-ROM sync detection circuit 14, the CD
-Detect the CD-ROM sync signal from the ROM data,
The signal is supplied to the CD-ROM signal processing circuit 17. The descramble circuit 15 descrambles the CD-ROM data and supplies it to the CD-ROM signal processing circuit 17.
The CD-ROM signal processing circuit 17 performs correction processing of CD-ROM data and writing / reading control of data to / from the buffer memory 18.

The correction result by the CD-ROM signal processing circuit 17 is supplied to the judging circuit 19. The data read from the buffer memory is transferred to the host computer through the I / F control circuit 20. The determination circuit 19 determines the operation to be performed next based on the correction result, the current reproduction speed and the search information, and supplies the determination result to the system control circuit 6. The system control circuit 6 controls the operation of the entire CD-ROM device such as searching and ON / OFF operation of each circuit as in the conventional case. In addition to this, in this embodiment, the 1 × / 4 × speed is determined based on the determination result of the determination circuit 19. Generation of switching instruction signal and generation and output of an instruction signal as to whether to search N tracks before (1st, 2nd, 3rd track) of the data read target address. The switching signal of 1x / 4x speed is sent to the disk motor servo circuit 9, PLL circuit 5, X'TAL.
It is supplied to the frequency dividing circuit 21 and the determination circuit 19.

FIG. 2 is a flow chart for explaining the retry operation when the CD-ROM device of this embodiment cannot be corrected. The disk 2 is set in the CD-ROM device and reproduction is started (a to c). At this time, the system control circuit 6 resets the correction retry count N to 0 (b). CD-ROM signal processing circuit 8
In step (d), the CD-ROM data read from the disk 2 is corrected block by block. Next, it is judged whether or not these corrections are completed, and if they are completed, the correction processing of the next block is performed (e to g). At f, it is judged whether or not it is reproduced at 4x speed, and if it is 4x speed, it immediately moves to the next block. If it is not 4x speed, it is changed to 4x speed and the track including the next block is searched. (Fi).

If uncorrectable, it is determined whether or not the speed is 1 × speed. If the speed is 1 × speed, a track including a block two blocks before the uncorrectable block is searched and retry operation is performed up to three times (j to l). . If the number of retries is 3, it is determined that the correction cannot be completely performed and the retry operation is stopped (k,
m, n).

If the number of retries is not 0x and the number of retries is 0, it is determined whether the correction is within 16 blocks after the search operation. If it is within 16 blocks, four tracks before the uncorrectable block is searched. Perform a retry operation (o to q). If it is not within 16 blocks after the search operation in p, the speed is changed to 1 × speed, the track including one block before the uncorrectable block is searched, and the retry operation is performed (r, s).

When the number of retries is not 0 at o, the speed is changed to 1 × speed, the track including one block before the uncorrectable block is searched, and the retry operation is performed (o,
r, s).

When the operations of l, q, and s are completed, the system control circuit 6 makes a correction retry count N.
The operation of adding 1 to is performed, and the second correction operation is performed again (t).

FIG. 3 is an explanatory diagram showing the judgment standard in the judgment circuit 19 of this embodiment. In this embodiment, as shown in FIG. 4, the high-speed reproduction of 4 × speed is switched to the 1 × speed for reproduction, whereby the relative time axis jitter of the input RF waveform is reduced, and the probability that correction will become uncorrectable is extremely high. It becomes low.

[0033]

According to the present invention having the above structure,
During the correction process, the high-speed reproduction of an arbitrary integer multiple speed is switched to the single-speed reproduction for reproduction, whereby the relative time axis jitter of the input RF waveform is reduced and the correction efficiency is improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a CD-ROM device according to an embodiment of the present invention.

FIG. 2 is a flow chart diagram illustrating a retry operation at the time when correction is impossible in the embodiment of FIG.

FIG. 3 is an explanatory diagram showing a determination standard in the determination circuit 19 of FIG.

FIG. 4 is an explanatory diagram showing an RF waveform during quadruple speed reproduction in the embodiment of FIG.

FIG. 5 is a block diagram showing a conventional CD-ROM device.

FIG. 6 is a flowchart illustrating a retry operation when a conventional CD-ROM device cannot correct.

[Explanation of symbols]

2 ... Disc, 3 ... RF amplifier, 6 ... System control circuit, 7 ... CD synchronization detection circuit, 8 ... CD signal processing circuit, 9 ... Disc motor servo circuit, 14 ... CD-RO
M synchronization detection circuit, 19 ... Judgment circuit.

Claims (2)

[Claims] 1. A data reading means for performing high-speed reproduction and variable-speed reproduction of data recorded on a disc by an arbitrary positive multiple, correction means for correcting the data read by the data reading means, Correction determination retry unit for correcting again in the correction unit, and when the data being read at an arbitrary rotation speed cannot be corrected by the correction unit, and the retry is executed by the correction determination retry unit, A CD-ROM device characterized in that the data reading means changes the rotational speed to read and correct the data that has become uncorrectable again. 2. The CD-ROM device according to claim 1, wherein when the data is read again by the correction determination retry means, the data is read from a few tracks before a track including a block in which the data is recorded.