JPH0797853B2 - Digital signal recorder - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a device for recording and reproducing an encoded audio signal together with a video signal on a magnetic tape by a rotary magnetic head type scanner, and in particular, a sample of a PCM audio signal. It is suitable when the relationship between the digitization frequency and the rotation frequency of the scanner is asynchronous.

[Conventional technology]

The PCM method has been introduced in order to improve the quality of audio signals accompanying video.

Here, in 8mm Video, although the audio PCM system is adopted, the sampling frequency of the audio PCM signal is twice the horizontal synchronizing signal repetition frequency, and the sampling frequency ( 32KHz, 44.1KHz and 48KHz). For example, the sampling frequencies of audio PCM signals for satellite broadcasting are 32 KHz and 48 KHz.

On the other hand, in the MUSE method, which is one of the transmission methods of high-definition television, the sampling frequency of the audio PCM signal is set to 32 KHz and 48 KHz, so if you try to record the data sampled at the same sampling frequency in field units The number of data per field becomes a fraction, which causes inconvenience. As a method for solving this inconvenience, a packet transmission method having a leap field (leap field) for absorbing the surplus described in NHK Giken monthly report 27-7 P.282 is adopted.

In addition, the video disc has the same format as the compact disc and records PCM audio with a sampling frequency of 44.1 KHz.

However, when trying to record PCM audio in a device that records or transmits signals discontinuously in time, such as a video tape recorder, the following disadvantages occur. First, if the sampling frequency of the audio signal cannot be divided by the field frequency of the video signal, the above-mentioned inconvenience occurs in coding. For this reason, there is a solution method such as the above-mentioned MUSE method. In this case, the field frequency _{V of the} video signal, or the rotation frequency _{D of the} head scanner rotating in synchronization with this and the sampling frequency _{S of the} audio signal are used. It was necessary to establish a synchronization relationship between the two, which was a condition that limits the range of application of the system.

Furthermore, as a device for recording and reproducing only the audio signal on the rotary head type VTR by PCM, the Japan Electronic Machinery Manufacturers Association technical standard PCZ
-105 consumer PCM encoder / decoder (established 1983.9)
Is mentioned. As a recording / reproducing device based on this technical standard, for example, Presented at the 69 Convention, May 12-15, 1981 Los Angeles AES 1791 (B-6) (Presented at the 6
9th Convention 1981 May12−15 Los Angeles AES 1791
(B-6)) Digital Audio / Video Combination Recorder Using Custom MDS L.S.I.S., I.S. (Digital Audio / Video Combination Recorder Using C)
ustom Made LSI's, IC's) in Figures 1 and 14. In the same paper, for example, in the case of NTSC, the field frequency _V and the sampling frequency _S are divided from the same master clock, and there is a relation of _S = 735 _V between them, so that the number of samples per field is 735 constant. ing.

Further, FIG. 1 of the same paper shows a block diagram of a device configuration for recording / reproducing a sampled PCM signal. In the figure, the address of the RAM serving as the interleave memory is controlled by the address control circuit.

However, in this example, the field frequency _V and the sampling frequency
It is based on the premise that _S has a certain relationship,
No consideration was given to the case where _V and _S are uncorrelated.

[Problems to be solved by the invention]

In the above conventional technique, the sampling frequency of the audio signal is not an internationally generalized sampling frequency, the number of quantization bits is small, and there is a synchronous relationship between the audio signal sampling frequency and the field frequency. However, when trying to record audio with a video signal from a camera and a direct digital signal from a CD (compact disc), for example, the sampling frequency is different or between the sampling frequency and the field frequency. It was extremely difficult to record both at the same time because there was no synchronization.

An object of the present invention is to realize a video tape recorder capable of recording a digital audio signal having a sampling frequency internationally standardized together with a video signal having a field frequency having no synchronous relationship with this frequency.

[Means for solving problems]

The above-mentioned object is, in a digital signal recording apparatus adapted to multiplex-record an encoded digital audio signal together with a video signal, an input amount of the digital audio signal to a memory and a memory for recording the digital audio signal. This is achieved by providing a circuit for detecting a difference from the output amount and a circuit for controlling the amount of the digital audio signal for recording by the detection output of the detection circuit.

[Action]

In the recording system, the input sampling signal is once written in the memory, is subjected to a predetermined encoding process, is interleaved, and is sequentially read from the memory to form a signal for recording on the tape. . The writing cycle to the memory depends on the input sampling signal cycle, and the reading cycle depends on the field cycle of the video signal.

Here, by providing a circuit for detecting the difference between the input amount of the digital audio signal to the memory and the output amount from the memory for recording the digital audio signal, for example, when the input sampling signal period becomes short. When the difference between the detection outputs becomes large and the input sampling signal period becomes long, the operation is performed so that the difference between the detection outputs becomes small.

By providing a circuit for controlling the amount of the digital audio signal for recording by the detection output of the detection circuit, the number of sampling signals recorded in one field increases when the difference between the detection outputs is large, When the difference between the detection outputs is small, the number of sampling signals recorded in one field decreases. By this operation, it is possible to record and reproduce the digital audio signal together with the video signal even if the input sampling cycle and the field signal cycle of the video signal have no synchronization relationship.

〔Example〕

 An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows the structure of a rotary head type PCM signal recording / reproducing apparatus.

At the time of recording, analog signals of 2 channels of L and R are input from the input terminal 1. The input signal is amplified to a predetermined level by the amplifier circuit 2, band-limited by the filter 3, and then sampled by the sample-hold circuit 4. The sampled input signal is sequentially input to the A / D converter 6 by the switching circuit 5 and converted into a PCM signal. The signal converted by the A / D converter 6 is written in the RAM 15 through the bus line 14. Then, the PCM signals are arranged and error correction codes are added according to a predetermined format. The error correction code is added using the error correction circuit 20. After arranging the PCM signal and adding the error correction code, each data is read from the RAM. Writing, arranging, adding and reading correction codes of these PCM signals are performed by the address generation circuits 17 to 19 and the address switching circuit.
This is done by controlling the RAM address by 16. At this time, the read address generation circuit 19 determines the difference between the write address and the read address extracted by the address difference extraction circuit 33 by the number of audio signal samples in one field counted by the in-field sample number counting circuit 36. Judgment circuit
Based on the signal determined in 34, control is performed so that the number of samples set by the in-field sample number setting circuit 35 is obtained. The signal read from the RAM is converted into a serial signal by the parallel-serial conversion circuit 23. Then, the control signal circuit 24 and the switching circuit 25
When the number of audio signals in one field is smaller than the predetermined number of signals to be recorded in one field, a signal other than the audio signal to be recorded subsequently to the audio signal until the predetermined number is recorded A code indicating a signal other than a signal, a control signal such as a synchronization signal, and the like are added and modulated by the modulation circuit 37. Then, it is amplified to a predetermined level by the recording amplifier 26, and the magnetic tape 32 by the rotary head 31 for voice.
Recorded above. The switching circuit 30 switches between recording and reproduction. Further, the timing generation circuit 21 is a circuit which generates a timing signal for controlling the whole by a head switching signal determined by the clock generated by the oscillation circuit 22 and the scanner phase.

At the time of reproduction, the switching circuit 30 is switched to the reproduction side, the signal reproduced by the rotary head 31 for audio is amplified to a predetermined level by the reproduction amplifier 29, and waveform equalization is performed by the waveform equalization circuit 39. The waveform-equalized signal is demodulated by the demodulation circuit 38 and converted into a digital signal. The demodulated digital signal is detected by the synchronization detection circuit 28 and converted into a parallel signal by the serial-parallel conversion circuit 27. The detected sync signal is used as a reference for data reproduction. The data converted into the parallel signal is judged by the signal judgment circuit 44 as a voice signal or a signal other than the voice signal, only the voice signal is stored in the RAM 15, and the data rearrangement and the error correction by the error correction circuit 20 are performed. .
Then, it is input to the D / A converter 12 through the bus line 14 and sequentially converted into an analog signal, and the sample hold circuit 11 resamples each channel. The analog signal resampled in each channel is output from the output terminal 8 through the filter 10 and the amplifier circuit 9.

At the time of recording, the video signal is input from the input terminal 40 and converted into a predetermined signal by the video circuit 42.
Recorded on tape 32 by 43. During reproduction, the signal reproduced by the video rotary head 43 is converted into a predetermined signal by the video circuit 42 and output from the output terminal 41.

With such a configuration, by controlling the number of audio signal samples output in one field by the address difference signal, even if either one of the predetermined sampling period and the field period or both of them are different, There is an effect that it can be recorded just enough for the number of input samples.

The invention will now be described in more detail by means of an example of recording a signal conforming to the format of a rotary head digital audio tape recorder (R-DAT).

First, the signal format is shown in FIGS. FIG. 2 is a block diagram and FIG. 3 is a frame diagram.

One block is composed of 36 bytes, of which 4 bytes are 1 byte for each of the sync signal, the ID code, the block address and the parity. The remaining 32 bytes are PCM data and parity. Further, these blocks are composed of a pair of even-order blocks and next odd-order blocks, and the parity composed of the data in these two blocks is included in the odd-order blocks.

Next, one frame consists of 128 blocks, of which 24
The block is a parity block. The period of one frame is 15 msec.

For the above formats, the field cycle of VTR (525/60 system) is about 16.683 msec,
It is long unlike 15msec. Therefore, in one field, R-
About 142.364 blocks will be included in the DAT block. Therefore, the number of signal samples recorded on the tape is always 143 blocks, but the number of audio signal samples therein is 142 or 143 blocks depending on the difference between the write address and the read address. That is, if the address difference is larger than the predetermined value, all 143 blocks are set as the voice signal sample value, and if the address difference is smaller than the predetermined value, the voice signal sample value is recorded in 142 blocks, and then the voice signal sample value is recorded. The read address circuit and the control signal circuit are controlled so that one block of the sample value other than the signal is recorded. By recording as described above, the asynchrony of the sampling period and the field period can be absorbed.

Further, in this embodiment, in order to avoid both ends of the block, 14
The 3 blocks are compressed and recorded in the range of 170 ° in the 180 ° area, and the preamble and postamble signals are recorded at 5 ° intervals at both ends.

Here, since the block address value is not necessarily continuous in the field, it is unclear from which block to which block is recorded in the field. Therefore, in the block configuration of FIG. 2, by adding an address indicating the order of blocks in the field to the ID code area, there is an advantage that the block address can be easily controlled by using it together with the block address.

In still another embodiment, the number of blocks in the one field is fixed at 143 blocks, for example, and in the case of a field containing 142 blocks, one of them is a block other than the audio signal. Here, there is a method in which the block other than the voice is set as the first block or the last block in 143 blocks, for example.

There is also a method of inserting a control signal as a signal to be inserted in a block other than the voice.

A code indicating whether the sample value of the block is a voice signal or a sample value other than the voice signal is recorded in the most significant bit of the block address in the block configuration of FIG. For example, “0” is recorded if the sample value in the block is a voice signal, and “1” is recorded if the sample value is a signal other than the voice signal. At the time of reproduction, the signal determination circuit 44
At, it is determined whether or not the data in the block is recorded in the RAM.

A specific circuit configuration of the above embodiment will be described with reference to FIG. The figure shows the circuit configuration of the write / read address-related portion of the RAM during recording. The write address circuit 17 is composed of a counter 17-1.

The read address circuit 19 includes a counter 19-1 that divides the master clock by 8, a counter 19-2 that divides the output by 8 by 32, and a counter 19 that further divides the output by 32.
-3. Latch 33-1 is a write address circuit
The output of 17 and the output of the read address circuit 19 are latched by the transition point of the head switching signal 45 extracted by the exclusive OR gate 21-3. The latch output is input to the subtractor 33-2. 21-2 Addition The value obtained by subtracting the read address value from the write address value is input to the comparator 34-2 together with the output of the judgment value circuit 34-1, and whether it is larger or smaller than the output of the judgment value circuit 34-1. This determination output to be determined is input to the in-field sample number setting circuit 35. In the field sample number setting circuit 35, the decode value circuit 35- of the counter 36-2 of the field sample number counting circuit 36
The number of samples in the field is set by the selector 35-3 that selects 1 or 2. That is, when the output of the subtractor 33-2 is larger than the output of the decision value circuit 34-1, the decode value is set to 14
When the output of the subtractor 33-2 is smaller than the output of the judgment value circuit 34-1, the decode value is set to 142. In the field sample number counting circuit 36, the counter 36
When the output of -2 becomes the decode value selected by the selector 35-3, the counter of the read address circuit 19 is controlled to stop counting. Since the counter 36-2 counts the number of samples in the field, it is cleared at the transition point of the head switching signal 45. At this time, if the write address value is smaller than the read address value, an accurate difference cannot be extracted. Therefore, in addition to the number of operation bits, 1 bit is always input to the upper side of the write address input of the subtractor, and 1 bit is always input to the upper side of the read address input. An accurate difference can always be extracted by setting the output to the number of operation bits for such an input.

〔The invention's effect〕

According to the present invention, when the PCM audio signal is recorded together with the video signal by the rotary magnetic head type scanner, it is not necessary to establish a synchronous relationship between the rotation frequency of the head scanner and the sampling frequency of the PCM audio signal, so it is arbitrary. With the video signal of
It can be combined with PCM audio signal and recorded simultaneously or after-recorded mutually. Alternatively, only the audio signal can be recorded asynchronously with the number of revolutions of the head scanner.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, FIG. 2 and FIG.
FIG. 4 is a signal configuration diagram of the rotary head type digital audio tape recorder, and FIG. 4 is a specific circuit configuration diagram of the address control unit during recording. 15 ... RAM, 17 ... write address circuit, 19 ... read address circuit, 21 ... timing generation circuit, 33 ... address difference extraction circuit, 34 ... difference determination circuit, 35 ... field sample number setting circuit , 36 …… Field sample number counting circuit, 44 …… Signal judgment circuit, 45 …… Head switching signal.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location H04N 5/928 H04N 5/92 E (72) Inventor Yasushi Yumi 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Home Appliance Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-58-105415 (JP, A) JP-A-56-21446 (JP, A)

Claims (4)

[Claims] 1. A digital signal recording apparatus, wherein a coded digital audio signal is multiplex-recorded on a recording medium together with a video signal, in a unit corresponding to a period of a signal synchronized with the video signal. A circuit for detecting the difference between the input amount of the digital audio signal to the memory and the output amount from the memory for recording the digital audio signal, and the detection output of the detection circuit for determining the amount of the digital audio signal for recording. A digital signal recording apparatus comprising: a control circuit; and, in the memory, means for interleaving the digital audio signal input to the memory to read it from the memory. 2. A digital signal recording apparatus according to claim 1, wherein the circuit for controlling the amount of the digital audio signal for recording has a large amount of the digital audio signal to be recorded within a predetermined time. And a case where the amount of the digital audio signal to be recorded within the predetermined time is small is provided, and the above two cases are selectively controlled. If the amount of the digital audio signal to be recorded is small, within the predetermined time. A digital signal recording apparatus characterized in that data other than digital audio signals is added so that the data amount becomes the same as that when a large amount of digital audio signals is recorded. 3. The digital signal recording apparatus according to claim 2, wherein when the amount of digital audio signals to be recorded within the predetermined time is small, it is identified that data other than the digital audio signals has been added. A digital signal recording device characterized by recording a signal. 4. A digital signal recording apparatus according to claim 1, wherein a difference between an input amount of the digital audio signal to the memory and an output amount from the memory for recording the digital audio signal is detected. The digital signal recording circuit is characterized by detecting a difference between an input amount of the digital audio signal to the memory within a predetermined time and an output amount from the memory for recording the digital audio signal. apparatus.