JPH079630B2 - Information processing equipment - Google Patents

Description

TECHNICAL FIELD The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus to which an option board equipped with an optional memory is connected.

2. Description of the Related Art Conventionally, in a device such as a printer or an information processing device to which an option board having an optional memory is connected, it is necessary to recognize information about the memory on the main board side. This information was the following two items.

Is the option board connected? How big is the memory? The above information and the above information was transmitted to the CPU on the main board side via a signal line between the main board and the option board.

The conventional information processing apparatus will be described with reference to FIG. FIG. 2 is a block diagram showing the configuration of a conventional information processing apparatus. In the figure, the conventional information processing apparatus includes a main board 1, an option board 2, and a display mechanism 4.

The main board 1 is a CPU ((Central Processing Unit) 8
The display means 7 and the initialization program 10 are included.

The option board 2 includes a memory unit 3 including a plurality of memory ICs and a switch (SW) 9.

The main board 1 and the option board 2 are connected by a connector (not shown). That is,
The CPU 8 is connected to the memory unit 3 via BUS 11.

In such a configuration, when connecting the option board 2 to the main board 1, an operator or the like uses a switch 9 such as a DIP type switch.
, And the above information was set. Then, on the main board 1 side, the CPU 8 recognizes the set value of the switch 9,
The initialization program 10 was activated to initialize each memory IC in the memory unit 3. In addition, a display mechanism (for example, LC
D, 7-segment LED) 4 was displayed on the screen to convey a message to the operator.

However, in recent years, downsizing of the device has been required, and in particular, the option board is required to have a more compact structure. For that purpose, the number of parts to be mounted on the option board 2 must be minimized. In the conventional information processing apparatus, the above-mentioned information is recognized by the firmware as a signal line guided from the option board 2 to the main board 1 via a connector in a hardware-dependent type.

Therefore, in the conventional information processing apparatus, the option board has drawbacks such as complication of parts such as switches set at the time of shipment to generate information such as memory capacity, wiring patterns associated therewith and an increase in the number of pins of the connector. there were.

OBJECT OF THE INVENTION It is an object of the present invention to provide an information processing device capable of making an option board compact.

Configuration of the invention, an information processing apparatus of the present invention is an information processing apparatus composed of a main board and an option board, a memory having a plurality of addresses provided on the option board, and provided on the main board, The memory has access means for accessing a plurality of addresses at predetermined addresses, and determination means provided on the main board for determining an access result by the access means. If all accesses to the address are in error, it is determined that the memory is not mounted, and if access is not possible partially, it is determined that the memory is faulty.

Embodiments Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of an information processing apparatus according to the present invention, and the same portions as those in FIG. 2 are designated by the same reference numerals.

In the figure, an information processing apparatus according to one embodiment of the present invention includes a main board 1, an option board 2, and a display mechanism 4.

The main board 1 includes a CPU 8, a display means 7, an initialization program 10, a memory diagnostic means 5, and an analysis means 6.

The option board 2 has a memory unit 3 composed of a plurality of memory ICs. The memory section 3 on the option board 2 is connected to the CPU 8 on the main board 1 via the BUS 11 and can be accessed by the memory diagnostic means 5. The diagnosis result of the memory diagnosis unit 5 is analyzed by the analysis unit 6, and the analysis result is stored.

Next, the diagnostic operation of the present invention will be described with reference to FIGS. 3, 4, and 5. FIG. 3 is a conceptual diagram showing a diagnostic location in the memory space of the memory unit 3. In the figure, X
Diagnosis is performed for each [MByte], and each time diagnosis is performed for a memory space of 256 [Byte].

Therefore, the first diagnosis is performed only on 256 [Byte] (hatched portion) of the first X [MByte]. Similarly, the second time is the next X [MByte] (that is, 2X [MByte]
256 [Byte] of the second) and the next X [MBy]
te] (that is, 3X [MByte] th) only 256 [Byte] will be performed. Then, when all the diagnosis is completed, the initialization program
Initialization is performed by 10.

If the diagnosis is performed as described above, the state of the memory section 3 on the option board 2 can be recognized on the main board 1 side based on the result. In other words, instead of making a diagnosis by accessing the entire memory space of the memory unit 3, it is possible to save time by making a diagnosis by accessing every suitable address.

In the present embodiment, 256 [Byte] is accessed by one diagnosis, but the object can be achieved even with a smaller amount of access. However, if it is extremely small (for example, 1
[Byte]) cannot be said to be a good idea because correct results cannot be obtained if there is an accident in that part.

The diagnosis is performed by the procedure shown in FIG. FIG. 4 is a flow chart showing the procedure of diagnosis in the information processing apparatus of the present invention. In the figure, the case where the diagnosis is performed N times is shown. This flowchart is stored in the memory diagnostic means 5 as firmware.

First, the first diagnosis is performed (step 41).
As a result, if it cannot be accessed, ERROR is diagnosed (steps 42 → 48). In this case, if all accesses to the memory space to be accessed are ERROR, it is judged by the analysis means 6 that the memory is not mounted. If the access cannot be made partially, it is determined that there is a memory failure, ERROR is displayed, and then the operation ends (steps 48 → 50 → 51).

If the result of the first diagnosis is not ERROR, the second diagnosis is performed (steps 42 → 43). As a result, if access is not possible, ERROR is diagnosed (steps 44 → 48). In this case, if all accesses to the memory space to be accessed are ERROR, the first diagnosis is not ERROR, so
It is determined to be 1 [MByte], the memory capacity is stored as 1 [MByte], and the operation ends (steps 48 → 49 → 47). On the other hand, if the second diagnosis is not ERROR, then the third and fourth
It will be diagnosed as the second time. Similarly, the Nth time is also performed by steps 45 and 46.

Further, an example of the diagnostic operation will be described with reference to FIG.
In this example, if the memory unit 3 mounted on the option board 2 is 1 [MByte], 2 [MByte], 4 [MB
yte], there are a total of 3 versions. Then, the algorithm for each diagnosis is a read / write (R / W) check of the same data.

In the figure, first, diagnostic data is set (step 61), and diagnosis is performed on a 256 [Byte] space from the beginning of the memory space (step 62). As a result, in the case of ERROR, the content of the EROR is analyzed (steps 63 → 70),
When all byte data are ERROR, it is determined that there is no memory in that space (steps 70 → 71). Then, the operation ends after storing that the option board is not connected (step 71 → 69). Partially erro
When R is detected, it is determined that the memory is abnormal (fault), ERROR is displayed, and the operation ends (steps 70 → 76 → 79).

If there is no ERROR in the space of 256 [Byte] from the beginning, the following 1
Diagnosis is performed on a space of 256 [Byte] from the beginning of [MByte] (2 [MByte]) (step 63 → 64). As a result, in the case of ERROR, the contents of ERROR are analyzed (steps 65 → 72), and when all byte data are ERROR, it is determined that there is no memory in that space (step 65).
72 → 73).

Then, the operation ends after memorizing that the memory of the capacity of 1 [MByte] is connected on the option board (step 73 → 69). When ERROR is partially detected, it is determined that the memory is abnormal, and after displaying ERROR, the operation ends (steps 72 → 76 → 69).

If there is no ERROR in the space of 256 [Byte] from the beginning of 2 [MByte], this time 256 [Byte] from the beginning of 4 [MByte]
The diagnosis is performed on the space (steps 65 → 66). As a result, in the case of ERROR, the content of the ERROR is analyzed (step 67 → 74), and if all the byte data are ERROR, it is determined that there is no memory in that space (step 67).
74 → 75). Then, on the option board, 2 [MByt
After memorizing that the memory of the capacity e] is connected, the operation ends (steps 75 → 69). Partially ERROR
If is detected, it is determined that the memory is abnormal and the ER
The operation ends after displaying ROR (Steps 74 → 76 → 6
9). ERR in the space of 256 [Byte] from the beginning of the 4th [MByte]
If there is no OR, the operation ends after memorizing that the memory of the capacity of 4 [MByte] is connected on the option board (step 67 → 68 → 69).

In other words, in this example, the type of memory capacity is 1 [MByt
Since there are only three types, e], 2 [MByte], and 4 [MByte], it is optional if the first [MByte], 2 [MByte], and 4 [MByte] first 256 [Byte] are diagnosed. It is possible to judge the memory capacity on the board.
As a result, the switch on the option board, which was conventionally required, can be eliminated, and the device can be made compact.

EFFECTS OF THE INVENTION As described above, the present invention has an effect that the option board can be downsized by searching and recognizing information on the memory on the option board by the firmware on the main board side.

Further, there is an effect that the determination means can determine not only the presence or absence of the memory, but also the failure of the memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an information processing apparatus according to an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a conventional information processing apparatus, and FIG. 3 is a diagnostic location in a memory space of a memory section. FIG. 4 is a conceptual diagram, FIG. 4 is a flowchart showing a procedure of diagnosis in the information processing apparatus of the present invention, and FIG. 5 is a flowchart showing an example of a diagnostic operation. Description of main part symbols 1 ... Main board 2 ... Option board 3 ... Memory section 5 ... Memory diagnostic means 6 ... Analysis means 8 ... CPU

Claims (1)

[Claims] 1. An information processing apparatus comprising a main board and an option board, comprising: a memory provided on the option board and having a plurality of addresses; and a memory provided on the main board for each predetermined address. In addition to having access means for accessing over a plurality of addresses, and determination means provided on the main board for determining an access result by the access means, the determination means is capable of making an error in access to a plurality of addresses for each of the predetermined addresses. If so, it is determined that the memory is not mounted, and if it is partially inaccessible, it is determined that the memory has a failure.