JPH0795575B2 - Semiconductor rectifier - Google Patents
Semiconductor rectifierInfo
- Publication number
- JPH0795575B2 JPH0795575B2 JP62085836A JP8583687A JPH0795575B2 JP H0795575 B2 JPH0795575 B2 JP H0795575B2 JP 62085836 A JP62085836 A JP 62085836A JP 8583687 A JP8583687 A JP 8583687A JP H0795575 B2 JPH0795575 B2 JP H0795575B2
- Authority
- JP
- Japan
- Prior art keywords
- copper
- kovar
- heat dissipation
- semiconductor
- invar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） この発明は、半導体整流素子に関し、該半導体整流素子
は特に車両の交流発電機に内蔵される整流装置に用いら
れる。Description: [Object of the Invention] (Industrial field of application) The present invention relates to a semiconductor rectifying element, and the semiconductor rectifying element is particularly used for a rectifying device incorporated in an alternator of a vehicle.
（従来技術） 従来、交流発電機の固定子三相巻線の起電力をシリコン
ダイオードの三相ブリッジ接続で整流する場合などに用
いられてきた半導体整流素子の一例は、第４図に示す構
造のものである。同図において、１はシリコンチップ、
２は銅板でわん状に形成された放熱容器で、シリコンチ
ップ１はその一方の主面（図の下面）で、はんだ層3aに
よって放熱容器２の凹底にマウントされ、シリコンチッ
プ１の他方の主面（図の上面）は、はんだ層3bによって
リード線４に接続され、電極導出が行われている。ま
た、上記シリコンチップ１を保護するために、わん状の
放熱容器２の凹部内にはシリコーン樹脂のエンキャップ
材５が充填され、シリコンチップ１を被覆するとともに
これと放熱容器２とリード線４とを一体に封止する外囲
器を構成している。(Prior Art) An example of a semiconductor rectifying element that has been conventionally used for rectifying the electromotive force of a stator three-phase winding of an AC generator by a three-phase bridge connection of silicon diodes is shown in FIG. belongs to. In the figure, 1 is a silicon chip,
2 is a heat dissipation container formed of a copper plate in a bowl shape, and the silicon chip 1 is one main surface (lower surface in the figure) of which is mounted on the concave bottom of the heat dissipation container 2 by the solder layer 3a. The main surface (upper surface in the figure) is connected to the lead wire 4 by the solder layer 3b and the electrodes are led out. In order to protect the silicon chip 1, the encapsulation material 5 made of silicone resin is filled in the recess of the bowl-shaped heat dissipation container 2 to cover the silicon chip 1 and the heat dissipation container 2 and the lead wire 4. And an envelope that integrally seals and.
上記半導体整流素子の構造において、従来の放熱容器２
には熱伝導性のよい銅が使用される。しかし、銅の線膨
脹率は16.7×10-6/℃でシリコンの線膨脹率2.5×10-6/
℃に比して約６倍と大きいため、従来の放熱容器２には
んだ接合したチップ１には、大きな熱応力が働き破損の
原因になる。特に、近年自動車に電子機器が多く装備さ
れるようになり、整流素子の容量増大が要請されてい
る。これに伴いシリコンチップも大型化の傾向にあり、
熱衝撃対策としてシリコンチップ１と放熱容器２との間
にタングステンやモリブデン等の緩衝板を挿入すること
が一般に行われているが、これらの緩衝板は非常に高価
であり、製品価格の低減化に障害になる。In the structure of the semiconductor rectifying device, the conventional heat dissipation container 2
For this, copper with good thermal conductivity is used. However, the coefficient of linear expansion of copper is 16.7 × 10 -6 / ℃ and the coefficient of linear expansion of silicon is 2.5 × 10 -6 /
Since it is about 6 times as large as the temperature of ° C, a large thermal stress acts on the chip 1 solder-bonded to the conventional heat radiating container 2 and causes damage. Particularly, in recent years, many electronic devices have been installed in automobiles, and it has been required to increase the capacity of the rectifying element. Along with this, the size of silicon chips is also increasing,
As a measure against thermal shock, it is generally practiced to insert a buffer plate made of tungsten, molybdenum or the like between the silicon chip 1 and the heat dissipation container 2, but these buffer plates are very expensive, and the product price is reduced. Becomes an obstacle to.
また従来、シリコンの線膨脹係数に近い銅とインバーと
銅とのクラッド板を使用したものもあるが、その特性は
まだ十分ではない。すなわち、整流素子について、50℃
と170℃との熱繰り返しサイクルの破壊試験をすると、
所望値の10％破壊のサイクル数（F10）＝3000サイクル,
50％破壊のサイクル数（F50）＝5000サイクルに対してF
10＝4500サイクル,F50＝5800サイクル程度であって、上
記所望値を満足はするが余裕が少ない。Further, conventionally, there is also one using a clad plate of copper, Invar, and copper having a coefficient of linear expansion close to that of silicon, but the characteristics are not yet sufficient. That is, about the rectifying element,
When the destructive test of the thermal repetition cycle of
Number of cycles of 10% destruction of desired value (F 10 ) = 3000 cycles,
Number of cycles for 50% destruction (F 50 ) = F for 5000 cycles
10 = 4500 cycles, be on the order of F 50 = 5800 cycles, satisfies the desired value is less room for.
（発明が解決しようとする問題点） この発明は、従来の問題点に鑑み、熱伝導性と、熱衝撃
特性とが両立するという改良された材質の放熱容器をも
つ半導体清流素子を提供することである。(Problems to be Solved by the Invention) In view of the conventional problems, the present invention provides a semiconductor clearing device having a heat dissipation container made of an improved material in which both thermal conductivity and thermal shock characteristics are compatible. Is.
［発明の構成］ （問題点を解決するための手段） 第一発明にかかる半導体清流素子は、整流機能を有する
半導体チップを、その一主面の電極でわん状の金属製放
熱容器の内底にはんだ接合させ、一方その他主面の電極
でリード線の一端にはんだ接合させるとともに、該放熱
容器内を樹脂封止したものであって、該放熱容器が銅と
コバールと銅の３層のクラッド材から成り、特に該３層
の層厚の比率が１対２対１であることが好ましく、そし
てその表層の銅層に半導体チップ接合（マウント）した
ことを特徴とする。[Structure of the Invention] (Means for Solving the Problems) A semiconductor clearing element according to the first invention is a semiconductor chip having a rectifying function, in which an electrode on one main surface thereof has an inner bottom of a bowl-shaped metal heat dissipation container. Soldering to one end of a lead wire with an electrode on the other main surface and resin-sealing inside the heat dissipation container, the heat dissipation container being a three-layer clad of copper, kovar, and copper. It is preferable that the ratio of the layer thicknesses of the three layers is 1: 2: 1, and that the semiconductor chip is bonded (mounted) to the surface copper layer.
また第二発明にかかる半導体整流素子は、該放熱容器が
銅とコバール、銅とインバー、又は銅とNSDの２層クラ
ッド材から成り、該クラッド材のコバール、インバー又
はNSDの側が半導体チップのマウントされる内底になる
ようにしたことを特徴とする。Also, in the semiconductor rectifying device according to the second invention, the heat dissipation container is made of a two-layer clad material of copper and kovar, copper and invar, or copper and NSD, and the semiconductor chip is mounted on the kovar, invar or NSD side of the clad material. It is characterized in that it is designed to be the inner bottom.
なお、コバールはFe−29％Ni−17％Co合金、インバーは
Fe−36％Ni合金、またはNSDはFe−42％Ni合金である。
さらに３層又は２層クラッド材の好ましい比率における
許容度は±10％である。In addition, Kovar is a Fe-29% Ni-17% Co alloy, Invar is
Fe-36% Ni alloy, or NSD is Fe-42% Ni alloy.
Further, the tolerance in the preferable ratio of the three-layer or two-layer clad material is ± 10%.
（作用） この発明（特に銅−コバール−銅の層厚を特に１対２対
１の比率にしたもの）の３層クラッド材は、第１表に示
すように、従来例の銅に比較して０〜200℃までの線膨
脹係数と熱伝導係数がバランスして優れている。(Operation) As shown in Table 1, the three-layer clad material of the present invention (in particular, the layer thickness of copper-Kovar-copper in a ratio of 1: 2 to 1) is compared with the conventional copper. It has an excellent balance of linear expansion coefficient and thermal conductivity coefficient from 0 to 200 ℃.
また、この発明におけるクラッド材を構成するコバール
と従来クラッド材を構成するインバーの線膨脹係数は、
第２図にみるように、前記熱繰り返しサイクルの破壊試
験に採用されている温度範囲（50℃と170℃）を含む約2
90℃以下の範囲においては、コバールが5.7×10-6/℃
で、インバーの2.6×10-6/℃に比較してかなり大きいけ
れども、約300℃以上の線膨脹係数についてみると、コ
バールの方がインバーよりも小さいことに着目して、本
発明がなされたものである。すなわち、本発明の整流素
子の優れた熱衝撃特性は、単に０℃〜200℃までの線膨
脹係数と熱伝導係数との値がバランスして優れているば
かりでなく、主にはんだ接合の際の上記30℃以上におけ
るコバールの線膨脹特性によるものであることを意味し
ている。従って、コバールとの３層クラッド材の層厚比
率は上記比率に限定されない。 Further, the linear expansion coefficient of Kovar constituting the clad material in the present invention and Invar constituting the conventional clad material are
As shown in Fig. 2, about 2 including the temperature range (50 ° C and 170 ° C) used in the destructive test of the thermal cycle.
Kovar 5.7 × 10 -6 / ° C in the range of 90 ° C or less
In view of the linear expansion coefficient of about 300 ° C. or higher, the present invention was made by focusing on the fact that Kovar is smaller than Invar, although it is considerably larger than Invar's 2.6 × 10 −6 / ° C. It is a thing. That is, the excellent thermal shock characteristics of the rectifying device of the present invention are not only excellent in that the values of the linear expansion coefficient and the thermal conductivity coefficient from 0 ° C. to 200 ° C. are simply balanced, but also mainly in soldering. It means that it is due to the linear expansion characteristic of Kovar above 30 ° C. Therefore, the layer thickness ratio of the three-layer clad material to Kovar is not limited to the above ratio.
また、第二発明における銅とコバール、インバー又はNS
Dとの２層クラッド材は、わん状放熱容器のチップの接
合される側にコバール、インバー、NSDが置かれた場
合、実験的に第一発明と同様にチップの受ける熱衝撃が
緩和されることが確認された。そしてその特性はコバー
ルなどの層厚によって大きく変化しないので、主として
経済的な意味からコバールなどと銅の層厚の比率は１対
９であることが好ましい。Also, copper and kovar, invar or NS in the second invention
The two-layer clad material with D, when Kovar, Invar, and NSD are placed on the side where the chips of the bowl-shaped heat dissipation container are joined, experimentally reduces the thermal shock received by the chips as in the first invention. It was confirmed. Since the characteristics do not change significantly depending on the layer thickness of Kovar or the like, it is preferable that the ratio of the layer thickness of Kovar or the like to copper is 1 to 9 mainly from an economical point of view.
（実施例） 次に本発明の実施例を図面を参照して説明する。実施例
の図面において第４図におけると同じ符号を付した部分
は従来例と変化ない部分である。(Example) Next, the Example of this invention is described with reference to drawings. In the drawings of the embodiment, the parts denoted by the same reference numerals as those in FIG. 4 are the same as those in the conventional example.
第一実施例は、第１図に示すように、放熱容器６が、銅
6aとコバール6bと銅6cの３層クラッド材から成ってい
る。ここで銅とコバールの厚さの比率は重要である。当
然のことながら、コバールの占める割合が多いと熱応力
は小になるが、放熱は悪くなり、逆に銅の占める割合が
多いと放熱はよいが、熱応力は大となる。In the first embodiment, as shown in FIG. 1, the heat dissipation container 6 is made of copper.
It consists of a 3-layer clad material consisting of 6a, Kovar 6b and copper 6c. Here, the thickness ratio of copper and kovar is important. As a matter of course, when the proportion of Kovar is large, the thermal stress is small, but the heat radiation is poor, and conversely, when the proportion of copper is large, the heat radiation is good, but the thermal stress is large.
従って、銅−コバール−銅の厚さの比率は製品の要求仕
様によって決めればよい。この実施例では、評価結果の
最も好かった1:2:1の比率のクラッド材を採用した。Therefore, the copper-kovar-copper thickness ratio may be determined according to the required specifications of the product. In this example, a clad material having a ratio of 1: 2: 1, which is the most favorable evaluation result, was used.
第二実施例は、第３図に示すように、放熱容器７がコバ
ール7aと銅7bとの２層クラッド材から成っている。ここ
で銅とコバールの厚さの比率は９対１にした。当然のこ
とながら、コバールの占める割合が多いと熱応力は小に
なるが、放熱は悪くなり、逆に銅の占める割合が多いと
放熱はよいが、熱応力が大となる。従って、層厚の比率
は製品の要求仕様によって決めればよい。またインバー
タ及びNSDについての２層クラッド材についても製作し
た。In the second embodiment, as shown in FIG. 3, the heat dissipation container 7 is made of a two-layer clad material of Kovar 7a and copper 7b. Here, the thickness ratio of copper to Kovar was set to 9: 1. As a matter of course, when the proportion of Kovar is large, the thermal stress is small, but the heat radiation is poor. Conversely, when the proportion of copper is large, the heat radiation is good, but the thermal stress is large. Therefore, the layer thickness ratio may be determined according to the required specifications of the product. We also made a two-layer clad material for the inverter and NSD.
次に第一実施例と比較例（銅−インバー−銅の層厚比率
１対１対１）の３層クラッド材及び第二実施例のコバー
ル、インバー及びNSDの２層クラッド材について次の評
価を行った。Next, the following evaluation was made on the three-layer clad material of the first example and the comparative example (copper-invar-copper layer thickness ratio 1: 1: 1) and the two-layer clad material of Kovar, Invar and NSD of the second example. I went.
熱疲労試験 第５図に示す装置で、整流素子51を銅の放熱板52に半田
付けし、リード端子53と放熱板52の間に順方向に35Aの
電流を流す。放熱板の裏側の中央部に熱電対T.C.を取り
付けて温度を検出し、170℃で電流をオフし、50℃で電
流をオンさせるサイクルを繰り返す試験を、十分な検出
精度をもつ数の試料について行う。その結果、銅−イン
バー−銅を用いた従来３層クラッド材は、F10＝4500、F
505800で規格値のF10＝3000、F50＝5000を満足している
が余裕が少ないのに対して、第一実施例の３層クラッド
材はF10＝5900、F50＝7800でロットのバラツキや製造マ
ージンを考慮に入れても余裕をもって規格値を超えるこ
とができた。また第二実施例のコバール、インバー及び
NSD2層クラッド材はいずれもF10＝5500〜6200,F50＝750
0〜8200のレベルであった。Thermal Fatigue Test In the device shown in FIG. 5, the rectifying element 51 is soldered to a copper heat sink 52, and a current of 35 A is passed between the lead terminal 53 and the heat sink 52 in the forward direction. A thermocouple TC is attached to the center of the backside of the heat sink to detect the temperature, the current is turned off at 170 ° C, and the cycle of turning on the current at 50 ° C is repeated. To do. As a result, the conventional three-layer clad material using copper-invar-copper is F 10 = 4500, F
At 50 5800, the standard values of F 10 = 3000 and F 50 = 5000 are satisfied, but the margin is small, whereas the three-layer clad material of the first embodiment is F 10 = 5900, F 50 = 7800 It was possible to exceed the standard value with a margin even when taking into consideration the variation of the above and the manufacturing margin. Also, Kovar, Invar and the second embodiment
All NSD 2-layer clad materials are F 10 = 5500-6200, F 50 = 750
The level was from 0 to 8200.
熱衝撃試験 製品の整流素子を−40℃の雰囲気に30分間放置し、次に
70℃の雰囲気に30分間放置するというサイクルの繰返し
で不良発生を調べた。第一実施例及び第二実施例の試料
とも規格の100サイクルを経過しているがまだ不良発生
がみられない。Thermal shock test Leave the rectifier of the product in an atmosphere of -40 ° C for 30 minutes, then
The occurrence of defects was examined by repeating a cycle of leaving it in an atmosphere of 70 ° C for 30 minutes. Although the samples of the first and second examples have passed the standard 100 cycles, no defects have been observed yet.
［発明の効果］ 本発明によれば、前記の熱衝撃試験の結果のとおり、従
来例のように放熱容器が銅の場合、シリコンチップが破
損し、素子が機能しなくなる割合は、約２％程度あった
が、本発明の放熱容器を使った場合のそれは、0.1％以
下となり、著しく改善できた。[Effects of the Invention] According to the present invention, as shown in the results of the thermal shock test, when the heat dissipation container is copper as in the conventional example, the silicon chip is damaged and the element does not function at a rate of about 2%. Although there was a certain degree, it was 0.1% or less when using the heat dissipation container of the present invention, which was a remarkable improvement.
第１図及び第３図は本発明の半導体整流素子の断面図、
第２図は本発明の作用を説明するためのグラフ、第４図
は従来の半導体整流素子の断面図、第５図は熱疲労試験
装置を示す斜視図である。 １……半導体チップ、2,6,7……放熱容器、3a,3b……は
んだ層、４……リード線、５……封止樹脂。1 and 3 are cross-sectional views of the semiconductor rectifying device of the present invention,
FIG. 2 is a graph for explaining the operation of the present invention, FIG. 4 is a sectional view of a conventional semiconductor rectifying device, and FIG. 5 is a perspective view showing a thermal fatigue test apparatus. 1 ... semiconductor chip, 2,6,7 ... heat dissipation container, 3a, 3b ... solder layer, 4 ... lead wire, 5 ... encapsulating resin.
Claims (4)
主面の電極でわん状の金属製放熱容器の内底にはんだ接
合させ、一方その他主面の電極でリード線の一端にはん
だ接合させるとともに、該放射熱容器内を樹脂封止した
半導体整流素子において、該放熱容器が銅とコバールと
銅の３層クラッド材から成ることを特徴とする半導体整
流素子。1. A semiconductor chip having a rectifying function is solder-bonded to an inner bottom of a bowl-shaped metal heat dissipation container with an electrode on one main surface thereof, and is solder-bonded to one end of a lead wire with an electrode on the other main surface. At the same time, in the semiconductor rectifying device in which the inside of the radiant heat container is resin-sealed, the radiating container is made of a three-layer clad material of copper, kovar, and copper.
１である特許請求の範囲第１項記載の半導体整流素子。2. The semiconductor rectifying device according to claim 1, wherein the ratio of the layer thicknesses of copper, kovar and copper is 1: 2: 1.
主面の電極でわん状の金属製放熱容器の内底にはんだ接
合させ、一方その他主面の電極でリード線の一端にはん
だ接合させるとともに、該放熱容器内を樹脂封止した半
導体整流素子において、該放熱容器が銅とコバール、銅
とインバー、又は銅とNSDとの２層クラッド材から成
り、該クラッド材のコバール、インバー又はNSDの側が
半導体チップの接合をする内底になるようにしたことを
特徴とする半導体整流素子。3. A semiconductor chip having a rectifying function is solder-bonded to the inner bottom of a bowl-shaped metal heat dissipation container with an electrode on one main surface, and is soldered to one end of a lead wire with an electrode on the other main surface. In addition, in the semiconductor rectifying device in which the inside of the heat dissipation container is resin-sealed, the heat dissipation container is made of a two-layer clad material of copper and Kovar, copper and Invar, or copper and NSD, and the Kovar, Invar or NSD of the clad material is used. The semiconductor rectifying device is characterized in that the side of is the inner bottom for joining the semiconductor chips.
の比率が９対１である特許請求の範囲第３項記載の半導
体整流素子。4. The semiconductor rectifying device according to claim 3, wherein the layer thickness ratio of copper to Kovar, Invar or NSD is 9: 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62085836A JPH0795575B2 (en) | 1987-04-09 | 1987-04-09 | Semiconductor rectifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62085836A JPH0795575B2 (en) | 1987-04-09 | 1987-04-09 | Semiconductor rectifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63252457A JPS63252457A (en) | 1988-10-19 |
| JPH0795575B2 true JPH0795575B2 (en) | 1995-10-11 |
Family
ID=13869942
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62085836A Expired - Lifetime JPH0795575B2 (en) | 1987-04-09 | 1987-04-09 | Semiconductor rectifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0795575B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07120736B2 (en) * | 1988-07-11 | 1995-12-20 | 株式会社東芝 | Semiconductor rectifier |
| JP2643396B2 (en) * | 1988-12-15 | 1997-08-20 | 日立電線株式会社 | Plate-shaped lead wire soldered to a ceramic capacitor |
| US5015803A (en) * | 1989-05-31 | 1991-05-14 | Olin Corporation | Thermal performance package for integrated circuit chip |
| KR19990028818A (en) * | 1995-07-14 | 1999-04-15 | 와인스타인 폴 | Metal ball grid electronic package |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50127566A (en) * | 1974-03-27 | 1975-10-07 | ||
| JPS59161855A (en) * | 1983-03-07 | 1984-09-12 | Hitachi Ltd | Semiconductor device |
-
1987
- 1987-04-09 JP JP62085836A patent/JPH0795575B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63252457A (en) | 1988-10-19 |
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