JPH0795310B2 - Cache memory - Google Patents

Description

The present invention relates to cache memories.

[Conventional technology]

"Cache Memories: ACM Computi"
ng Surveys, vol.14, no3, 1982, pp.473-530), in an information processing device with a memory hierarchy, main memory is divided into blocks of a certain size, and these blocks are By copying a part of the data to the cache memory that can be accessed at high speed, when the data requested by the processor exists in the cache memory,
By passing this to the processor at high speed, the access speed seen from the processor is improved. The size of this block (hereinafter referred to as block size) is generally taken as a power of two.

In the cache memory, a copy of data held by a block in the main memory (hereinafter referred to as main memory block) and an address tag indicating the position where this block exists in the main memory are recorded. The data memory in the cache memory is the part that records a copy of the data held in the main memory block, and the directory is the address
This is the part that records tags. A block corresponding to one address tag serves as a unit of mapping between the main memory and the cache memory.

When there is a data access request from the processor, the cache memory determines whether the requested data exists in the cache memory by checking whether the address output by the processor exists in the directory. As a result, when the requested data exists in the cache (hereinafter, hit), the data is passed from the cache data memory to the processor. If the requested data does not exist in the cache (below,
In the case of “miss hit”, the main memory block holding the data is accessed, and this data is passed to the processor and also copied to the data memory of the cache.
At this time, the value of the address output by the processor is recorded in the corresponding directory, and the mishit processing is completed.

Mapping methods between the main memory block and the cache memory block include a full associative method, a set associative method, and a direct map method. The full associative method is a method in which an arbitrary main memory block can be mapped to an arbitrary block of a cache memory and a block. The direct map method is a method in which a block of a cache memory to be mapped by an address where a main memory block exists is uniquely determined. In the set associative method, the cache memory blocks are divided into several groups,
This is a method in which a block can be mapped to an arbitrary block in the cache memory block having a groove number (set number) determined by an address where the main memory block exists.

Thus, in the cache memory of the full associative method or the set associative method, 1
There are multiple blocks of cache memory that can be mapped to one main memory block. So the cache
Inside the memory, the entry address is used to identify these blocks to access the data memory or directory.

[Problems to be Solved by the Invention]

The entire cache memory is an ultra-high integrated circuit (LSI chip)
However, there is a problem in that the contents of the address tag held in the cache memory directory and the contents of the data held in the data memory cannot be used in an external circuit. .

[Means for Solving the Problems]

In order to solve the above problems, the cache memory of the present invention is provided with an entry address output terminal for outputting an entry address, which is originally used only in the cache, to the outside of the LSI chip, and does not require a cache hit. For example, the address of the hit entry and the address of the replacement target entry in the case of a cache miss are output to the entry address output terminal.

[Action]

When the processor makes an access, if there is a cache hit, the address of the entry that hit, if it is a cache miss, the address of the replacement target entry,
Output to the entry address output pin. This allows
In the circuit added to the outside of the cache memory chip,
By using this entry address, the external directory and external data memory are accessed at the time of a cache hit, and the contents of the external directory and the external data memory are updated to the outside at the time of a cache miss. The same contents as the contents of the directory and the data memory, which are held only at, can be used in the external circuit.

〔Example〕

FIG. 1 shows the structure of a cache memory system using a cache memory according to the present invention, FIG. 2 shows the structure of a cache memory according to the present invention, and FIG. 3 shows the contents of addresses output by a processor during access. Indicates. This address is, in order from the least significant bit, in-block address 16, set address 14 and address tag 15
It is divided into The bits and number of these addresses depend on the block size and number of sets.

First, the operation of the cache memory 3 shown in FIG. 2 will be described. The cache memory operation when the processor outputs the access address and accesses the cache memory 3 is as follows.

First, the directory 7 is accessed by the set address 14 in the access address, and as many address tags as the number of entries are output from the directory 7. Comparison unit 9
Then, these plural address tags are compared with the address tag 15 in the access address. As a result, when there is a matching tag, it is a cache hit, and the data requested by the processor exists in the cache memory 3. Therefore, the data memory 2 is accessed by the set address 14 in the access address and the entry address 18 output from the comparator 9 to pass the data requested by the processor to the processor. The entry address 18 is output to the outside of the cache memory 3 through the entry address output terminal 4.

As a result of the comparison operation by the comparison unit 9, when there is no match among the plurality of address tags output from the directory 7 with the address tag 15 in the access address, it is a cache miss and the processor requests. Data is not present in the cache memory 3.
At this time, the address of the entry to be replaced is output from the comparison unit 9, the main memory block is accessed by the access address to obtain the data requested by the processor, and the data is passed to the processor.

In the directory 7 and the data memory, the address tag 15 in the access address is located at a position specified by the entry address 18 output from the comparison unit 9 and the set address 14 in the access address.
By writing the contents of the main memory block, the updating of the contents of the cache memory at the time of a cache miss is completed. When a cache miss occurs, the address of the entry to be replaced is output to the outside of the cache memory through the entry address output terminal 4.

The cache memory system shown in FIG. 1 is a system in which an external directory 7 and an external data memory 8 are added to the cache memory chip of FIG.
This operation is as follows.

At the time of a cache miss, the address of the entry among the addresses of the blocks in the cache to be replaced is output to the entry address output terminal 4,
The set number is indicated by the set address in the access address. Therefore, the external directory 7 and the external data memory 8 indicated by these addresses
The address when accessing the main memory and the obtained contents of the main memory block are stored in the block. By this operation, a copy inside the cache memory and a copy inside the data memory are held in the external directory 7 and the external data memory 8.

At the time of a cache hit, of the addresses of the blocks in the cache where the data requested by the processor exists,
The address of the entry is output to the entry address output terminal 4, and the set number is indicated by the set address 14 in the access address. Therefore, the external directory 7 and the external data memory 8 indicated by these addresses can be accessed, and the address and data of the access made by the processor can be used in the external circuit.

As described above, the gist of the present invention is to output the entry address of the block to be accessed from the cache memory realized as an ultra high-integrated circuit chip, thereby It is possible to retain the same data as the contents of the directory and the data memory in the external circuit.

Therefore, it is obvious that the present invention has various embodiments. For example, in the present embodiment, both the directory 7 and the data memory 8 are placed outside.
A system having only a directory or only a data memory is also included in the present invention.

Further, in the present embodiment, at the time of a cache hit, the external directory 7 and the external data are stored by using the entry address output from the entry address output terminal.
It is obvious that the present invention also includes a system that accesses the memory 8 but does not access the external directory 7 and the external data memory 8 at the time of a cache hit and uses the contents held in these.

Further, in the present embodiment, the processor and the cache memory are described as blocks of different blocks, but the present invention can be applied to the case where both are mounted on the same chip.

〔The invention's effect〕

According to the present invention, even in a cache memory chip in which the entire cache memory is realized as an ultra-high-integrated circuit (LSI chip), the content of the address tag and the data memory held in the directory of the cache memory are The content of the held data can be used in an external circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a cache memory system using a cache memory according to the present invention, FIG. 2 is a block diagram showing a configuration of a cache memory according to the present invention, and FIG. 3 is a processor. FIG. 5 is a diagram showing the contents of an address that is output at the time of access. 1 ... Directory, 2 ... Data memory, 3 ... Cache memory, 4 ... Entry address output terminal, 5 ... Processor, 6 ... Main memory, 7 ... External directory, 8 ... External data memory, 9 ... Comparison section, 10 ... Processor data bus, 11 ... Processor address bus, 12 ... Memory address bus, 13 ... Memory data bus, 14 ...
Set address, 15 ... Address tag, 16 ... Block address, 17 ... Access address, 18 ... Entry
address.

Claims (1)

[Claims] 1. A directory and data in a highly integrated circuit.
In a cache memory with a built-in memory, an entry address output terminal is provided, and when the processor accesses, the address of the entry that is a hit if the cache hits, the address of the replacement target entry if the cache miss, A cache memory characterized by outputting to an entry address output terminal.