JPH0795125A - Spread spectrum communication receiver - Google Patents

Abstract

PURPOSE:To minimize bit deterioration without increasing the sampling rate. CONSTITUTION:Digital matched filters 221-22n input respectively the output of an A/D converter 21 and sample the inputted signal and applies inverse spread processing to the signal. A multiplexer 24 outputs the output of the digital matched filter 22 based on the output of a counter circuit 26 sequentially. An absolute value arithmetic circuit 25 and a maximum absolute value search circuit 27 obtain a maximum value of the absolute value of the output of the multiplexer 24 and informs the counter circuit 26 of a number of the corresponding digital matched filter. The counter circuit 26 controls the digital matched filter 22 to select an optimum digital matched filter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a direct spread spectrum spread spectrum communication receiver. In particular, the present invention relates to a receiver that uses a digital matched filter to perform despreading at an optimum sample timing.

[0002]

2. Description of the Related Art Conventionally, in a spread spectrum communication receiver, when performing despreading using a digital matched filter, an analog signal output from a radio section is subjected to analog-digital conversion, and the converted digital signal is digitally converted. The data is input to the matched filter and processed at an appropriate sample timing, or the data is processed at a sample timing that is several times the data rate and despread data is output. Moreover, the sampling clock signals of the digital matched filter itself are not always synchronized.

[0003]

However, in such a conventional spread spectrum communication receiver, a digital matched filter is used especially when the transmission waveform and the reception waveform are filtered using the rate Nyx in the radio section. Since there is already a digital matched filter for the chip before, the sample must be one sample for one chip. However, there is a problem that bit deterioration occurs due to the sampling timing being deviated from the signal point.

Even with other filtering configurations, if the digital matched filter processes a received signal at an appropriate sampling timing, data bit deterioration occurs. In order to avoid this, there is a method of monitoring a data change point and generating a sample clock signal in synchronization with it. However, in this method, this function is meaningless unless the circuit is operated with a clock signal that is at least twice the data rate. As another method, there is a method of simply increasing the sampling rate (Japanese Patent Laid-Open Nos. 61-93746 and 63-737.
31), this method fails to collect data unless operated at a sampling rate which is several times the data rate.
That is, bit deterioration may occur. With the above method, when the data rate is increased, the sampling rate is more than doubled accordingly. However, if the sampling clock signal is increased beyond the processing capability of the hardware, it may be inconvenient in operation. There was a problem.

The present invention solves the above problems.
An object of the present invention is to provide a spread spectrum communication receiver capable of minimizing bit deterioration without increasing the sampling rate.

[0006]

The present invention comprises a receiving section (10) for receiving a spread spectrum signal and a spreading demodulation section (20) for despreading the output signal of the receiving section, and the spreading demodulation is provided. The section (20) is a spread spectrum communication receiver including a converter for converting the output of the receiving section from an analog signal to a digital signal, and a digital matched filter for despreading the output of the converter. N filters (n is an integer of 2 or more)
An absolute value of the output of the n digital matched filters, which is commonly connected to the outputs of the converters and includes means for performing despreading processing by sampling the outputs of the converters at mutually independent timings. And selecting means for selecting the output of the digital matched filter having the maximum absolute value.

According to the present invention, the selection means is the n
A multiplexer (24) that sequentially outputs the outputs of the digital matched filters as serial signals, and an absolute value calculation circuit (2) that calculates the absolute value of the output of the multiplexer.
5) and a maximum absolute value search circuit (2) for detecting the maximum value of the n absolute values output by this absolute value operation circuit and searching for the digital matched filter that has output this maximum value.
7) and a counter which controls the multiplexer to scan and change the output order, and fixes the output of the digital matched filter searched by the maximum absolute value search circuit to output the output as despread data. Circuit (26).

Further, according to the present invention, the means for generating the independent timing may include independent asynchronous clocks respectively provided so as to be supplied to the respective digital matched filters.

[0009]

The n (n is a positive integer) digital matched filters for inputting the outputs of the converters are arranged in parallel, and the outputs of the converters are sampled at different independent timings to perform despreading processing. The absolute values of the outputs of the n digital matched filters are calculated, and the digital matched filter having the maximum absolute value is selected. Since sampling is performed at each independent timing, the phase is random. It is not necessary to increase the sampling rate because the one with the largest absolute value is searched for by comparison. As a result, bit deterioration can be minimized without increasing the sampling rate.

[0010]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a spread spectrum communication receiver according to an embodiment of the present invention. FIG. 2 is a block diagram of a spread demodulation unit of the spread spectrum communication receiver of the present invention. FIG. 3 is a block diagram of the digital matched filter of the spread spectrum communication receiver. 1 to 3, the spread spectrum communication receiver is
The spread demodulation unit 20 includes a reception unit 10 that receives a spread spectrum signal and a spread demodulation unit 20 that despreads the output signal of the reception unit 10. The spread demodulation unit 20 converts the output of the reception unit 10 from an analog signal a to a digital signal b. An analog-digital converter 21 as a converter for converting and a digital matched filter for despreading the output of the analog-digital converter 21 are included.

Here, as a feature of the present invention, the number of the digital matched filters is n (n is an integer of 2 or more).
, And the commonly connected to the output of the analog-to-digital converter 21, each containing a means for processing the sampled despread with independent timing the output of the analog digital converter 21, n pieces of digital matched filters 22 ₁ It is characterized by comprising selection means for obtaining the absolute value of the output of .about.22 _n and selecting the output of the digital matched filter having the maximum absolute value.

The selecting means includes a multiplexer 24 for sequentially outputting the outputs of the _n digital matched filters 22 _{1 to} 22 _n as serial signals, and an absolute value calculation circuit 25 for calculating an absolute value of the output of the multiplexer 24. ,
The maximum absolute value search circuit 27 that detects the maximum value of the n absolute values output from the absolute value calculation circuit 25 and searches the digital matched filter 22 that has output this maximum value, and the multiplexer 24 is controlled to output the maximum absolute value search circuit 27. And a counter circuit 26 which fixes the output of the digital matched filter 22 searched by the maximum absolute value search circuit 27 and outputs the output as despread data d.

Further, the means for generating the independent timings are the digital matched filters 22 _{1 to} 22 _n.
Independent asynchronous clocks 23 ₁ to 23 _n , which are individually provided so as to be respectively supplied to

Further, the digital matched filter 22 ₁
Through 22 _n is an operation clock signal cl ₁ -CL spread code generator _{32 n} by generating a spread code at independent timing of outputting of the clock 23 ₁ ~ 23 _n, multiplying the diffusion code and the digital signal b And a mixer 31.

The operation of the spread spectrum communication receiver having such a configuration will be described.

FIG. 4 is a diagram showing an autocorrelation function of a spectrum spread signal of the spread spectrum communication receiver of the present invention. In FIG. 4, the autocorrelation function represents, as a function of the amount of time difference, the degree to which the original waveform is similar to that obtained by temporally shifting the waveform of the spread code (M sequence) (correlation value). It is a thing. The M-sequence autocorrelation function has a sharp peak for each cycle as shown in FIG.
Elsewhere it has a very small negative constant.

1 to 3, the receiving section 10 receives a spectrum-spread signal and outputs an analog signal a. The analog-digital converter 21 converts the analog signal a into a digital signal b, and inputs the digital signal b to n digital matched filters 22 _{1 to} 22 _n in parallel. Digital matched filter 22 ₁ ~
22 _n also generates a sampling clock signal based on the n operation clock signal cl ₁ -CL _n to be input independently from the clock 23 ₁ ~ 23 _n, and outputs the output data c ₁ to c _n despreading . The multiplexer 24 is 1
Th-digital matched filter 22 ₁ of n-th digital matched filters 22 _n output data c ₁ ~
and sequentially outputs to the absolute value calculating circuit 25 and c _n. The multiplexer 24 selects from the _first digital matched filter 22 ₁ to the nth digital matched filter 22 _n based on the output of the counter circuit 26. If the absolute value computation circuit 25, a look at the code of the output data c ₁ to c _n input positive value as it calculates the absolute value of the negative of the output data c ₁ takes the complement if the value to c _n, The data are sequentially output to the maximum absolute value search circuit 27. The maximum absolute value search circuit 27 compares the sequentially input data with the previous data, saves the previous data when the absolute value of the previous data is large, and stores the absolute value of the newly input data. If the value is large, the maximum value is updated. Here, when the maximum absolute value is further updated, the number of the digital matched filter 22 is counted in association with it, and when the number of outputs of the digital matched filter 22 is completed up to n, the digital signal with the maximum output level is output. The number of the matched filter 22 is determined and notified to the counter circuit 26. Based on the number, the counter circuit 26 controls the multiplexer 24 to select the digital matched filter 22 having the optimum sample timing. This gives 1
The despread data d with the minimum bit deterioration can be obtained at the timing of one sample of the chip. The primary demodulation unit 30 demodulates the despread data d and outputs the demodulated data.

[0019]

As described above, the present invention has an excellent effect that the bit deterioration can be minimized without increasing the sampling rate. In particular, when the spreading factor is small, or when one sample is used for one chip, bit deterioration is severe when the sampling timing is shifted. Therefore, using this method has an advantage that bit deterioration can be minimized.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a spread spectrum communication receiver according to an embodiment of the present invention.

FIG. 2 is a block configuration diagram of a spread demodulation unit of the spread spectrum communication receiving apparatus of the present invention.

FIG. 3 is a block configuration diagram of a digital matched filter of the spread spectrum communication receiver of the present invention.

FIG. 4 is a diagram showing an autocorrelation function of a spread spectrum signal of the spread spectrum communication receiver of the present invention.

[Explanation of symbols]

10 reception unit 20 spread demodulation unit 21 analog-digital converter 22, 22 _{1 to} 22 _n digital matched filter 23, 23 ₁ to 23 _n clock 24 multiplexer 25 absolute value calculation circuit 26 counter circuit 27 maximum absolute value search circuit 30 primary demodulation unit 31 mixer 32 spread code generator a analog signal b digital signal c, the output data cl, cl ₁ ~cl _n operation clock signal d output level is the maximum of the despread data from c ₁ to c _n digital matched filters

Claims (3)

[Claims] 1. A reception section (10) for receiving a spread spectrum signal, and a spread demodulation section (20) for despreading an output signal of this reception section, wherein the spread demodulation section (20) comprises the reception section. In a spread spectrum communication receiver including a converter for converting an analog signal to a digital signal for the output of the unit, and a digital matched filter for despreading the output of the converter, the number of the digital matched filters is n (n is 2). An integer greater than or equal to the above), and is connected in common to the outputs of the converters, and includes means for performing despreading processing by sampling the outputs of the converters at mutually independent timings. It is characterized in that it has a selecting means for obtaining the absolute value of the output and selecting the output of the digital matched filter having the maximum absolute value. Pectrum spread communication receiver. 2. A multiplexer (24) for sequentially outputting the outputs of the n digital matched filters as serial signals, and an absolute value calculation circuit (25) for calculating an absolute value of the output of the multiplexer. , A maximum absolute value search circuit (27) for detecting the maximum value of the n absolute values output from the absolute value calculation circuit and searching for the digital matched filter that has output the maximum value, and the multiplexer. A counter circuit (26) for fixing the output of the digital matched filter searched by the maximum absolute value search circuit so as to be selected and outputting the output as despread data. The spread spectrum communication receiver described. 3. The spread spectrum communication receiver according to claim 1, wherein said means for generating independent timing includes independent asynchronous clocks respectively provided so as to be supplied to each digital matched filter.