JPH0794779A - Sic light emitting device and its manufacture - Google Patents
Sic light emitting device and its manufactureInfo
- Publication number
- JPH0794779A JPH0794779A JP23761393A JP23761393A JPH0794779A JP H0794779 A JPH0794779 A JP H0794779A JP 23761393 A JP23761393 A JP 23761393A JP 23761393 A JP23761393 A JP 23761393A JP H0794779 A JPH0794779 A JP H0794779A
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- sic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
- Led Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、ＳｉＣ基板の両面に
濃度が異なる同一導電型のＳｉＣ層が同時に形成された
ＳｉＣ発光素子及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a SiC light emitting device in which SiC layers of the same conductivity type having different concentrations are simultaneously formed on both sides of a SiC substrate, and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来の技術をＳｉＣ青色発光ダイオード
を例に説明する。2. Description of the Related Art A conventional technique will be described by taking a SiC blue light emitting diode as an example.
【０００３】ＳｉＣ青色発光ダイオードは、６Ｈ型もし
くは４Ｈ型のＳｉＣ単結晶基板上に６Ｈ型の結晶を成長
させることにより作製される。ＳｉＣ発光素子の製造で
はA SiC blue light emitting diode is manufactured by growing a 6H type crystal on a 6H type or 4H type SiC single crystal substrate. In the manufacture of SiC light emitting device
【外３】 が使用される。ディッピング法を用いた液相エピタキシ
ャル成長により、図５（ａ）に示すように、約５００μ
ｍ厚のｎ型のＳｉＣ結晶基板５０の両面（Ｓｉ面及びＣ
面）にＡｌと窒素をドープしたｎ型の発光層１１を成長
し、続いてＡｌをドープしたｐ型のＳｉＣ層５２を成長
する。ディッピング法では、通常基板５０の両面に結晶
層が成長するためこの段階では、ｐｎｐ構造となる。[Outside 3] Is used. By liquid phase epitaxial growth using the dipping method, as shown in FIG.
Both sides of the n-type SiC crystal substrate 50 of m thickness (Si surface and C
On the surface, the n-type light emitting layer 11 doped with Al and nitrogen is grown, and then the p-type SiC layer 52 doped with Al is grown. In the dipping method, a crystal layer usually grows on both surfaces of the substrate 50, so that a pnp structure is formed at this stage.
【０００４】そのため、次に、図５（ｂ）に示すよう
に、主面とする反対の面をダイアモンド研磨粉を用いて
研磨し、１００〜４００μｍの厚みになるよう片側の成
長層５１，５２を除去する。次に、基板５０の表面を洗
浄処理した後、文献「春季応用物理学会予稿集、２９ａ
−Ｗ−１，Ｐ５８６（１９８５）」に記載されているよ
うに、ｐ型のＳｉＣ層５２上にＡｌ−Ｓｉ電極５３、ｎ
型のＳｉＣ結晶基板５０側にＮｉ電極１４を形成する。
又は、特開平２−１９６４２１号公報に記載されている
ように、ｐ型のＳｉＣ層５２上にＴｉ−Ａｌ、ｎ型のＳ
ｉＣ結晶基板５０側にＮｉ電極５４を形成する。Therefore, as shown in FIG. 5 (b), the surface opposite to the main surface is then polished with diamond polishing powder to grow the growth layers 51, 52 on one side to a thickness of 100 to 400 μm. To remove. Next, after cleaning the surface of the substrate 50, the document "Spring Society of Applied Physics, 29a"
-W-1, P586 (1985) ", the Al-Si electrode 53, n is formed on the p-type SiC layer 52.
The Ni electrode 14 is formed on the side of the SiC crystal substrate 50 of the mold.
Alternatively, as described in JP-A-2-196421, Ti-Al and n-type S are formed on the p-type SiC layer 52.
A Ni electrode 54 is formed on the iC crystal substrate 50 side.
【０００５】次に、ワイアボンディングパッド部及び導
電性接着剤などを塗布する部分を残し、ホトレジスト工
程を用いてパターニング除去し高温で熱処理する。その
後、パターニングに沿って２００〜３００μｍ角の素子
に分離し、図６に示すような従来から使用されているス
テム５５に導電性接着剤５６を用いて、上述したように
して形成された素子５７をマウントし、Ａｕワイヤ５８
を用いてワイアボンディングを行う。この場合に、光の
吸収が少ないｎ型結晶基板側を上にマウントすることに
より効率良く光を取り出すことができる。Next, the wire bonding pad portion and the portion to which the conductive adhesive is applied are left, and the patterning is removed using a photoresist process, followed by heat treatment at a high temperature. After that, the pattern is separated into elements of 200 to 300 μm square according to the patterning, and the element 57 formed as described above by using the conductive adhesive 56 on the conventionally used stem 55 as shown in FIG. Mount the Au wire 58
Wire bonding is performed using. In this case, light can be efficiently extracted by mounting the n-type crystal substrate side, which absorbs less light, on top.
【０００６】[0006]
【発明が解決しようとする課題】以上説明したように、
従来のＳｉＣ発光素子の構造においては、光の吸収が少
ないＳｉＣ結晶は一般的に低キャリア濃度であり、真に
透明な基板を用いようとすると、その基板のキャリア濃
度は１０16ｃｍ-3台以下となる。As described above,
In the structure of a conventional SiC light emitting device, an SiC crystal that absorbs little light generally has a low carrier concentration, and when a truly transparent substrate is used, the carrier concentration of the substrate is 10 16 cm −3 . It becomes the following.
【０００７】そのため、これに最適な電極形成条件で電
極を形成した場合でも、その接触抵抗は数十オームとな
り、通電電流による大きな電圧降下と熱が発生する。こ
の発熱は、発光素子をモジュール化しようとする場合、
特に大きな障害となっていた。Therefore, even when the electrodes are formed under the optimum electrode forming conditions, the contact resistance is several tens of ohms, and a large voltage drop and heat are generated due to the applied current. This heat is generated when the light emitting element is modularized.
It was a particularly big obstacle.
【０００８】そこで、この発明は、上記に鑑みてなされ
たものであり、その目的とするところは、製造工程の簡
略化ならびに発熱を低減することができるＳｉＣ発光素
子及びその製造方法を提供することにある。Therefore, the present invention has been made in view of the above, and an object thereof is to provide a SiC light emitting device and a manufacturing method thereof, which can simplify the manufacturing process and reduce heat generation. It is in.
【０００９】[0009]
【課題を解決するための手段】上記目的を達成するため
に、請求項１記載の発明は、第１導電型のＳｉＣ基板の
（０００１）面に液相成長により形成された第１導電型
の第１のＳｉＣ層と、In order to achieve the above object, the present invention according to claim 1 provides a first conductivity type SiC substrate formed by liquid phase growth on a (0001) plane of a first conductivity type SiC substrate. A first SiC layer,
【外４】 ｉＣ層と同時に液相成長により形成された第１導電型の
第２のＳｉＣ層と液相成長により第１のＳｉＣ層上にの
み形成された第２導電型のＳｉＣ層とから構成される。[Outside 4] The first conductivity type second SiC layer formed by liquid phase growth at the same time as the iC layer and the second conductivity type SiC layer formed only on the first SiC layer by liquid phase growth.
【００１０】請求項２記載の発明は、第１導電型のＳｉ
Ｃ基板の（０００１）面に第１導電According to a second aspect of the invention, the first conductivity type Si is used.
First conductivity on (0001) plane of C substrate
【外５】 くかつ高濃度の第１導電型の第２のＳｉＣ層とを、液相
成長により同時に形成する工程と、第１のＳｉＣ層上に
のみ第２導電型のＳｉＣ層を液相成長により形成する工
程とから構成される。[Outside 5] A step of simultaneously forming a low-concentration high-concentration second-conductivity-type second SiC layer by liquid-phase growth, and forming a second-conductivity-type SiC layer only on the first SiC layer by liquid-phase growth It consists of a process and.
【００１１】[0011]
【作用】発光素子を形成するＳｉＣ基板の主面を（００
０１）面とした場合及び、（０The main surface of the SiC substrate forming the light emitting element is (00
If it is a (01) plane and (0)
【外６】 図３及び図４に示す結果が得られた。この関係から、同
一成長時間では（０００[Outside 6] The results shown in FIGS. 3 and 4 were obtained. From this relationship, (000
【外７】 てはキャリア濃度が高くなることが明らかとなった。こ
れは、ｎ型不純物に限らず、ｐ型の不純物に関しても同
様な傾向を示した。[Outside 7] It became clear that the carrier concentration increased. This shows a similar tendency not only for n-type impurities but also for p-type impurities.
【００１２】本発明は、図３及び図４に示す成長速度の
差及び不純物添加量とキャリア濃度の関係から、第１導
電型の基板の（０００１）面に形成する第１導電型の第
１のＳｉＣ層の成長厚みを十分厚くすることにより、主
面と反対側の面すなわち（０According to the present invention, the first conductivity type first layer formed on the (0001) plane of the first conductivity type substrate is considered from the relationship between the growth rate difference and the impurity addition amount and the carrier concentration shown in FIGS. By sufficiently increasing the growth thickness of the SiC layer, the surface opposite to the main surface, that is, (0
【外８】 ＳｉＣ層を形成するとともに、（０００１）面に形成す
る第２の層の成長厚みを[Outside 8] In addition to forming the SiC layer, the growth thickness of the second layer formed on the (0001) plane
【外９】 ャリア濃度の第２のＳｉＣ層に第１導電型の電極を形成
することで、接触抵抗を低減することができる。[Outside 9] By forming the electrode of the first conductivity type on the second SiC layer having a carrier concentration, the contact resistance can be reduced.
【００１３】[0013]
【実施例】以下、本発明の詳細を図示の実施例によって
説明する。The details of the present invention will be described below with reference to the illustrated embodiments.
【００１４】図１は本発明の一実施例に係わるＳｉＣ青
色ＬＥＤのエピタキシャル成長工程を示す図であり、図
２は成長工程を実施する装置を示す図である。FIG. 1 is a diagram showing an epitaxial growth process of a SiC blue LED according to an embodiment of the present invention, and FIG. 2 is a diagram showing an apparatus for carrying out the growth process.
【００１５】図２において、１０は高周波コイル、１１
は石英管、１２は黒鉛ルツボ、１３はＳｉ融液、１４は
ＳｉＣ基板、１５は黒鉛よりなる基板保持具である。In FIG. 2, 10 is a high frequency coil, and 11
Is a quartz tube, 12 is a graphite crucible, 13 is a Si melt, 14 is a SiC substrate, and 15 is a substrate holder made of graphite.
【００１６】結晶成長時には黒鉛ルツボ１２を高周波に
より１７５０℃程度に加熱しＳｉを溶融する。この時、
黒鉛ルツボ１２にはルツボ底部から上部に向かって５ｄ
ｅｇ／ｃｍの割合で温度が高くなるように高周波コイル
１０の位置を調整する。Ｓｉ融液１３中にはｎ型結晶成
長の場合は、窒化珪素を２×１０-4ｗｔ％、アルミニウ
ムを０．９ａｔ％、ｐ型結晶成長の場合はアルミニウム
１．４ａｔ％を不純物として混入する。基板１４は（０
００１）面を下にして融液面にたいして並行に低速で回
転させながらディップする。During crystal growth, the graphite crucible 12 is heated to about 1750 ° C. by high frequency to melt Si. At this time,
The graphite crucible 12 has 5d from the bottom to the top.
The position of the high frequency coil 10 is adjusted so that the temperature rises at a rate of eg / cm. In the Si melt 13, 2 × 10 −4 wt% of silicon nitride, 0.9 at% of aluminum in the case of n-type crystal growth, and 1.4 at% of aluminum in the case of p-type crystal growth are mixed as impurities. . The substrate 14 is (0
The dip is performed while rotating the 001) surface downward and parallel to the melt surface at a low speed.
【００１７】ｎ型結晶成長の場合には、Ｓｉ融液１３の
高温部に一定時間浸漬し、続いて低温部に約１時間浸漬
する。成長終了後、基板１４をＳｉ融液１３の液面より
上部に引上げ冷却する。この時の（０００１）面のｎ型
のＳｉＣ層１６の成長厚みはIn the case of n-type crystal growth, the Si melt 13 is immersed in the high temperature part for a certain period of time, and subsequently, immersed in the low temperature part for about 1 hour. After the growth is completed, the substrate 14 is pulled up above the liquid surface of the Si melt 13 and cooled. At this time, the growth thickness of the n-type SiC layer 16 on the (0001) plane is
【外１０】 であった（図１（ａ））。[Outside 10] Was (Fig. 1 (a)).
【００１８】続いて、ｐ型結晶成長の場合には、ｎ型の
場合と同様に、Ｓｉ融液１３の高温部に一定時間浸漬
し、その後低温部に約１５分間浸漬する。成長終了後、
基板１４をＳｉ融液１３の液面より上部に引上げ冷却す
る。この時、（０００１）面にSubsequently, in the case of p-type crystal growth, as in the case of n-type crystal growth, the Si melt 13 is immersed in the high temperature part for a certain time and then in the low temperature part for about 15 minutes. After growth,
The substrate 14 is pulled above the liquid surface of the Si melt 13 and cooled. At this time, on the (0001) plane
【外１１】 起こらなかった（図１（ｂ））。[Outside 11] It did not happen (Fig. 1 (b)).
【００１９】ｎ型のＳｉＣ層成長後のＣ−Ｖ法による不
純物濃度判定では、（０００１）面In the impurity concentration determination by the CV method after the growth of the n-type SiC layer, the (0001) plane
【外１２】 物濃度は１０19ｃｍ-3台と考えられる高い値を示した。
また、続いて成長を行なったｐ型のＳｉＣ層の不純物濃
度は（０００１）面で５×１０18ｃｍ-3程度であ[Outside 12] The substance concentration showed a high value which was considered to be 10 19 cm -3 .
The impurity concentration of the subsequently grown p-type SiC layer is about 5 × 10 18 cm −3 on the (0001) plane.
【外１３】 まであった。[Outside 13] It was.
【００２０】最後に、従来と同様にして、ｎ型の電極を
ｎ型のＳｉＣ層１７上に形成し、ｐ型の電極をｐ型のＳ
ｉＣ層１８上に形成し、図６に示すように素子化されて
ＳｉＣ青色ＬＥＤが得られる。Finally, as in the conventional method, an n-type electrode is formed on the n-type SiC layer 17, and a p-type electrode is formed as a p-type S layer.
It is formed on the iC layer 18 and formed into a device as shown in FIG. 6 to obtain a SiC blue LED.
【００２１】上記実施例によれば、成長基板は成長後に
おいて既にｐｎ構造を成しており、成長後において主面
と反対側の面を研磨する必要がないため、製造が簡略化
されて生産コストを下げることができる。また、ｎ型の
電極を形成する側の不純物濃度が高く、接触抵抗を低減
することができるため、通電電流による大きな電圧降下
及び発熱を低減できる。According to the above embodiment, since the growth substrate has already formed the pn structure after the growth, and it is not necessary to polish the surface opposite to the main surface after the growth, the production is simplified and the production is performed. The cost can be reduced. Further, since the impurity concentration on the side where the n-type electrode is formed is high and the contact resistance can be reduced, it is possible to reduce a large voltage drop and heat generation due to the applied current.
【００２２】[0022]
【発明の効果】以上説明したように、この発明によれ
ば、ＳｉＣ基板の（０００１）面にｐ型As described above, according to the present invention, the p-type is formed on the (0001) plane of the SiC substrate.
【外１４】 成するようにしたので、ｎ型電極側のＳｉＣ層をｐ型電
極側のＳｉＣ層に比べて薄くかつ高濃度にｐ型電極側の
ＳｉＣ層と同時に形成することが可能となる。[Outside 14] Since it is formed, the SiC layer on the n-type electrode side can be formed simultaneously with the SiC layer on the p-type electrode side in a thinner and higher concentration than the SiC layer on the p-type electrode side.
【００２３】この結果、ｎ型電極側のＳｉＣ層を研磨す
ることなくｎ型電極の形成が可能となり、製造工程を簡
略化することができる。さらに、ｎ型電極側のＳｉＣ層
が高濃度であるため、ｎ型電極との接触抵抗が小さくな
り、接触部における発熱を低減することが可能となる。As a result, the n-type electrode can be formed without polishing the SiC layer on the n-type electrode side, and the manufacturing process can be simplified. Furthermore, since the concentration of the SiC layer on the n-type electrode side is high, the contact resistance with the n-type electrode is small, and it is possible to reduce heat generation at the contact portion.
【図１】この発明の一実施例に係わるＳｉＣ発光素子の
製造工程を示す図である。FIG. 1 is a diagram showing a manufacturing process of a SiC light emitting device according to an embodiment of the present invention.
【図２】図１に示す工程を実施する装置の概略を示す図
である。FIG. 2 is a schematic view of an apparatus for performing the process shown in FIG.
【図３】ＳｉＣ基板の面方位におけるＳｉＣ結晶の成長
速度と成長厚さの関係を示す図である。FIG. 3 is a diagram showing a relationship between a growth rate and a growth thickness of a SiC crystal in a plane orientation of a SiC substrate.
【図４】ＳｉＣ基板の面方位におけるＳｉＣ結晶のｎ型
不純物添加量と不純物濃度の関係を示す図である。FIG. 4 is a diagram showing the relationship between the amount of n-type impurities added to the SiC crystal and the impurity concentration in the plane direction of the SiC substrate.
【図５】従来のＳｉＣ発光素子の製造工程を示す図であ
る。FIG. 5 is a diagram showing a manufacturing process of a conventional SiC light emitting device.
【図６】製品化されたＳｉＣ発光素子の概略構成を示す
図である。FIG. 6 is a diagram showing a schematic configuration of a commercialized SiC light emitting device.
１０ 高周波コイル １１ 石英管 １２ 黒鉛ルツボ １３ Ｓｉ融液 １４ ＳｉＣ基板 １５ 基板保持具 １６ （０００１）面上に成長したｎ型ＳｉＣ層 １７ 高濃度ｎ型ＳｉＣ層 １８ ｐ型ＳｉＣ層 10 High-frequency coil 11 Quartz tube 12 Graphite crucible 13 Si melt 14 SiC substrate 15 Substrate holder 16 n-type SiC layer grown on (0001) plane 17 High-concentration n-type SiC layer 18 p-type SiC layer
Claims (2)
面に液相成長により形成された第１導電型の第１のＳｉ
Ｃ層と、 【外１】 ＳｉＣ層と同時に液相成長により形成された第１導電型
の第２のＳｉＣ層と、 液相成長により第１のＳｉＣ層上にのみ形成された第２
導電型のＳｉＣ層とを有することを特徴とするＳｉＣ発
光素子。1. A (0001) SiC substrate of the first conductivity type.
Conductive type first Si formed on the surface by liquid phase growth
Layer C and [External 1] A second SiC layer of the first conductivity type formed by liquid phase growth at the same time as the SiC layer, and a second SiC layer formed only on the first SiC layer by liquid phase growth
A SiC light-emitting device comprising a conductive type SiC layer.
面に第１導電型の第 【外２】 高濃度の第１導電型の第２のＳｉＣ層とを、液相成長に
より同時に形成する工程と、 第１のＳｉＣ層上にのみ第２導電型のＳｉＣ層を液相成
長により形成する工程とを有することを特徴とするＳｉ
Ｃ発光素子の製造方法。2. A (0001) of a first conductivity type SiC substrate.
The surface of the first conductivity type [External 2] A step of simultaneously forming a high concentration first conductivity type second SiC layer by liquid phase growth, and a step of forming a second conductivity type SiC layer only on the first SiC layer by liquid phase growth. Si characterized by having
C Light emitting device manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23761393A JPH0794779A (en) | 1993-09-24 | 1993-09-24 | Sic light emitting device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23761393A JPH0794779A (en) | 1993-09-24 | 1993-09-24 | Sic light emitting device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0794779A true JPH0794779A (en) | 1995-04-07 |
Family
ID=17017916
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23761393A Pending JPH0794779A (en) | 1993-09-24 | 1993-09-24 | Sic light emitting device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0794779A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014196437A1 (en) * | 2013-06-08 | 2014-12-11 | エルシード株式会社 | METHOD FOR PRODUCING SiC MATERIAL AND SiC MATERIAL LAMINATE |
-
1993
- 1993-09-24 JP JP23761393A patent/JPH0794779A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014196437A1 (en) * | 2013-06-08 | 2014-12-11 | エルシード株式会社 | METHOD FOR PRODUCING SiC MATERIAL AND SiC MATERIAL LAMINATE |
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