JPH0794724A - Insulating gate bipolar transistor and its manufacturing method - Google Patents

Abstract

PURPOSE:To improve latch-up withstanding strength that is regarded as a weak point in an insulating gate bipolar transistor with a vertical-type structure. CONSTITUTION:An n-type source layer 23, for example, is diffused inside a p-type base layer 22 that has been diffused from a surface of an n-type semiconductor region 12. After a recessed part 24 that reaches a semiconductor region 12 is drilled from the surface of the source layer 23 through the base layer 22, an insulating gate 25 is buried therein. A p-type collector layer 26 is diffused from the semiconductor region 12 on the opposite side to the insulating gate 25 in the source layer 23. Then, holes (h), which are produced by electrons (e) flowing into the collector layer 26, are taken out from a contact layer 27 of the base layer 22 to an emitter terminal (E). In addition, while the holes (h) pass sideways through the base layer 22 under the source layer 23, the holes (h) are injected into the source layer 23 so that latch-up affected from the holes (h) is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral insulated gate bipolar transistor (hereinafter referred to as IGBT) suitable for incorporation into an integrated circuit device and a manufacturing method thereof.

[0002]

2. Description of the Related Art As is well known, an IGBT has a feature that it has both a high input impedance of an insulated gate and a low output impedance of a bipolar transistor, and has an extremely high frequency characteristic as a transistor for high voltage or large current. It has come to be widely used for applications that do not require it. This IGBT has been conventionally used in the form of an individual element having a vertical structure, but recently, with the trend of so-called intelligence of power devices, a plurality of IGBTs and one related control circuit are integrated into one. The number of examples of incorporation into an integrated circuit device is increasing, and since a so-called planar structure is advantageous for this integration, the IGBT is often a lateral structure.

In order to make the IGBT a horizontal structure, the simplest structure is to simply bring the back side structure of the chip in the conventional vertical structure to the front side, and FIG. 5 shows a typical horizontal structure of this conventional type. The unit structure of the IGBT is shown in a sectional view. A chip or wafer for an integrated circuit is formed by growing an n-type epitaxial layer 2 on a p-type semiconductor substrate 1 as usual, and a lateral IGBT has the epitaxial layer 2 as its semiconductor region. The unit structure U shown in the figure is repeatedly formed in the left-right direction a plurality of times.

The central portion of the figure is the same as the vertical structure, and n
The p-type base layer 3 and the high-impurity-concentration base contact layer 4 are diffused from the surface of the p-type semiconductor region 2, and a polycrystalline silicon gate 5 is formed on both peripheral portions of the base layer 3 via a thin gate oxide film 5a. The n-type source layer 6 having a high impurity concentration and dipped into the lower side of the insulated gate 5 as shown in the figure to diffuse the p-type base contact layer 4 and the n-type source layer. The surface of 6 is short-circuited by the electrode film 9 of aluminum to lead out the emitter terminal E and the gate terminal G from the insulated gate 5.

The left and right end portions of FIG. 5 correspond to the back surface side of the chip in the vertical structure, and the same n-type buffer layer 7 is diffused from the surface of the semiconductor region 2 at a relatively high impurity concentration, and the inside thereof. Then, the p-type collector layer 8 is diffused with a high impurity concentration, and the electrode film 9 conductively connected to the surface thereof is used as the collector terminal C. The collector layer 8 is usually formed by simultaneous diffusion with the above-mentioned base contact layer 4 having the same p type and a high impurity concentration.

In the lateral IGBT shown in FIG. 5, the gate terminal G is applied with a voltage applied between the emitter terminal E and the collector terminal C.
When a positive voltage is applied to the emitter terminal E, an n-type channel is formed on the surface of the p-type base layer 3 below the insulated gate 5, and electrons serving as majority carriers from the n-type source layer 6 are generated in the semiconductor region 2. And to the collector layer 8 via the buffer layer 7, and in response to this, holes serving as minority carriers are injected from the p-type collector layer 8 into the semiconductor region 2 via the buffer layer 7, and this causes a base current to flow. As a bipolar transistor composed of the p-type base layer 3, the n-type semiconductor region 2 and the p-type collector layer 8 is turned on, the main terminals E and C are generated by the so-called conductivity modulation action of electrons and holes in the semiconductor region 2. It conducts at a very low on-voltage during the period. When the IGBT is turned off, the gate terminal G is applied with a voltage equal to or lower than the emitter terminal E to block electrons flowing through the channel below the insulated gate 5. The buffer layer 7 is for controlling the amount of holes injected from the collector layer 8 into the semiconductor region 2.

[0007]

The lateral IGBT described above can have a high breakdown voltage by increasing the distance between the base layer 3 and the collector layer 8 and can increase the current by increasing the number of repetitions of the unit structure U. Latch-up, which is a drawback of IGBT, is more likely to occur than in a vertical structure. FIG. 6 is an enlarged view of the right side portion of FIG.
And the moving path of the minority carrier hole h. The electrons e pass from the source layer 6 through the channel below the insulated gate 5 and enter the semiconductor region 2, and then flow from the buffer layer 7 to the collector layer 8 via a path along the surface thereof. On the other hand, hall h
Is injected from the collector layer 8 into the semiconductor region 2 through the buffer layer 7 and contributes to the conductivity modulation while passing through the range close to the surface by the Coulomb force acting between the electron e and the base layer 3 as shown in the figure. It enters and then escapes to the base contact layer 4 via the lower side of the source layer 6.

As described above, in the lateral IGBT, the holes h, which are minority carriers, flow laterally in the base layer 3 below the source layer 6, so that when the current due to the holes h increases, the holes h increase. 6 will be injected,
p-type collector layer 8, n-type semiconductor region 2, and p-type base layer 3
The pnpn four-layer thyristor structure existing between the n-type source layer 6 and the n-type source layer 6 is easily ignited to cause latch-up. The injection of the holes h into the source layer 6 is particularly likely to occur when an excessive overvoltage is applied between the collector terminal C and the emitter terminal E during turn-off of the IGBT. The reason is that when the potential drop due to the holes h flowing in the lateral direction in the base layer 3 increases, the base layer 3 and the source layer 6 are short-circuited by the emitter terminal E. The potential at the point indicated by I rises, the pn junction becomes forward biased at that point, and the hole h
Is easy to inject. Therefore, the IGBT having a lateral structure has a problem that the allowable current or the latch-up withstanding current that can be applied to the IGBT has been considerably reduced as compared with the conventional structure.

An object of the present invention is to solve the above problems and improve the latch-up resistance of a lateral IGBT.

[0010]

In the IGBT according to the present invention,
The base layer of the other conductivity type diffused from the surface of the semiconductor region of one conductivity type, the source layer of the one conductivity type diffused to the surface in this base layer, and the semiconductor layer passing through the base layer from the surface of the source layer. An insulating gate buried in a recess dug up to the region and a collector layer of the other conductivity type diffused from the surface of the semiconductor region on the side opposite to the insulating gate of the source layer are provided. The above object is achieved by deriving the emitter terminal from the source layer, the collector terminal from the collector layer, and the gate terminal from the insulated gate.

Also in the IGBT of the present invention, as in the conventional case, the base contact layer is diffused on the surface side of the base layer with the other conductivity type so as to overlap the peripheral edge of the base contact layer and contact the source layer. Is preferably derived, and the buffer layer surrounding the collector layer from the outside may be diffused in one conductivity type. In order to further improve the latch-up resistance of this IGBT, a semiconductor region in which one conductivity type auxiliary collector layer is diffused into the pattern portion of the collector layer surrounding the tip on the planar pattern of the source layer or in contact with the collector layer is used. It is very advantageous to diffuse the auxiliary collector layer in one conductivity type from the surface of and to derive the collector terminal from such auxiliary collector layer and collector layer.

Further, the method of manufacturing the lateral structure IGBT according to the present invention includes a step of diffusing the base layer with the other conductivity type from the surface of the semiconductor region of one conductivity type, and the source layer on the surface within the base layer. With one conductivity type,
The step of digging a recess from the surface of the source layer through the base layer to the semiconductor region, the step of embedding an insulated gate in this recess, and the step of removing the collector layer from the surface of the semiconductor region on the side of the base layer and the source layer It is preferable to go through the step of diffusing with the conductivity type of, and at the same time with the step of diffusing the collector layer, the base contact layer described above is overlapped with the periphery of the base contact layer on the surface side of the base layer with the same other conductivity type. It is advantageous to diffuse.

[0013]

In the conventional lateral IGBT, the collector layer 8 is arranged on the same side as the insulated gate 5 with respect to the source layer 3 as shown in FIG. 6, but in the present invention, the insulated gate is buried as described in the preceding paragraph. By arranging the collector layer on the side opposite to the insulated gate of the source layer, minority carriers that cause latch-up do not pass laterally in the base layer below the source layer as in the conventional case. By directly pulling out from the base layer or its contact layer to the emitter terminal, injection of minority carriers into the source layer is almost completely prevented, and the latch-up withstand capability is improved. In the embodiment in which the base contact layer that connects the base layer to the emitter terminal is provided, almost all of the minority carriers are pulled out only through the base contact layer having a high impurity concentration and a low resistance, so that the effect of improving the latch-up withstand level can be further enhanced. You can

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the IGBT of the present invention, and FIG.
FIG. 3 shows an IGBT manufacturing method corresponding to the embodiment of FIG.
And FIG. 4 show different embodiments of the present invention. Figure 1
(a) is a cross-sectional view showing a unit structure U of the lateral IGBT according to the present invention, which corresponds to FIG. 5 described above.
Reference numeral 10 is, for example, an n-type epitaxial layer 12 grown on a p-type semiconductor substrate 11 with a predetermined impurity concentration, and the IGBT of the present invention uses the epitaxial layer 12 as a semiconductor region for the epitaxial layer 12 for the unit structure U shown in the figure. Usually, it is made by repeatedly making dozens of times in the left-right direction and connecting them in parallel.

The emitter side shown in the center of the figure is a characteristic part of the lateral IGBT of the present invention, and the p-type base layer 22 is diffused from the surface of the n-type semiconductor region 12 described above to a slightly deeper position. , And an n-type source layer on the inner surface of the base layer 22.
After shallowly diffusing 23 with a high impurity concentration, a trench-shaped recess
24 is dug from the central surface of the source layer 23 through the base layer 22 to reach the semiconductor region 12 below it, and this recess is formed.
Insulated gate 25 is formed by embedding, for example, polycrystalline silicon, which is insulated by a very thin gate oxide film 25a, into 24, and in the example shown in the figure, it is p-type so as to overlap with the peripheral edge of the base layer 22 and contact the source layer 23. Base contact layer 27
Is diffused with a high impurity concentration. Base layer 22 and source layer
An electrode film 31 for leading the emitter terminal E from 23 is provided so as to short-circuit the surfaces of the source layer 23 and the base contact layer 27. Further, the gate terminal G is led out from the insulated gate 25.

The collector side shown in the left and right portions of the figure has the same structure as the conventional one, and the same n-type buffer layer 21 is diffused from the surface of the semiconductor region 12 at a relatively high impurity concentration, and the p-type is formed inside thereof. The collector terminal C is derived from the electrode film 32 which is diffused in the collector layer 26 at a high impurity concentration and conductively connected to the collector layer 26. In the conventional structure shown in FIGS. 5 and 6, the collector terminal C is provided on the same side as the insulated gate 5 of the source layer 6. Whereas the collector layer 8 is provided, in the present invention, the collector layer 26 is replaced by the insulated gate of the source layer 22.
The difference is that it is placed on the opposite side of 25.

The movement paths of the majority carriers or electrons e and the minority carriers or holes h in the ON state of the IGBT of the present invention constructed as described above are shown in FIG. 1 (b) in a manner corresponding to FIG. Since the insulated gate 25 is embedded in the IGBT of the present invention, a channel is formed on the surface of the side surface of the recess 24 of the base layer 22 in contact with the gate oxide film 25a, and the electron e passes from this source layer 23 through the channel to the semiconductor. After flowing into the lower part of the base layer 22 in the region 12, it flows into the collector layer 26 via the buffer layer 21 through the oblique flow path indicated by Pe in the figure. The holes h generated from the contact layer 26 due to the inflow of the electrons e are injected into the semiconductor region 12 through the buffer layer 21, and then, as shown in the figure, a part thereof is a Coulomb force acting between the holes and the electrons e. Then, after flowing through the internal flow path Ph1 and the other portion through the surface flow path Ph2, they enter the base layer 22, the contact layer 27 in the example in the figure, and are withdrawn toward the electrode film 31 on the surface. Incidentally, in this ON state, the conductivity modulation action occurs between the holes h and the electrons e, as in the conventional case.

According to the present invention, as described above, the collector layer 26 is disposed on the side of the source layer 22 opposite to the insulated gate 25.
As can be seen from (b), the extraction location of the hole h is on the same side as the collector layer 26 with respect to the source layer 23. Therefore, according to the present invention, the holes h may pass through the base layer 22 below the source layer 23 in the lateral direction and may be injected into the source layer 23 by the forward bias of the pn junction between the two layers, as shown in FIG. It is possible to improve the latch-up withstanding capacity by almost eliminating. In particular, in the embodiment in which the base contact layer 27 having a high impurity concentration is provided as shown in the figure, its specific resistance is much lower than that of the base layer 22, so that the possibility of injecting holes h due to the forward bias of the pn junction is further reduced. The effect of improving the latch-up resistance can be further enhanced.

Also, when the IGBT is turned off, the electrons e and holes h remaining in the semiconductor region 2 are swept out to expand the depletion layer. Since the Coulomb force to the hole h decreases sharply, most of the hole h is the above-mentioned surface flow path Ph.
It is pulled out via 2nd person. Therefore, in the present invention, the risk of holes h being injected into the source layer 23 at the time of turn-off can be further reduced than at the time of turn-on, and the latch-up resistance of the lateral IGBT can be increased. As described above, in the lateral IGBT of the present invention, the latch-up withstand capability can be increased several times when it is turned on, and can be increased by about one digit when turned off. Further, the IGBT of the present invention can shorten the turn-off time as compared with the conventional one. That is, the turn-off characteristic is almost determined by the time for sweeping out the hole h whose mobility is lower than that of the electron e, but the drift time becomes shorter because the extraction location of the hole h is closer to the collector layer 26 than before, and the withstand voltage value of the IGBT is reduced. The turn-off time can be reduced by 20 to 30% depending on the above.

Next, the method of manufacturing the IGBT of the present invention will be described with reference to FIG. 2 for the IGBT of FIG. The base layer is shown in Fig. 2 (a).
22 shows 22 diffusion steps. Only the n-type semiconductor region 12, which is an epitaxial layer, is shown on the wafer 10 in the figure.
When the withstand voltage is about 300 V, the semiconductor region 12 has a specific resistance of about 40 Ωcm and a thickness of at least 10 μm to several tens of μm. In the example shown in the figure, first the n-type buffer layer 21 for the collector layer is, for example, 10
After diffusing to a depth of 4 μm with an impurity concentration of ¹⁷ atoms / cm ³ , the p-type base layer 22 is diffused to a depth of ³ to 4 μm with an impurity concentration of 10 ¹⁷ atoms / cm ³ , for example. In either case, ion implantation of impurities and thermal diffusion using a photoresist as a mask may be used.

In the step of FIG. 2B, the source layer 23 is diffused in the n-type. The diffusion pattern is made smaller than that of the base layer 22 as shown in the figure, and, for example, arsenic is used as the minimum n-type impurity.
By diffusing to a depth of about 0.1 μm with a high impurity concentration of 10 ¹⁹ atoms / cm ³ , this is formed on the inner surface portion of the base layer 22. The following FIG. 2 (c) shows the digging process of the recess 24. A reactive ion etching method is advantageous for digging the trench-shaped recess 24 as shown in the figure. First, a low temperature oxide film is applied as a mask M to a thickness of 1 to 1.5 μm and the recess 24 is dug. After opening the window with a width of 3 μm, for example, 10 Pa of etching gas in which silicon tetrachloride and nitrogen are mixed.
By performing reactive ion etching for about 30 minutes in an ambient atmosphere, the recess 24 passes through the base layer 22 from the surface of the central portion of the source layer 23 to reach the lower semiconductor region 12, for example, 4 to 6 μm. Dig into the depth of. This Figure 2
After the step (c), the mask M is removed.

FIG. 2D shows a gate oxide film for the insulated gate 25.
This is a step of coating 25a and growing polycrystalline silicon. First, the gate oxide film 25 is thinly applied to the surface including the recess 24 to a thickness of about 0.1 μm by a conventional thermal oxidation method, and then CVD is performed.
Method is used to grow impurity-doped polycrystalline silicon for the insulated gate 25 to a thickness of, for example, 2 μm to completely fill the recess 24. Next, Fig. 2 (e) shows a step of removing unnecessary portions of polycrystalline silicon. After removing unnecessary portions of polycrystalline silicon by dry etching using a photoresist as a mask, gate oxidation is performed by a simple wet etching with a fluorine solution. By removing the unnecessary portion of the film 25a, the insulated gate 25 is formed to have a sectional shape as shown in the drawing.

In this embodiment, the same p-type base contact layer 27 is diffused at the same time as the collector layer 26 in the step shown in FIG. 2 (f). As shown in the figure, the collector layer 26 has a high impurity concentration of about 10 ¹⁸ atoms / cm ³ so that the collector layer 26 is in the buffer layer 21 and the base contact layer 27 is in contact with the source layer 23 so as to overlap the peripheral edge on the surface side of the base layer 22. For example, it diffuses to a depth of 1 to 1.5 μm. This completes the diffusion process of the semiconductor layer, and in order to change the state of FIG. 2 (f) to the completed state of FIG. Opened aluminum electrode films 31 and 32 are provided for the emitter terminal E and the collector terminal C, respectively, and an electrode film for the gate terminal G is provided on the insulated gate 25 at a position other than the illustrated cross section,
Further, it may be covered with a usual protective film.

Next, a preferred embodiment will be described with reference to the partially enlarged top view of the IGBT of the present invention shown in FIG. The up-down direction of FIG. 3 is the left-right direction of FIG. 1, and for convenience of illustration, the central portion in the left-right direction is omitted in FIG. 3, and the electrode films 31 and 32 are removed from FIG. . The embedded portion of the insulated gate 25 in the recess 24 is in the shape of a comb tooth that is elongated in the left-right direction in the figure, and the comb teeth are interconnected by the polycrystalline silicon of the insulated gate 25 that covers the surface on the left side of the figure. The gate terminal G is led out from this connecting portion to form a comb-like structure. The collector layer 26 is also diffused in a pattern in which p-shaped comb-teeth portions elongated in the left-right direction are connected by an auxiliary collector layer 26a.
Since a is originally p-type as shown by (p) in the figure, the collector layer 26 and the insulated gate 25 have a comb-like structure in which they are intricately integrated with each other.

The surface of the semiconductor region 12, the buffer layer 21, the source layer 23, and the base contact layer 27, which are interposed between the insulated gate 25 and the collector layer 26, have a bent meandering pattern. As described above, the emitter terminal E is derived from the source layer 23 and the base contact layer 27, and the collector terminal C is derived from the collector layer 26. However, in the vicinity of the tip of the pattern of the source layer 23, the holes h are concentrated from the surrounding collector layer 26 as shown by the arrow in the figure, so that the tip is most likely to cause latch-up due to injection of the hole h. It becomes a point. In the embodiment of FIG. 3, paying attention to this point, the collector layer 26 surrounding the tip of the pattern of the source layer 23 has an n-type auxiliary collector layer 26a instead of the p-type as shown in the figure.
Of the electrode film 32 of FIG.
And short-circuit to make collector terminal C. As a result, the same n-type auxiliary collector layer 26a as the source layer 23 is diffused into a field-effect transistor free from latch-up.
It can be further improved over the embodiment of FIG. 1 without 26a. Thus, the auxiliary collector layer 26a may be p-type, but n-type is more preferable.

In the embodiment shown in FIG. 4 in a section corresponding to FIG. 1A, the emitter side at the center of the drawing is the same as that of the embodiment shown in FIG. 1, but an n-type auxiliary collector layer 26b is provided on the collector side. P
In the illustrated example, the collector layer 26 of the shape is diffused so as to be surrounded by the collector layer 26, and the surface of the collector layer 26 and the collector layer 26 are short-circuited by the electrode film 32 to form the collector terminal C. Auxiliary collector layer
26b may be co-diffused with the source layer 23, for example. In this embodiment, since a considerable amount of electrons e flow toward the auxiliary collector layer 26b, the on-voltage of the IGBT rises slightly, but the holes h
It is possible to improve the latch-up resistance by reducing the number of.

[0027]

As described above, in the lateral structure IGBT according to the present invention, the one conductivity type semiconductor region is diffused from the surface of the other conductivity type base layer to the surface of the one conductivity type semiconductor layer. Shape source layer is diffused, and then a recess is dug from the surface of the source layer to penetrate the base layer to reach the semiconductor region to bury the insulated gate, and to the side of the source layer opposite to the insulated gate. The following effects can be obtained by diffusing the collector layer of the other conductivity type from the surface of the semiconductor region.

(A) Since the collector layer can be disposed on the opposite side of the source layer from the insulated gate by embedding the insulated gate in the recess, minority carriers that cause latch-up are the same as in the conventional source layer insulated gate. The minority carriers are almost not injected into the source layer by directly extracting from the base layer or the contact layer to the emitter terminal without passing the lower side of the source layer in the lateral direction unlike the structure in which the collector layer is disposed on the side. Completely prevent it and improve the latch-up resistance. In particular, in the aspect in which the contact layer having a high impurity concentration and low resistance is provided for the base layer, almost all of the minority carriers are extracted through the contact layer, so that the latch-up withstand capability can be further enhanced.

(B) After the supply of electrons to the semiconductor region is stopped when the IGBT is turned off, the Coulomb force exerted on the hole decreases, and most of the hole is extracted via the flow path near the surface of the semiconductor region. Therefore, the risk of holes being injected into the source layer is reduced rather than when it is turned on.
The latch-up resistance at the time of turn-off can be significantly increased compared to the conventional one.

(C) Since the collector layer is disposed on the side of the source layer opposite to the insulated gate, and therefore the hole extraction point is closer to the source layer on the same side as the collector layer, that is, it is closer to that on the collector layer than in the prior art, it is easier to move than electrons. The drift time in the semiconductor region during the turn-off of the IGBT of the low degree hole is shortened,
By sweeping holes from the semiconductor region and spreading the depletion layer within a short time, the turn-off time of the IGBT can be shortened and the applicable frequency can be increased.

The horizontal IG having the features of the present invention
BT is suitable for being incorporated in an integrated circuit device, and in addition to the above-mentioned excellent latch-up resistance and turn-off characteristics, it can be endowed with a high withstand voltage of several hundred V and a current capacity of 1 A or more as needed.

[Brief description of drawings]

1 shows an embodiment of an IGBT of the present invention, FIG. 1 (a) is a cross-sectional view of its unit structure, and FIG. 1 (b) is a main part of FIG. 1 (a) showing the flow of electrons and holes therein. FIG.

FIG. 2 shows a method for manufacturing an IGBT according to the embodiment of FIG. 1 in a state of each main step, and FIG. 2 (a) shows a diffusion step of a base layer,
The figure (b) shows the source layer diffusion step, the figure (c) shows the recess digging step, the figure (d) shows the growth step of polycrystalline silicon for the insulated gate, and the figure (e) shows the insulation step. Gate formation process, same figure
(f) shows the state of the collector layer during the diffusion process
It is a principal part expanded sectional view of IGBT.

FIG. 3 is an enlarged top view of essential parts of an IGBT showing a different embodiment of the present invention together with a planar pattern of the IGBT according to the embodiment of FIG.

FIG. 4 is a sectional view of a unit structure of an IGBT showing still another embodiment of the present invention.

FIG. 5 is a sectional view of a unit structure of a conventional lateral IGBT.

6 is an enlarged cross-sectional view of an essential part showing the flow of electrons and holes inside the IGBT of FIG.

[Explanation of symbols]

 10 IGBT chip or wafer for it 12 Semiconductor region or epitaxial layer 21 Buffer layer 22 Base layer 23 Source layer 24 Recess 25 Insulated gate 25a Gate oxide film 26 Collector layer 26a Auxiliary collector layer 26b Auxiliary collector layer 27 Base contact layer C Collector terminal E Emitter terminal e Electron or majority carrier G Gate terminal h Hole or minority carrier Pe Electron flow path Ph1 hole internal flow path Ph2 hole surface flow path

Claims (6)

[Claims] 1. A semiconductor region of one conductivity type, and a base layer of the other conductivity type diffused from the surface of the semiconductor region,
A source layer of one conductivity type diffused to the surface portion in the base layer, an insulated gate buried in a recess dug from the surface of the source layer to the semiconductor region through the base layer, and the source A collector layer of the other conductivity type diffused from the surface of the semiconductor region on the side opposite to the insulated gate of the layer, the emitter terminal from the base layer and the source layer,
An insulated gate bipolar transistor, wherein a collector terminal is derived from the collector layer and a gate terminal is derived from the insulated gate. 2. The transistor according to claim 1, wherein
Insulation characterized in that the base contact layer is diffused in the other conductivity type so as to overlap the peripheral edge of the base layer and contact the source layer, and the emitter terminal is led out from the base layer through this base contact layer. Gate bipolar transistor. 3. The transistor according to claim 1, wherein
An insulated gate bipolar transistor, wherein a buffer layer of one conductivity type is diffused so as to surround the collector layer from the outside. 4. The transistor according to claim 1, wherein
One of the conductivity type auxiliary collector layers is diffused in the diffusion pattern part of the collector layer surrounding the tip of the source layer in a planar pattern, and the collector terminal is derived from the collector layer and the auxiliary collector layer. And insulated gate bipolar transistor. 5. The transistor according to claim 1, wherein
An insulated gate bipolar transistor, characterized in that an auxiliary collector layer of one conductivity type is diffused on a surface of a semiconductor region in contact with the collector layer, and a collector terminal is derived from the collector layer and the auxiliary collector layer. 6. A step of diffusing a base layer with the other conductivity type from the surface of a semiconductor region of one conductivity type, a step of diffusing the source layer with the one conductivity type on the surface in the base layer, and a source layer. A step of digging a recess from the surface of the base layer to reach the semiconductor region, a step of embedding an insulating gate in this recess, and a step of forming a conductive layer from the surface of the semiconductor region on the side of the base layer and the source layer to the other conductive layer. And a step of diffusing in a shape.