JPH0794661A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPH0794661A
JPH0794661A JP23527393A JP23527393A JPH0794661A JP H0794661 A JPH0794661 A JP H0794661A JP 23527393 A JP23527393 A JP 23527393A JP 23527393 A JP23527393 A JP 23527393A JP H0794661 A JPH0794661 A JP H0794661A
Authority
JP
Japan
Prior art keywords
integrated circuit
lid
circuit device
view
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23527393A
Other languages
Japanese (ja)
Inventor
和史 ▲高▼橋
Kazufumi Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23527393A priority Critical patent/JPH0794661A/en
Publication of JPH0794661A publication Critical patent/JPH0794661A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate

Abstract

PURPOSE:To provide an integrated circuit device for inputting/outputting high speed signal in which the crosstalk and the interferential noise due to electrostatic coupling between the high speed signal wiring and the power supply/control signal wiring are suppressed. CONSTITUTION:The integrated circuit device comprising an integrated circuit chip 6 having first signal I/O electrodes 9A, 9B and second power supply/control signal electrodes 9C, 9D, a semiconductor circuit body 1 for mounting the integrated circuit chip, and a cover 2 covering the surface of the semiconductor circuit body 1, wherein the external wiring from the first electrodes 9A, 9B is formed on the semiconductor circuit body 1 whereas the external wiring from the second electrodes 9C, 9D is formed on the cover 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は集積回路装置に関し、特
に集積回路本体と蓋とを有し、外部に信号用のリード端
子と電源や制御信号授受用のリード端子を備えてパッケ
ージされた集積回路装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device, and more particularly, to an integrated circuit package having an integrated circuit body and a lid, and externally provided with lead terminals for signals and lead terminals for exchanging power and control signals. Regarding circuit devices.

【0002】[0002]

【従来の技術】従来、この種の集積回路装置は図4の組
立完了後のパッケージされた斜視図、および図5の集積
回路本体12の平面図に示すように、集積回路本体1
2、スペーサ11、蓋14から構成される。ここで集積
回路本体12は中央にセラミック基板3上の集積回路の
チップ6が搭載され、このチップ6の電極9A〜9Dか
ら信号入出力用のリード端子5A,5Bと、電源及び制
御信号授受用のリード端子5C,5Dとが、ワイヤ7お
よびリード端子4C,4Dを介して接続されている。す
なわち、すべての電気回路と接続用のリード端子は集積
回路本体12に配設されており、その上にスペーサ11
を介して蓋14で密封してパーケージを形成していた。
2. Description of the Related Art Conventionally, an integrated circuit device of this type is shown in FIG. 4 which is a packaged perspective view after assembly is completed and FIG. 5 is a plan view of an integrated circuit body 12.
2. It is composed of a spacer 11 and a lid 14. Here, the integrated circuit main body 12 has a chip 6 of the integrated circuit mounted on the ceramic substrate 3 in the center, and leads 9A to 5D for signal input / output from the electrodes 9A to 9D of the chip 6 and power / control signal transfer The lead terminals 5C and 5D are connected via the wire 7 and the lead terminals 4C and 4D. That is, all the electric circuits and the lead terminals for connection are arranged in the integrated circuit body 12, and the spacers 11 are arranged on the lead terminals.
It was sealed with a lid 14 via a via to form a package.

【0003】[0003]

【発明が解決しようとする課題】この従来の集積回路装
置では、集積回路本体に信号用の入出力リード端子及び
電源,制御信号のリード端子を搭載しているので、セラ
ミック基板等の誘電体内の静電結合による信号線路や電
源などの相互間の結合でクロストークおよび干渉ノイズ
等の現象が生じるという欠点があった。
In this conventional integrated circuit device, since the input / output lead terminals for the signal and the lead terminals for the power supply and the control signal are mounted on the integrated circuit main body, the dielectric body such as a ceramic substrate is provided. There is a drawback in that phenomena such as crosstalk and interference noise occur due to mutual coupling of signal lines and power supplies due to electrostatic coupling.

【0004】[0004]

【課題を解決するための手段】本発明の集積回路装置
は、信号の入力および出力用の第1の電極と電源および
制御信号用の第2の電極とを有する集積回路チップと、
この集積回路チップを搭載する半導体回路本体と、前記
半導体回路本体の面を被覆する蓋とを有する集積回路装
置において、前記第1の電極から外部への配線を前記半
導体回路本体に形成し、前記第2の電極から外部への配
線を前記蓋に形成している。
SUMMARY OF THE INVENTION An integrated circuit device of the present invention includes an integrated circuit chip having a first electrode for inputting and outputting signals and a second electrode for supplying power and control signals.
In an integrated circuit device having a semiconductor circuit body on which this integrated circuit chip is mounted and a lid covering the surface of the semiconductor circuit body, wiring from the first electrode to the outside is formed in the semiconductor circuit body, Wiring from the second electrode to the outside is formed on the lid.

【0005】[0005]

【実施例】次に本発明について図面を参照して説明す
る。図1(a)は本発明の第1の実施例の集積回路装置
の組立完了後の全体を示す斜視図、図1(b)は図1
(a)の蓋2を示す平面図、図1(c)は図1(a)の
集積回路本体1を示す平面図、図1(d)は図1(a)
の縦断面図である。図1(a)及び図1(d)により集
積回路装置の構成を説明する。本実施例の装置は集積回
路本体1、蓋2、スペーサ11から構成され、さらに蓋
2から外部に引出すリード端子5C,5Dと集積回路本
体1内のチップ6からワイヤ7を介して外部に引出すリ
ード端子5A,5Bを示している。図1(b)に示す蓋
2は図1の状態の蓋2を裏面から見た図であり、リード
端子5C,5Dを突起部10(図1(d)参照)のバン
プ8に接続するリード端子4C,4Dがセラミック基板
3に埋め込まれている。図1(c)に示す集積回路本体
1はチップ6を中央の凹部に搭載し、このチップ6の電
極9A〜9Dからワイヤ7とリード端子4A,4Bとを
介して信号の入出力となるリード端子5A,5Bに接続
されている。ここでリード端子4A,4Bは信号伝送路
となるので、所望の特性インピーダンスとなるように形
成されている。また電極9C,9Dは電源端子及び制御
端子であり、蓋2を組立てた状態で緩衝性のリード状の
バンプ8を介して蓋2のリード端子5C,5Dと接触す
るように設定される。したがってスペーサ11はこの接
触が良好に保持される高さに設定される。
The present invention will be described below with reference to the drawings. FIG. 1A is a perspective view showing the whole integrated circuit device of the first embodiment of the present invention after completion of assembly, and FIG.
1A is a plan view showing the lid 2, FIG. 1C is a plan view showing the integrated circuit body 1 of FIG. 1A, and FIG. 1D is FIG. 1A.
FIG. The structure of the integrated circuit device will be described with reference to FIGS. The device of this embodiment is composed of an integrated circuit body 1, a lid 2 and a spacer 11, and further leads from the lid 2 to the outside through lead terminals 5C and 5D and a chip 6 in the integrated circuit body 1 through a wire 7 to the outside. The lead terminals 5A and 5B are shown. The lid 2 shown in FIG. 1B is a view of the lid 2 in the state of FIG. 1 seen from the back side, and leads for connecting the lead terminals 5C and 5D to the bumps 8 of the protrusions 10 (see FIG. 1D). The terminals 4C and 4D are embedded in the ceramic substrate 3. In the integrated circuit body 1 shown in FIG. 1C, a chip 6 is mounted in a central recess, and leads for inputting and outputting signals from electrodes 9A to 9D of the chip 6 through wires 7 and lead terminals 4A and 4B. It is connected to terminals 5A and 5B. Here, since the lead terminals 4A and 4B serve as signal transmission paths, they are formed so as to have a desired characteristic impedance. The electrodes 9C and 9D are a power supply terminal and a control terminal, and are set so as to come into contact with the lead terminals 5C and 5D of the lid 2 through the bump-shaped bumps 8 having a buffer property when the lid 2 is assembled. Therefore, the spacer 11 is set to a height at which this contact is well maintained.

【0006】図2は本発明の第2の実施例を示す図であ
り、図2(a)は組立完了後の斜視図、図2(d)は図
2(a)の縦断面図、図2(b)は図2(a)の蓋2を
裏面から見た平面図、図2(c)は図2(a)の集積回
路本体1の平面図である。図1(a)〜(d)と図2
(a)〜(d)の各構成部品の符号は実質的に同一であ
るが、蓋2の方に信号入出力用のリード端子5A,5B
を配置し、集積回路本体1の方に電源及び制御信号用の
リード端子5C,5Dを配置している。
FIG. 2 is a view showing a second embodiment of the present invention, FIG. 2 (a) is a perspective view after completion of assembly, and FIG. 2 (d) is a vertical sectional view of FIG. 2 (a). 2 (b) is a plan view of the lid 2 of FIG. 2 (a) seen from the back side, and FIG. 2 (c) is a plan view of the integrated circuit body 1 of FIG. 2 (a). 1 (a)-(d) and FIG.
The reference numerals of the constituent parts of (a) to (d) are substantially the same, but lead terminals 5A and 5B for signal input / output are provided on the lid 2 side.
And lead terminals 5C and 5D for power supply and control signals are arranged toward the integrated circuit body 1.

【0007】図3は本発明の第3の実施例を示す図であ
り、図3(a)は第1の実施例である図1(c)の集積
回路本体1にタブ13を追加している。タブ13は図3
(b)の断面図に示すように、チップ6からリード端子
4A,4Bに接続するワイヤの中間接続体として使用さ
れる。
FIG. 3 is a diagram showing a third embodiment of the present invention. FIG. 3 (a) is a diagram showing the integrated circuit body 1 of FIG. 1 (c) which is the first embodiment with a tab 13 added. There is. The tab 13 is shown in FIG.
As shown in the sectional view of (b), it is used as an intermediate connecting body of a wire connecting the chip 6 to the lead terminals 4A and 4B.

【0008】以上説明したように本発明では信号用のリ
ード端子は集積回路本体に配置し、電源及び制御信号用
のリード端子を蓋に配置し、この間にスペーサにより間
隔をとるようにしたので、両者間の結合を排除して例え
ばクロストーク等を低減することができる。
As described above, in the present invention, the signal lead terminals are arranged in the integrated circuit main body, the power supply and control signal lead terminals are arranged in the lid, and the spacers are provided between the lead terminals to provide a space therebetween. By eliminating the coupling between the two, for example, crosstalk can be reduced.

【0009】[0009]

【発明の効果】以上説明したように本発明は、集積回路
装置内の信号用のリード端子と電源等のリード端子とこ
れらに付属する配線を集積回路本体と蓋とに分離したの
で、信号線路、電源、あるいは制御信号間の結合による
クロストーク及び干渉ノイズ等を低減できるという効果
を有する。
As described above, according to the present invention, the signal lead terminal in the integrated circuit device, the lead terminal for the power source and the like and the wirings attached to them are separated into the integrated circuit body and the lid. The effect is that crosstalk and interference noise due to the coupling between the power source and the control signal can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例の斜視図(a)、蓋の平
面図(b)、集積回路本体の平面図(c)、組立後の断
面図(d)である。
FIG. 1 is a perspective view (a) of a first embodiment of the present invention, a plan view of a lid (b), a plan view of an integrated circuit body (c), and a sectional view after assembly (d).

【図2】本発明の第2の実施例の斜視図(a)、平面図
(b),(c)、断面図(d)である。
FIG. 2 is a perspective view (a), plan views (b) and (c), and a sectional view (d) of a second embodiment of the present invention.

【図3】本発明の第3の実施例の集積回路本体の平面図
(a)、組立後の断面図(b)である。
FIG. 3 is a plan view (a) of an integrated circuit body of a third embodiment of the present invention, and a sectional view (b) after assembly.

【図4】従来の集積回路装置の斜視図である。FIG. 4 is a perspective view of a conventional integrated circuit device.

【図5】従来例の集積回路本体の平面図である。FIG. 5 is a plan view of a conventional integrated circuit body.

【符号の説明】[Explanation of symbols]

1,12 集積回路本体 2,14 蓋 3 セラミック基板 4A,4B リード端子 5A,5B 信号用のリード端子 5C,5D 電源等のリード端子 6 チップ 7 ワイヤ 8 バンプ 9A〜9D 電極 10 突起部 11 スペーサ 13 タブ 1, 12 Integrated circuit body 2, 14 Lid 3 Ceramic substrate 4A, 4B Lead terminal 5A, 5B Signal lead terminal 5C, 5D Lead terminal for power supply 6 Chip 7 Wire 8 Bump 9A-9D Electrode 10 Protrusion 11 Spacer 13 tab

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 27/04 21/822 8832−4M H01L 27/04 E ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication H01L 27/04 21/822 8832-4M H01L 27/04 E

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 信号の入力および出力用の第1の電極と
電源および制御信号用の第2の電極とを有する集積回路
チップと、この集積回路チップを搭載する半導体回路本
体と、前記半導体回路本体の面を被覆する蓋とを有する
集積回路装置において、前記第1の電極から外部への配
線を前記半導体回路本体に形成し、前記第2の電極から
外部への配線を前記蓋に形成していることを特徴とする
集積回路装置。
1. An integrated circuit chip having a first electrode for inputting and outputting a signal and a second electrode for a power source and a control signal, a semiconductor circuit body on which the integrated circuit chip is mounted, and the semiconductor circuit. In an integrated circuit device having a lid covering a surface of a body, wiring from the first electrode to the outside is formed in the semiconductor circuit body, and wiring from the second electrode to the outside is formed in the lid. An integrated circuit device characterized by:
【請求項2】 前記集積回路チップに形成された前記第
2の電極と前記蓋に形成された配線先端部の接触部とが
弾性をもって接触するバンプで形成されることを特徴と
する請求項1記載の集積回路装置。
2. The bumps that elastically contact the second electrode formed on the integrated circuit chip and the contact portion of the wiring tip formed on the lid. The integrated circuit device described.
【請求項3】 前記第1の電極から前記半導体回路本体
への配線の中間接続部としてタブを使用していることを
特徴とする請求項1記載の集積回路装置。
3. The integrated circuit device according to claim 1, wherein a tab is used as an intermediate connecting portion of a wiring from the first electrode to the semiconductor circuit body.
JP23527393A 1993-09-22 1993-09-22 Integrated circuit device Pending JPH0794661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23527393A JPH0794661A (en) 1993-09-22 1993-09-22 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23527393A JPH0794661A (en) 1993-09-22 1993-09-22 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0794661A true JPH0794661A (en) 1995-04-07

Family

ID=16983659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23527393A Pending JPH0794661A (en) 1993-09-22 1993-09-22 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0794661A (en)

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