JPH10303203A - Semiconductor integrated circuit and its mounting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a parasitic component, for example, the parasitic impedance component of a semiconductor integrated circuit extremely small. SOLUTION: In a semiconductor integrated circuit, second electrode pads 13 and 14 which are electrically connected to the electrode pads of a printed wiring board on a substrate within a region surrounded by a group of first electrode pads 15. Therefore, the second electrode pads 13 and 14 can be provided near an integrated electronic circuit 1 and a parasitic component, for example, the parasitic impedance component caused by the wiring of wires in the substrate can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit and a method for mounting the same.

[0002]

2. Description of the Related Art A substrate (substrate) of a semiconductor integrated circuit is usually called a semiconductor chip, and is packaged with a resin or the like in order to prevent physical or chemical influence from the surrounding environment. . As shown in FIG. 7 in which a plan view is shown in FIG. 7A and a front view is shown in FIG. 7B, an electronic circuit is formed on the packaged semiconductor chip 70, and the electronic circuit is further operated. An electrode pad 71 for supplying power, grounding, and inputting and outputting various signals is provided. A lead 72 of a conductor is drawn out from a package 73 made of an insulating resin or the like, and is connected to an electrode or a wiring pattern formed on a printed wiring board 74. Also,
The electrode pads 71 on the semiconductor chip 70 and the leads 72 are connected by bonding wires 75.

The above-described leads 72 and bonding wires 75 are composed of conductors, but have a parasitic inductance and a parasitic resistance, and particularly have a large effect on input and output of high-frequency signals. Therefore, in order to minimize this parasitic inductance component and parasitic resistance,
The electrode pads 71 need to be formed as close as possible to the outer periphery of the semiconductor chip 70, and the lengths of the leads 72 and the bonding wires 75 need to be as short as possible.

On the other hand, since the bonding wire 75 is connected to the electrode pad 71 provided on the semiconductor chip 70, the electrode pad 71 must have a certain area. In the current technology, the electrode pad 71 needs to be formed in a rectangular shape of about 100 microns square, and therefore, a parasitic capacitance occurs between the electrode pad 71 and the substrate.

Further, as apparent from FIG. 8 showing the inside of the semiconductor chip 70 in detail, wirings 77 and 78 are provided between the electronic circuit 76 on the semiconductor chip 70 and the electrode pads 71.
It is connected by 79. The wirings 77, 78, and 79 also have a parasitic resistance. In particular, the semiconductor chip 70
The upper wiring becomes thinner as the degree of integration of the integrated circuit increases,
The parasitic resistance cannot be ignored. Further, the semiconductor chip 7
Depending on the structure of 0 and the circuit layout, as shown in FIG. 8, a crossing 80 occurs in the wiring, and a parasitic capacitance is generated between the wirings at the crossing 80. For this reason, there is a problem that interference from other wirings occurs through the parasitic capacitance.

FIG. 9 shows an integrated electronic circuit 76 taking into account the above-mentioned parasitic inductance and parasitic resistance of the leads and wires, the parasitic capacitance of the electrode pads, and the parasitic resistance and parasitic capacitance of the wiring on the substrate. The equivalent circuit around is shown. As shown,
The integrated electronic circuit 76 has a parasitic capacitance 82 between wirings.
Is present, between the integrated electronic circuit 76 and the signal input / output unit, between the integrated electronic circuit 76 and the power supply 86,
A parasitic impedance component 81 relating to input and output is parasitic between the integrated electronic circuit 76 and the ground. The parasitic impedance component 81 includes a parasitic inductance 8
4, a parasitic resistance 83, and a parasitic capacitance 85. Here, although it depends on the structure of the semiconductor integrated circuit and the package, the parasitic inductance 84 is usually several nH and the parasitic resistance 83
Is several hundred mΩ to several Ω, and the parasitic capacitances 82 and 85 are several tens pF to several hundred pF.

As described above, a semiconductor chip is mounted on a printed wiring board by a method called flip-chip bonding, in addition to packaging with a resin or the like.
For example, as shown in FIG. 10, a semiconductor chip 70 is mounted on a multilayer printed wiring board 90 by bumps 91 made of a material such as solder. The multilayer printed wiring board 90 has a conductive portion such as a wiring pattern 94 on an outer layer, and has wiring patterns 95 and 96 on an inner layer. Also, bump 9
Via holes 92 and 93 connected to the wiring pattern 95 extend from a portion opposite to the electrode pad 71 to be connected by 1. Semiconductor chip 7
In the case of No. 0, the bump 91 and the via holes 92, 93 are formed in a state where the bump 91 is bonded to the electrode pad 71.
Of the electrode pad 71 corresponding to. The semiconductor chip 70 is mounted on the multilayer printed wiring board 90 as shown in FIG. 11 or the semiconductor chip 7 provided on the multilayer printed wiring board 90 as shown in FIG.
It is placed in a hole larger than 0, and pressure and heat are applied to achieve bonding.

Further, as shown in FIG. 11 showing a main part of the connection between the multilayer printed wiring board 90 and the semiconductor chip 70, the semiconductor chip 70 connected to the multilayer printed wiring board 90 by bumps 91 is covered with a resin 97. Allow to solidify and fix. 11A is a plan view of the semiconductor chip 70, and FIG. 11B shows a main part of the connection between the multilayer printed wiring board 90 and the semiconductor chip 70.

[0009]

As described above, according to the flip-chip bonding method, since no lead is used, the parasitic impedance component related to the lead can be removed. Is still present, and has a problem that circuit characteristics are affected.

Furthermore, since the semiconductor chip 70 is covered with the resin 97, when the resin 97 is in a semi-solid state, the resin 97 is placed between the semiconductor chip 70 and the multilayer printed wiring board 90 as shown in FIG. There is a problem that the semiconductor chip 70 is lifted up and the electrical connection by the bumps 91 is alienated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems of a semiconductor integrated circuit and its mounting, and it is an object of the present invention to provide a power supply line, a ground line, a parasitic component in a signal line, for example, an impedance An object of the present invention is to provide a semiconductor integrated circuit whose components can be extremely reduced. Another object of the present invention is to provide a method of mounting a semiconductor integrated circuit which has a small parasitic impedance component even when mounted, and can be stably connected to a printed wiring board.

[0012]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a substrate having a first circuit surface on which an integrated electronic circuit is formed; and a peripheral portion of the substrate. A first electrode group provided on the same surface as the first electrode group and on the center side of the first electrode with respect to the electrode of the printed wiring board. A second electrode for obtaining electrical connection is provided. As a result, the electrodes can be provided in the vicinity of the integrated electronic circuit, and a parasitic component due to wiring routing in the substrate can be suppressed.

According to a sixth aspect of the present invention, there is provided a method for mounting a semiconductor integrated circuit, comprising the steps of:
And a first electrode group provided on a peripheral portion of the substrate, the same surface as the first electrode group, and a central portion more than the first electrode. On the side, a semiconductor integrated circuit provided with a second electrode for obtaining electrical connection to an electrode of a printed wiring board is provided, and the first electrode and the second electrode are provided on a multilayer printed wiring board. The electrodes provided in the first electrode group are connected to a first outer conductive portion and an inner layer of the multilayer printed wiring board, and the second electrodes are connected to the multilayer printed wiring board. Characterized by being connected to the second outer conductive portion. As a result, mounting is performed using a semiconductor integrated circuit in which electrodes can be provided in the vicinity of the integrated electronic circuit, and parasitic components due to wiring routing in the substrate are suppressed. Components can be suppressed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit according to an embodiment of the present invention and a method for mounting the same will be described below with reference to the accompanying drawings. In each drawing, the same components are denoted by the same reference numerals. FIG. 1 shows a semiconductor chip 20 of a semiconductor integrated circuit according to the present embodiment. In the semiconductor chip 20 according to this example, five electronic circuits (integrated circuits) 1 to 5 are formed. Since each of the electronic circuits 1 to 5 has basically the same configuration, the electronic circuit 1 will be described. On one end of the electronic circuit 1, a ground circuit region 6 for applying a ground potential to the electronic circuit 1 is formed, and on the other end of the electronic circuit 1, a power supply to the electronic circuit 1 is provided. Power supply circuit region 7 for providing

As described above, the semiconductor chip 2 which is a substrate (hereinafter, referred to as a substrate) in which the electronic circuit 1, the ground circuit region 6, and the power supply circuit region 7 are formed as a pair.
At the periphery of the circuit surface of No. 0, an electrode group including first electrode pads (first electrodes) 15 to be connected to the electronic circuit, the ground circuit area, and the power supply circuit area, respectively, is provided. In the present invention, these first electrode pads 1
5 and a second electrode pad (13, 13) for obtaining an electrical connection to the electrode pad of the printed wiring board, inside the first electrode pad 15.
14) is provided. In other words, the second electrode pad (13, 1) for obtaining electrical connection to the electrode pad of the printed wiring board is provided in a portion surrounded by the first electrode pad 15.
4) is provided.

In the present embodiment, a second electrode pad 14 is provided in the ground circuit area 6 and a second electrode pad 13 is provided in the power supply circuit area 7 in the present embodiment. . Electronic circuit 2 other than electronic circuit 1
Similarly, in Nos. 1 to 5, the second electrode pad is provided in the ground circuit area, and the second electrode pad is provided in the power supply circuit area.

Further, a part related to the electronic circuit 1 will be described. The electronic circuit 1 is connected to the first electrode pad 15 through signal lines 8, 9, and 10. The electronic circuit 1 and the required electronic circuits 4 and 5 are interconnected via signal lines 11 and 12, respectively. Electronic circuit 1
In the electronic circuits 2 to 5 other than the above, similarly to the electronic circuit 1,
It is connected to the first electrode pad 15 and other necessary electronic circuits via signal lines. Note that the first electrode pad 15,
Except for the second electrode pads 13 and 14, the surfaces on which these electrode pads and the electronic circuits 1 to 5 are provided are insulated by resist.

As described above, in the present embodiment, the second electrode pad is provided in the ground circuit area and the second electrode pad is provided in the power supply circuit area. A signal line for the first electrode pad 15 provided on the peripheral portion of the first electrode pad is removed. Therefore, the parasitic impedance component due to the signal line,
That is, the parasitic resistance and the parasitic inductance can be reduced. Further, since the number of connection of the signal lines to the first electrode pad 15 is reduced, it is possible to eliminate or reduce the intersection of the signal lines, and as a result, to prevent the occurrence of the parasitic capacitance at the intersection. it can.

Next, a method for mounting a semiconductor integrated circuit will be described with reference to FIG. In this example, the semiconductor chip 2
0 is mounted on the multilayer printed wiring board 22. In the multilayer printed wiring board 22, a wiring pattern (conductive portion) 23 is formed on the component surface (outer layer), and via holes (via holes) 27, 28 connected to an inner layer wiring pattern (conductive portion) 24 are formed. The via hole 2 formed and further connected to the wiring pattern (conductive portion) 25 in the inner layer
9 are formed. Positions (lands and the like) of the via holes 27 to 29 on the component surface and wiring pattern 2
The third end 23A is located at a position corresponding to the first electrode pad 15 and the second electrode pads 13 and 14 of the semiconductor chip 20, and forms a conductive portion.

The first electrode pad 15 and the second electrode pads 13 and 14 of the semiconductor chip 20 are, for example,
The bump 21 is bonded by a method such as transfer with the surface of the electrode pad facing upward. The semiconductor chip 20 to which the bumps 21 are adhered is turned over so that the surfaces of the bumps 21 and the electrode pads face downward, and the bumps 21 and the via holes 27 are turned down.
To 29, etc., are mounted on the multilayer printed wiring board 22, and the bumps 21 and the via holes 27 are
The connection between の 29 and so on is made. Thus, the semiconductor chip 20
Are electrically connected to the via holes 27 to 29 of the multilayer printed wiring board 22 via the bumps 21.

Another mounting method will be described with reference to FIGS. 3, 4, and 5. FIG. In this mounting method, the hole 3 for mounting the semiconductor chip 20 on the multilayer printed wiring board 30 is formed.
Drill 3 The hole 33 has an inclined wall 34 for holding the semiconductor chip 20 halfway when the semiconductor chip 20 is embedded. That is, as shown in FIGS. 5A and 5B, the semiconductor chip 2
Assuming that the plane shape of the reference numeral 0 is, for example, a square and one side is l1, the hole 3 formed in the multilayer printed wiring board 30
Numeral 3 is 12 at the entrance and one side at the bottom and one side at the bottom. Here, since the magnitude relation of l2>l1> l3 is set, it is easy to insert the semiconductor chip 20 when mounting the semiconductor chip 20 in the hole 33, and the semiconductor chip 20 is held by the inclined wall 34. The position can be fixed.

As shown in FIG. 4, the first electrode pad 15 of the semiconductor chip 20 and the second
The electrode pads 32 corresponding to the electrode pads 13 and 14 are provided. A wiring pattern 31 extends from a required electrode pad in the electrode pad 32. Further, on the component surface of the multilayer printed wiring board 30, an external wiring pattern 35 is provided.
Are formed. Further, a wiring pattern 36 is also formed on the inner layer. The wiring patterns 35 and 36 are connected by via holes 37 provided between required wiring patterns.

The first electrode pad 15 and the second electrode pads 13 and 14 of the semiconductor chip 20 have, for example,
The bump 21 is bonded by a method such as transfer with the surface of the electrode pad facing upward. The semiconductor chip 20 to which the bumps 21 are adhered is turned over, and the bumps 21 and the electrode pads 32 are positioned in the holes 33 with the surfaces of the bumps 21 and the electrode pads facing downward. The connection between the electrode pad 32 is made. Thus, the required electrode pads of the semiconductor chip 20 are electrically connected to the electrode pads 32 of the multilayer printed wiring board 30 via the bumps 21. Then, as shown in FIG. 5, the semiconductor chip 20 is held by the resin 38, but the lower peripheral surface of the semiconductor chip 20 abuts against the inclined wall 34 to hold the semiconductor chip 20.
Further, the bonding surface of the semiconductor chip 20 itself with the electrode pad 32 provided on the multilayer printed wiring board 30 by the bump 21 can be sealed, and the resin 38 can be prevented from sneaking to the bottom side.

As shown in FIG. 5B, the depth of the hole 33 is d1, and the distance from the semiconductor chip 20 to the bottom surface of the hole 20 in a state where the semiconductor chip 20 is stopped on the inclined wall 34. Is d2, the height of the bump 21 needs to be d2 or more. In addition, on the inclined wall 34,
As shown in FIG. 5C, a step 39 is formed at a distance d2 from the bottom surface of the hole 33, and the peripheral portion of the lower surface of the semiconductor chip 20 is placed on the step 39. With such a configuration, the semiconductor chip 20 can be held at a more accurate position, the sealing property is improved, and the effect of preventing the resin 38 from wrapping around is improved. In FIG. 5, the hole 3
The inclination angles of the three inclined walls 34 are the same. At this time, the relation among l1, l2, l3, d1, and d2 is d2 = d
1 (l1-l3) / (l2-l3), and the semiconductor chip 20 stops at the height of d2.

A dielectric 40 as shown in FIG. 4 is provided between wiring patterns 36 of a required inner layer of the multilayer printed circuit board 30.
To fix the wiring pattern 36
A desired capacitance element can be arranged therebetween. Further, it is also possible to mount the chip component 42 by soldering to the electrode pad 41 formed on the component surface opposite to the surface on which the semiconductor chip 20 is mounted.

Next, a semiconductor chip 60 according to another embodiment and a mounting method thereof will be described with reference to FIG. In this semiconductor chip 60, the first
The configuration of the surface on which the electrode pads and the second electrode pads are provided is the same as the configuration shown in FIG. The entire surface opposite to the surface on which the first and second electrode pads are provided is a ground electrode surface 61.

The semiconductor chip 60 is mounted in a hole 52 formed in a multilayer printed wiring board 50 in which an inner wiring pattern 51 is formed. The relationship between the size of the hole 52 and the size of the semiconductor chip 60 is as described with reference to FIG.
Is held in the middle of The semiconductor chip 60 is connected via bumps 21 to electrode pads provided on the multilayer printed wiring board 50. In the present embodiment, the ground electrode surface 61 of the semiconductor chip 60 is connected to the wiring pattern 54 so that the wiring pattern 54 of the inner layer is formed on the ground electrode surface 61.
To protect the semiconductor chip 60. With such a structure, the ground potential can be appropriately supplied to the semiconductor chip 60, and the semiconductor chip 60 can be protected. In this embodiment, the ground electrode surface 6
Although the semiconductor chip 1 is directly covered with the wiring pattern 54, a structure in which the ground electrode surface 61 side is covered with a conductive resin and the conductive resin is further covered with the wiring pattern 54 is the same as in the present embodiment. The ground potential can be appropriately supplied to the semiconductor chip 60 and the semiconductor chip 60 can be protected.

In the semiconductor chip according to each of the above embodiments, the signal line is extended from the electronic circuit 1 to the first electrode pad 15 as shown in FIG. A second electrode may be provided to enable transmission and reception of signals of the electronic circuit. With such a structure, the influence of a parasitic component, for example, a parasitic impedance component on a signal transmitted and received by the electronic circuit can be prevented.

[0029]

As described above, according to the semiconductor integrated circuit of the first aspect, the first circuit provided on the periphery of the substrate having the first circuit surface on which the integrated electronic circuit is formed. The second electrode for obtaining electrical connection to the electrode of the printed wiring board is provided on the same surface as the group of electrodes and closer to the center than the first electrode. This can be provided near the integrated electronic circuit, and a parasitic component, for example, a parasitic impedance component due to wiring routing in the substrate can be suppressed.

As described above, according to the semiconductor integrated circuit of the second aspect, the second electrode is provided adjacent to the electronic circuit and in the power supply circuit area for supplying power to the electronic circuit. Therefore, the second electrode can be provided in the power supply circuit region to suppress a parasitic component, for example, a parasitic impedance component.

As described above, according to the semiconductor integrated circuit of the third aspect, the second electrode is provided adjacent to the electronic circuit and in the ground circuit area for grounding the electronic circuit. Therefore, by providing the second electrode in the ground circuit region, it is possible to suppress a parasitic component, for example, a parasitic impedance component.

As described above, according to the semiconductor integrated circuit of the fourth aspect, the second surface behind the first circuit surface provided with the first electrode and the second electrode is connected to the ground electrode. Therefore, the second surface on the back side of the first circuit surface provided with the first electrode and the second electrode can be grounded,
An appropriate ground potential can be supplied.

As described above, according to the method of mounting a semiconductor integrated circuit according to the fifth aspect, the second electrode is adjacent to the electronic circuit, and inputs an AC signal and / or a DC signal to the electronic circuit. Alternatively, since it is connected to the signal line to be output, the second electrode can not only obtain a connection with the electrode of the printed wiring board but also obtain a connection with an adjacent electronic circuit, thereby facilitating circuit design. .

As described above, according to the semiconductor integrated circuit mounting method of the sixth aspect, the first circuit provided on the peripheral portion of the substrate having the first circuit surface on which the integrated electronic circuit is formed. The same surface as the group of electrodes of
A semiconductor integrated circuit provided with a second electrode for obtaining electrical connection to the electrode of the printed wiring board on the center side of the electrode is used. The first electrode and the second electrode are provided so that the surfaces on which the first electrode and the second electrode are provided face each other, and the electrodes of the first electrode group are connected to an outer conductive portion and an inner layer of the multilayer printed wiring board; Since the electrodes are connected to the second outer layer conductive portion of the multilayer printed wiring board, mounting using a semiconductor integrated circuit that can be provided in the vicinity of an electronic circuit in which the electrodes are integrated is performed. Since the parasitic component due to the routing is suppressed, the parasitic component can be suppressed as a whole.

As described above, according to the method of mounting a semiconductor integrated circuit according to claim 7, a hole having an inclined wall for holding the semiconductor integrated circuit when the semiconductor integrated circuit is embedded in the multilayer printed wiring board. Forming a portion and bonding the electrode of the semiconductor integrated circuit to the conductive portion of the multilayer printed wiring board exposed to the hole via a bump.
When the semiconductor integrated circuit is buried in the hole, it is held in the middle of the inclined wall, and since the semiconductor integrated circuit serves as a lid, the resin is prevented from entering between the multilayer printed wiring boards when covering the semiconductor integrated circuit with the resin. can do.

As described above, according to the semiconductor integrated circuit mounting method of the eighth aspect, the step for receiving the bottom of the semiconductor integrated circuit is formed in the middle of the inclined wall. When the semiconductor integrated circuit is embedded in the hole, the semiconductor integrated circuit can be appropriately held in the middle of the inclined wall.

As described above, according to the semiconductor integrated circuit mounting method of the ninth aspect, the distance from the bottom of the semiconductor at the position where the semiconductor is held to the bottom of the hole is equal to or less than the height of the bump. Therefore, when the semiconductor integrated circuit is held in the middle of the hole, the bump can be pressed to obtain an appropriate electrical connection.

As described above, according to the semiconductor integrated circuit mounting method of the present invention, the hole is sealed in a state where the semiconductor integrated circuit is inserted into the hole, so that the inside of the hole is sealed. The semiconductor integrated circuit can be appropriately fixed and protected.

As described above, according to the semiconductor integrated circuit mounting method of the eleventh aspect, the back surface side of the surface of the semiconductor integrated circuit on which the first electrode and the second electrode are provided becomes the ground electrode. Since the hole is sealed by covering the ground electrode with a conductive resin, and the resin is used to connect to a required conductive part in the outer conductive part and the inner conductive part of the multilayer printed wiring board, In the above, the semiconductor integrated circuit can be appropriately fixed, and the back surface side of the surface of the semiconductor integrated circuit on which the first electrode and the second electrode are provided can be grounded.

[Brief description of the drawings]

FIG. 1 is a diagram showing a planar structure of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a mounting state of the semiconductor integrated circuit according to the embodiment of the present invention;

FIG. 3 is a diagram illustrating a method of mounting the semiconductor integrated circuit according to the embodiment of the present invention.

FIG. 4 is a diagram illustrating a method for mounting the semiconductor integrated circuit according to the embodiment of the present invention.

FIG. 5 is a diagram illustrating a method for mounting the semiconductor integrated circuit according to the embodiment of the present invention.

FIG. 6 is a diagram illustrating a method of mounting the semiconductor integrated circuit according to the embodiment of the present invention.

FIG. 7 is a diagram for explaining a conventional method for mounting a semiconductor integrated circuit.

FIG. 8 is a plan view of a conventional semiconductor integrated circuit.

FIG. 9 is an equivalent circuit of a parasitic impedance component of a conventional semiconductor integrated circuit.

FIG. 10 is a diagram illustrating a conventional method for mounting a semiconductor integrated circuit.

FIG. 11 is a diagram for explaining a conventional method for mounting a semiconductor integrated circuit.

FIG. 12 is a diagram illustrating a conventional method for mounting a semiconductor integrated circuit.

[Explanation of symbols]

1-5 Electronic circuit 6 Ground circuit area 7 Power supply circuit area 8-12
Signal line 13, 14 Second electrode pad 15 First electrode pad 20, 60 Semiconductor chip 21 Bump 22, 30, 50 Multilayer printed wiring board 33, 5
2 holes 34, 53 Inclined wall

Claims (11)

[Claims] 1. A first device on which an integrated electronic circuit is formed.
A semiconductor integrated circuit having a substrate having a circuit surface of (i) and a first electrode group provided on a peripheral portion of the substrate, wherein the first electrode is on the same surface as the first electrode group. A semiconductor integrated circuit, wherein a second electrode for obtaining electrical connection to an electrode of the printed wiring board is provided closer to the center of the semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the second electrode is provided adjacent to the electronic circuit and provided in a power supply circuit region for supplying power to the electronic circuit. 3. The semiconductor integrated circuit according to claim 1, wherein the second electrode is provided adjacent to the electronic circuit and provided in a ground circuit region for grounding the electronic circuit. 4. The device according to claim 1, wherein the second surface on the back side of the first circuit surface provided with the first electrode and the second electrode is a ground electrode. Item 2. The semiconductor integrated circuit according to item 1. 5. The electronic device according to claim 1, wherein the second electrode is adjacent to the electronic circuit and is connected to a signal line for inputting or outputting an AC signal and / or a DC signal to the electronic circuit. The semiconductor integrated circuit according to any one of the above items. 6. A first device in which an integrated electronic circuit is formed.
And a first electrode group provided on a peripheral portion of the substrate, the same surface as the first electrode group, and a central portion more than the first electrode. A semiconductor integrated circuit provided with a second electrode for obtaining electrical connection to an electrode of the printed wiring board on the side of the printed circuit board;
The first electrode group is connected to a first outer conductive portion and an inner layer of the multilayer printed wiring board, and the second electrode is connected to the multilayer. A method for mounting a semiconductor integrated circuit, wherein the method is connected to a second outer conductive portion of a printed wiring board. 7. A multilayer printed wiring board, wherein a hole having an inclined wall for holding the semiconductor integrated circuit when the semiconductor integrated circuit is buried is formed, and a conductive portion of the multilayer printed wiring board exposed to the hole. 7. The method according to claim 6, wherein an electrode of the semiconductor integrated circuit is bonded via a bump. 8. The semiconductor integrated circuit mounting method according to claim 6, wherein a step for receiving the bottom of the semiconductor integrated circuit is formed in the middle of the inclined wall. . 9. The method according to claim 7, wherein the distance from the bottom of the semiconductor at the position where the semiconductor is held to the bottom of the hole is equal to or less than the height of the bump. A method for mounting a semiconductor integrated circuit. 10. The hole is sealed with the semiconductor integrated circuit inserted in the hole.
A mounting method of the semiconductor integrated circuit according to claim 9. 11. A first electrode and a second electrode of a semiconductor integrated circuit.
The back surface side of the surface provided with the electrodes is a ground electrode, covers the ground electrode with a conductive resin, seals the hole, and uses the resin to form an outer conductive portion and an inner layer of the multilayer printed wiring board. 11. The method for mounting a semiconductor integrated circuit according to claim 10, wherein the conductive part is connected to a required conductive part therein.