CN220456412U - Electronic device - Google Patents

Abstract

Disclosed according to embodiments of the present application is an electronic device comprising: a first chip; the power regulator is arranged above the first chip; the heat dissipation piece is used for providing power for the first chip, wherein the heat dissipation piece is provided with a space for accommodating the power regulator. In the above electronic device, by providing a space accommodating the power conditioner by using the heat sink and forming the power supply path of the first chip by such heat sink, the power supply path and the signal path can be arranged on different sides of the first chip, so that at least the problem of interference between the circuit and the signal caused by forming the power path and the signal path on the same side of the chip can be solved.

Description

Electronic device

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to an electronic device.

Background

In the current chip design, power and signals are laid out on the same side of the chip, for example, as shown in fig. 1, the power and signals are laid out on the lower sides of the chips 10 and 20, and reach the corresponding chips 10 and 20 from the substrate 12 via power paths P1 and P2 and signal paths S1 and S2, respectively. Specifically, the power paths P1, P2 and the signal paths S1, S2 are all transmitted to the chips 10, 20 via the substrate 12 and the redistribution layer 14 between the substrate 12 and the chips 10, 20. This requires additional design of signal blocking circuitry to avoid interference, which may result in a larger number of layers being required for the substrate 12 and the redistribution layer 14 to be laid out. And, the power and signal lines are limited to the same side, which also causes design limitations.

In addition, since the line width (or the line diameter) of the power line is generally higher than that of the signal line, the number of layers of the redistribution layer 14 cannot be reduced. For example, the line width/space (L/S) of the power lines is >8 μm/8 μm, the L/S of the signal lines is <5 μm/5 μm, and if they are integrated together, the number of layers of the redistribution layer 14 is greater than 6 dielectric layers and 6 metal line layers. In another aspect, the structure shown in FIG. 1 may be referred to as a Fanout module (Fanout module) 30. Too many layers of the substrate 12 and the redistribution layer 14 may also lead to warpage of the fan-out module 30, e.g., warpage of the fan-out module 30 may > +/-150 μm, which may lead to warpage difficult to control and board loading problems.

Disclosure of Invention

In view of the above problems, the present application provides an electronic device, which at least can solve the problem of interference between a circuit and a signal caused by forming a power path and a signal path on the same side of a chip.

The technical scheme of the application is realized as follows:

according to one aspect of the present application, there is provided an electronic device comprising: a first chip; a power conditioner arranged above the first chip; the heat dissipation piece is used for providing power for the first chip, wherein the heat dissipation piece is provided with a space for accommodating the power regulator.

In some embodiments, the heat sink provides power to the first chip through the power conditioner.

In some embodiments, the heat sink has a bottom surface adjacent the power conditioner and the first chip, with redistribution lines provided at the bottom surface to provide a line to transfer power and ground.

In some embodiments, the electronic device further comprises a substrate supporting the heat spreader and the first chip, wherein the substrate is electrically connected to the first chip through the redistribution lines at the bottom surface of the heat spreader.

In some embodiments, the substrate is connected to the heat sink via nanowires.

In some embodiments, the substrate has a first region adjacent an edge of the substrate and a second region disposed adjacent the first region, wherein power provided to the first chip is from the first region.

In some embodiments, the active surface of the first chip is disposed opposite to the second region, and is in signal communication with the second region.

In some embodiments, an insulating layer is disposed between the redistribution line and the heat sink.

In some embodiments, the electronic device further comprises a second chip adjacent to the first chip and to receive power provided from the heat sink.

In some embodiments, the power conditioner is connected to the heat sink through nanowires.

In the above electronic device, by providing a space accommodating the power conditioner by using the heat sink and forming the power supply path of the first chip by such heat sink, the power supply path and the signal path can be arranged on different sides of the first chip, so that at least the problem of interference between the circuit and the signal caused by forming the power path and the signal path on the same side of the chip can be solved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic cross-sectional view of a conventional layout of power lines and signal lines on the same side of a chip.

Fig. 2A is a schematic cross-sectional structure of an electronic device according to one embodiment of the present application.

FIG. 2B is a schematic diagram of various power paths and signal paths of the electronic device of FIG. 2A.

Fig. 3A is a schematic cross-sectional view of the heat spreader with redistribution layer of fig. 2A.

Fig. 3B is a schematic top view of fig. 3A.

Fig. 3C is a partially enlarged schematic view at a region A1 in fig. 2A.

Fig. 3D is a partially enlarged schematic view at a region A2 in fig. 2A.

Fig. 3E is a schematic top view of the electronic device of fig. 2A with the heat sink omitted.

Fig. 4A is a schematic cross-sectional structure of an electronic device according to another embodiment of the present application.

Fig. 4B is a schematic top view of the electronic device of fig. 4A with the heat sink omitted.

Fig. 4C is an enlarged partial schematic view at the power conditioner in fig. 4A.

Fig. 5A, 6A, 7A, 8A, 9A are schematic cross-sectional structures at various stages of forming the electronic device shown in fig. 2A.

Fig. 5B, 6B, 7B, 8B, 9B are schematic top views at various stages of forming the electronic device shown in fig. 2A.

Fig. 10A, 11A, 12A, 13A, and 14A are schematic cross-sectional structures at various stages of forming the electronic device shown in fig. 4A.

Fig. 10B, 11B, 12B, 13B, 14B are schematic top views at various stages of forming the electronic device shown in fig. 4A.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application are within the scope of the protection of the present application.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the utility model. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are in direct contact, and may also include embodiments in which additional components are formed between the first component and the second component such that the first component and the second component may not be in direct contact. Moreover, the present utility model may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In addition, embodiments and features of embodiments in this application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments. In the various drawings, the same reference numerals are used for the same elements.

An electronic device is provided according to various embodiments of the present application. Fig. 2A is a schematic cross-sectional structure of an electronic device 1000 according to one embodiment of the present application. Referring to fig. 2A, an electronic device 1000 provided herein includes a first chip 100, and a power conditioner 310 disposed above the first chip 100. In some embodiments, power conditioner 310 may be a voltage regulator (VR, voltage Regulated) chip. The electronic device 1000 further includes a heat sink 400. The heat sink 400 has a space 420 for accommodating the power conditioner 310. The heat sink 400 may be used to provide power to the first chip 100, that is, the first power supply path for providing power to the first chip 100 is extended to the first chip 100 by the heat sink 400, and such a first power supply path L1 is shown in fig. 2B. The first power supply path L1 specifically includes a first power path Lp1 and a first ground path Lg1. By means of the heat sink 400, the first power path Lp1 can enter the first chip 100 from the upper surface of the first chip 100 to drive the first chip 100, and the first ground path Lg1 extends to the ground via the upper surface of the first chip 100. In some embodiments, a lower surface side of the first chip 100 is used to configure the first signal path Ls1.

In the above-described electronic device 1000, by providing a space accommodating the power conditioner 310 by the heat sink 400 and forming the first power supply path L1 of the first chip 100 by such heat sink 400, the first power supply path L1 and the first signal path Ls1 can be disposed on different sides of the first chip 100, and thus the problem of interference between the circuit and the signal caused by forming the power path and the signal path on the same side of the chip can be solved and the limitation of design is avoided.

With continued reference to fig. 2A and 2B, the heat sink 400 supplies power to the first chip 100 through the power conditioner 310, that is, after the power is supplied to the power conditioner 310 by the heat sink 400, the power conditioner 310 may condition the power and then distribute the power to the first chip 100. In some embodiments, the upper surface of the first chip 100 facing the heat sink 400 is a passive surface of the first chip 100, and the opposite lower surface is an active surface. The first chip 100 has a first through via (TSV) 112 extending from an upper surface thereof to a lower surface thereof. The first TSV 112 may transfer power from the upper surface to the lower surface of the first chip 100 to drive the first chip 100.

With continued reference to fig. 2A, the electronic device 1000 may further include a substrate 500, and the substrate 500 may support the heat sink 400 and the first chip 100. The heat sink 400 may be attached to the substrate 500 by an adhesive layer 480. Wherein the power supplied to the first chip 100 may be from the substrate 500. The substrate 500 includes a first region 510 adjacent an edge 501 of the substrate 500, and a second region 520 disposed adjacent the first region 510. The power line 502 for supplying power, which has a larger wire diameter, may be provided only in the first region 510 and provide the first power supply path L1 shown in fig. 2B. The lower surface (active surface) of the first chip 100 is opposite to the second region 520 in the vertical direction, and performs signal transmission with the second region 520, and only the signal line 504 for signal transmission with a smaller line diameter may be laid out in the second region 520 to provide the first signal path Ls1 as shown in fig. 2B.

Accordingly, as shown in fig. 2B, the first power path Lp1 of the first chip 100 extends from the substrate 500, through the heat sink 400 to the power conditioner 310, and then through the power conditioner 310 to the upper surface of the first chip 100, and reaches the lower surface of the first chip 100 through the corresponding first TSV 112. Accordingly, the first ground path Lg1 of the first chip 100 is grounded through the corresponding first TSV 112 to the upper surface of the first chip 100, and then through the power conditioner 310 and the heat sink 400 to the substrate 500.

By configuring the first power supply path L1 from the first region 510 of the substrate 500 to the upper surface of the first chip 100 and the first signal path Ls1 from the second region 520 of the substrate 500 to the lower surface of the first chip 100, it is achieved that the first power supply path L1 and the first signal path Ls1 are separated from different regions of the substrate 500 to different sides of the first chip 100, and thus it is not necessary to design more layers of substrates to reduce parasitic capacitance, interference and wiring problems between power and signal lines, and the number of layers of the substrate 500 can be reduced. Warpage problems are also reduced due to the reduced number of layers of the substrate 500.

Referring to fig. 2A, the heat sink 400 has a bottom surface 400b facing the first chip 100. The bottom surface 400b has a first partial bottom surface 400b1 adjacent to the power conditioner 310 and the first chip 100, and a second partial bottom surface 400b2 connecting the first chip 100. The second partial bottom surface 400b2 may be connected to a portion of the upper surface of the first chip 100 through a heat conductive layer 600 to dissipate heat from the first chip 100. In addition, the heat sink 400 has a protrusion 430 at the first portion bottom 400b1, and the protrusion 430 is connected to the power conditioner 310 through the heat conductive layer 600 to dissipate heat from the power conditioner 310. The thermally conductive layer 600 connected to the first chip 100 and the thermally conductive layer connected to the power conditioner 310 may be patterned thermally conductive layers formed in the same process, and thus collectively referred to as the thermally conductive layer 600. For some embodiments, the material of the thermally conductive layer 600 may employ a thermally conductive interface material (TIM, thermal Interface Material).

The first partial bottom surface 400b1 may extend over the power conditioner 310 and to the junction of the heat sink 400 and the first region 510 of the substrate 500. The first partial bottom surface 400b1 is spaced apart from the first chip 100 in the vertical direction to form a space 420 for accommodating the power conditioner 310. The electronic device 1000 further includes a passive element 320 such as an inductor, a capacitor, a resistor, or the like, or a combination thereof, the passive element 320 and the power regulator 310 are disposed together in a space 420 provided by the heat sink 400, and the passive element 320 can be used as a part of a voltage stabilizing circuit.

The first partial bottom surface 400B1 may be used to form a first power supply path L1 as shown in fig. 2B. Specifically, the first power supply path L1 shown in fig. 2B is provided by forming the redistribution layer 810 on the first portion bottom surface 400B 1. Fig. 3A is a schematic cross-sectional view of the heat sink 400 with the redistribution layer 810 in fig. 2A, with the bottom surface 400b of the heat sink 400 disposed upward in fig. 3A. Fig. 3B is a schematic top view of fig. 3A. As shown in connection with fig. 2A, 3A and 3B, a redistribution layer 810 is disposed at the first portion bottom surface 400B 1. Redistribution layer 810 may include a dielectric layer 812 and a redistribution line 814 embedded in dielectric layer 812, redistribution line 814 providing a line for transferring power and ground. By designing the redistribution traces 814 for transferring power and grounding at the first portion bottom surface 400B1 of the heat sink 400, as shown in fig. 3B, since no other traces are disposed on the heat sink 400, the redistribution traces 814 in the redistribution layer 810 are allowed to be disposed at a smaller density and more sparse, so as to reduce parasitic capacitance and interference between the traces.

Referring to fig. 2A and 3A, an additional insulating layer 820 is further disposed between the redistribution layer 810 and the heat sink 400. The redistribution lines 814 in the redistribution layer 810 may be further isolated from the heat sink 400 by an insulating layer 820. By providing the insulating layer 820 between the redistribution layer 810 and the heat spreader 400, shorting and parasitic capacitance effects can be avoided.

Further, referring to fig. 2A, a portion 400bs of the first portion bottom surface 400b1 of the heat sink 400 opposite to the side surface of the first chip 100 is inclined (rather than vertical), and the portion 400bs extends gradually closer to the first chip 100 in a direction away from the substrate 500. In some embodiments, the redistribution layer 810 is formed by: referring to fig. 3A, an insulating layer 820 is first formed on a first partial bottom surface 400b1 of the heat sink 400; then, when the heat spreader 400 is placed upward, a dielectric layer 812 of the redistribution layer 810 is formed on the insulating layer 820, and then a redistribution line 814 is formed by electroplating on the dielectric layer 812. If the portion 400bs is vertically extended, the redistribution line 814 may not be formed by electroplating. By providing the portion 400bs to be inclined, it is possible to allow the corresponding redistribution line 814 to be formed by electroplating on the portion 400bs by an electroplating process.

The substrate 500 is electrically connected to the first chip 100 through the redistribution traces 814 at the first portion of the bottom surface 400b1 of the heat spreader 400. Fig. 3C is a partially enlarged schematic view at a region A1 in fig. 2A. Referring to fig. 3C, the substrate 500 is connected to the redistribution layer 810 at the heat spreader 400 through the nanowires 710. The redistribution lines 814 in the redistribution layer 810 include contacts 818, and the substrate 500 is connected to the corresponding contacts 818 through nanowires 710. In some embodiments, the material of the nanowires 710 is the same as the material of the power lines 502 in the substrate 500 under the nanowires 710, e.g., copper. Because the warpage of the substrate 500 at the edge (e.g., the edge 501) is greatest and the stress is more concentrated, if the substrate 500 and the heat sink 400 are bonded by using the conventional copper bump and solder ball, the warpage at the edge 501 of the substrate 500 is greater due to the diversification of the materials of copper and tin. The present application interfaces with the redistribution layer 810 on the heat spreader 400 through the nanowires 710, and because a more single material (e.g., copper material) is used near the edge 501 of the substrate 500, the material diversity problem at the edge 501 of the substrate 500 can be reduced, warpage can be reduced, and the risk of cracking due to stress concentration can be reduced.

Fig. 3D is a partially enlarged schematic view at a region A2 in fig. 2A. Referring to fig. 3D, the power conditioner 310 is connected to the heat sink 400 through the nanowire 720. A wiring layer 330 may be provided on the upper surface of the power conditioner 310. Corresponding contacts 819 in the redistribution layer 810 at the heat spreader 400 are connected to the wiring layer 330 through nanowires 720. Thus, the power transferred from the redistribution layer 810 reaches the upper surface of the power conditioner 310 via the wiring layer 330, and is transferred to the lower surface via the third TSV 312 passing through the power conditioner 310. In addition, the heat conductive layer 600 above the power conditioner 310 is in contact with the wiring layer 330 in particular to dissipate heat from the power conditioner 310. The protruding portion 430 of the heat sink 400 extends through the redistribution layer 810 onto the heat conductive layer 600.

In some embodiments, the heat spreader 400 is placed over the substrate 500 by a pick and place process, and then heated so that the nanowires 710, 720 are respectively bonded to the corresponding contacts 818, 819 of the redistribution layer 810. Since the nanowires 710 and 720 are used for bonding, there are a plurality of nanowires 710 for bonding with a corresponding one of the contacts 818 of the redistribution layer 810, and a plurality of nanowires 720 for bonding with a corresponding one of the contacts 819, so that only a portion (but not all) of the nanowires 710 and 720 are bonded to the corresponding contacts 818 and 819, an electrical connection can be achieved, thereby reducing the requirement for alignment accuracy. In addition, since the wire diameter of the redistribution line 814 for supplying power in the redistribution layer 810 is large, power loss can be reduced by employing the nanowires 710, 720 to bond with the redistribution layer 810.

Referring again to fig. 2A, the electronic device 1000 further includes a second chip 200 supported by the substrate 500, the second chip 200 being adjacent to the lateral first chip 100. The electronic device 1000 further comprises a first circuit structure 910, the first circuit structure 910 being operable to bridge the first chip 100 and the second chip 200. The first chip 100 and the second chip 200 may be connected to the first circuit structure 910 by respective connectors 105, 205. The connectors 105, 205 may for example comprise copper bumps or tin solder balls or the like.

The underfill 740 fills between the first circuit structure 910 and the first chip 100, between the first circuit structure 910 and the second chip 200, and between the first chip 100 and the second chip 200. The underfill 740 may encapsulate each of the connectors 105, 205. The first chip 100, the second chip 200, and the underfill 740 on the first circuit structure 910 are encapsulated by the molding compound 750. The first circuit structure 910 and the substrate 500 are connected to each other through the connection member 209. The connection 209 may, for example, comprise a copper bump or a tin solder ball, etc. The space between the first circuit structure 910 and the substrate 500 is filled with the underfill 730 to encapsulate the respective connectors 209 and the lower portion of the molding compound 750.

The first circuit structure 910 may electrically connect the substrate 500 with the first chip 100 and the second chip 200 for signal transmission. As shown in fig. 2B, the first signal path Ls1 of the first chip 100 is formed via the first circuit structure 910 and the second region 520 of the substrate 500, the second signal path Ls2 of the second chip 200 is formed via the first circuit structure 910 and the second region 520 of the substrate 500, and the signal bridge path Ls3 between the first chip 100 and the second chip 200 is formed via the first circuit structure 910.

By configuring the first power supply path L1 from the first region 510 of the substrate 500 into the upper surface of the first chip 100 and configuring the first signal path Ls1, the second signal path Ls2 and/or the signal bridge path Ls3 between the lower surface of the first chip 100 and the second region 520 of the substrate 500, only the signal lines need to be laid out in the first circuit structure 910, which avoids the problems of parasitic capacitance, interference and wiring between the power lines and the signal lines in the first circuit structure 910, and can allow the number of layers of the first circuit structure 910 to be reduced. For example, the number of layers of the first circuit structure 910 may be reduced to 3 dielectric layers and 3 metal wiring layers. By reducing the number of layers of the first circuit structure 910, warpage problems can be further reduced.

Referring to fig. 2A, the electronic device 1000 may further include a second circuit structure 920, and the second circuit structure 920 is disposed between the heat sink 400 and the first chip 100, and between the heat sink 400 and the second chip 200. In some embodiments, the second circuit structure 920 extends over the outer edges of the first chip 100 and the second chip 200. The second circuit structure 920 is configured to distribute the power provided by the power conditioner 310 to the first chip 100 and the second chip 200, so that the second chip 200 can also receive the power provided by the heat sink 400. In addition, referring again to fig. 3D, the lower surface of the power conditioner 310 may be an active surface. And the lower surface of the power conditioner 310 may be connected to the second circuit structure 920 through a connection 319. The connector 319 may include copper bumps or solder balls, etc.

Referring to fig. 2B, a second power supply path L2 for the second chip 200 is formed through the second circuit structure 920, and the second power supply path L2 includes a second power path Lp2 and a second ground path Lg2. It should be understood that the second power path Lp2 for the second chip 200 shown in fig. 2B is only a part, the second power path Lp2 before reaching the upper surface of the second chip 200 is similar to the first power path Lp1, and is not shown for clarity of illustration. After the second power path Lp2 reaches the upper surface of the second chip, it reaches the lower surface of the second chip 200 through the corresponding second TSV 212 in the second chip 200 to drive the second chip 200. Similarly, the second ground path Lg2 of the second chip 200 reaches the upper surface of the second chip 200 via the corresponding second TSV 212, and then reaches the substrate 500 in a path similar to the first ground path Lg1 to be grounded.

Fig. 3E is a schematic top view of the electronic device of fig. 2A with the heat sink 400 omitted. It should be appreciated that for clarity of illustration, the heat sink 400 is not shown in fig. 3E. As shown in fig. 2A and 3E, the substrate 500 has a first region 510 and a second region 520 disposed adjacent to the first region 510. The first region 510 of the substrate 500 may have a power contact region 508 and a ground contact region 509 therein. The power contact region 508 and the ground contact region 509 are respectively bonded to corresponding contacts 818 (see fig. 3B and 3C) of the redistribution layer 810 by nanowires 710. An adhesive layer 480 is provided along the periphery of the substrate 500 for attachment with the heat sink 400. The second circuit structure 920 covers the outer edges of the first chip 100 and the second chip 200 and extends in a closed loop shape. In fig. 3E, the first chip 100 and the second chip 200 are shown in dotted lines, as they are covered by the second circuit structure 920. The second circuit structure 920 also extends below each passive element assembly 320, so that the passive element assemblies 320 can be connected to the first chip 100 and the second chip 200 through the second circuit structure 920.

The heat conductive layer 600 is disposed on: in a region surrounded by the second circuit structure 920 and where the second circuit structure 920 is not disposed. In addition, the thermally conductive layer 600 may also be disposed on a portion of the power conditioner 310. In some embodiments, the forming of the thermally conductive layer 600 surrounded by the second circuit structure 920 includes: on the surfaces of the molding compound 750, the first chip 100, the second chip 200, and the underfill 740 (see fig. 2A), the second circuit structure 920 is formed first, and then a thermally conductive material is filled in a region surrounded by the second circuit structure 920 to form the thermally conductive layer 600. In some embodiments, the process of forming the thermally conductive layer 600 includes: the region surrounding the second circuit structure 920 is first dispensed by a dispenser to define a boundary of the region where the heat conductive layer 600 is to be formed, and then the heat conductive material is filled into the boundary of the dispensing to form the heat conductive layer 600. By first dispensing to form the boundary, the thermally conductive layer 600 may be prevented from overflowing onto the second circuit structure 920 during formation. And, the patterned heat conductive layer 600 is disposed on the first chip 100, the second chip 200 and a portion of the power conditioner 310 avoiding the second circuit structure 920, so that the heat sink 400 can have the functions of providing power and dissipating heat at the same time.

Fig. 4A is a schematic cross-sectional structure of an electronic device 2000 according to another embodiment of the present application. Fig. 4B is a schematic plan view corresponding to the electronic device 2000 in fig. 4A, with the heat sink 400 omitted, and for clarity of illustration, the heat sink 400 is not shown in fig. 4B. The electronic device 2000 illustrated in fig. 4A and 4B may be similar or identical in many respects to the electronic device 1000 described with reference to fig. 2A-3E and may have the benefits described above with reference to fig. 2A-3E. To avoid repetition, only the differences of the electronic device 2000 are described below.

Referring to fig. 4A and 4B, the substrate 500 is connected to the second circuit structure 920 through a wire 850. The first partial bottom surface 400b1 of the heat sink 400 extends laterally over the power conditioner 310 and the passive element assembly 320 without the above-described protrusions 430. The entire upper surface of the power conditioner 310 is in contact with the heat conductive layer 600 and is connected to the heat sink 400 through the heat conductive layer 600. The heat sink 400 is attached to the substrate 500 through the adhesive layer 480.

In the present embodiment, the power path Lp' of the first chip 100 extends from the substrate 500 to the second circuit structure 920 via the wire 850, and then enters the power regulator 310, and after the power regulator 310 regulates the power, the power is distributed to the upper surface of the first chip 100 via the second circuit structure 920, and reaches the lower surface of the first chip 100 via the corresponding first TSV 112, so as to drive the first chip 100. Accordingly, the ground path Lg' of the first chip 100 is grounded through the corresponding first TSV 112 to the upper surface of the first chip 100, and then through the second circuit structure 920, the power conditioner 310, and the wire 850 to the substrate 500.

In fig. 4A, wire bond 850 is exposed. In other embodiments, the wire 850 may be encapsulated by a gel to protect the wire 850. In such an embodiment, the gel may not completely fill the space defined by the heat sink 400, but may cover only the wire 850.

Fig. 4C is a partially enlarged schematic view at the power conditioner 310 in fig. 4A. Referring to fig. 4C, the lower surface of the power conditioner 310 may be an active surface and connected to the second circuit structure 920 through a connection 319'. The connector 319' may include copper bumps, solder balls, and the like. In some embodiments, an underfill may be formed between the power conditioner 310 and the second circuit structure 920. The upper surface of the power conditioner 310 does not need to be provided with the above-described wiring layer 330, and in the present embodiment, the power conditioner 310 does not have the above-described TSV.

Embodiments of the present application also provide methods of forming electronic devices. Fig. 5A to 9A are schematic cross-sectional structures at a plurality of stages of forming the electronic device 1000 shown in fig. 2A, and fig. 5B to 9B are schematic top views at a plurality of stages of forming the electronic device 1000 shown in fig. 2A.

As shown with reference to fig. 5A and 5B, a substrate 500 is provided. The substrate 500 includes a first region 510 and a second region 520 adjacent to the first region 510. The first chip 100 and the second chip 200 are disposed on the substrate 500, and the first circuit structure 910 bridges the first chip 100 and the second chip 200. The space between the first circuit structure 910 and the substrate 500 is filled with an underfill 730. The underfill 740 fills between the first circuit structure 910 and the first chip 100, between the first circuit structure 910 and the second chip 200, and between the first chip 100 and the second chip 200. The first chip 100, the second chip 200, and the underfill 740 on the first circuit structure 910 are encapsulated by the molding compound 750. The first region 510 of the substrate 500 has nanowires 710 on a surface thereof. Nanowires 710 for a power path (e.g., first power path Lp1 in fig. 2B) may be disposed at the power contact region 508, and nanowires 710 for a ground path (e.g., first ground path Lg1 in fig. 2B) may be disposed at the ground contact region 509.

Then, referring to fig. 6A and 6B, a second circuit structure 920 is formed on the surfaces of the molding compound 750, the first chip 100, the second chip 200, and the underfill 740. In some embodiments, the second circuit structure 920 may cover the molding compound 750 and may cover peripheral areas of the first chip 100 and the second chip 200, at which time the second circuit structure 920 may cover a portion of the underfill 740 that is located at the periphery and fills between the first chip 100 and the second chip 200.

Referring to fig. 7A and 7B, the power conditioner 310 and the passive element assembly 320 are formed on the second circuit structure 920 on the first chip 100. A wiring layer 330 may be disposed at an upper surface of the power conditioner 310, and nanowires 720 are disposed on the wiring layer 330.

Referring to fig. 8A and 8B, a heat conductive layer 600 is formed over the power conditioner 310, and the heat conductive layer 600 is formed in a region where the second circuit structure 920 is not formed over the first and second chips 100 and 200. In some embodiments, the region surrounding the second circuit structure 920 is first dispensed with glue, so as to define a boundary of the region where the heat conductive layer 600 is to be formed, and then the heat conductive material is filled into the boundary of the dispensed glue to form the heat conductive layer 600.

Then, referring to fig. 9A and 9B, the heat sink 400 with the redistribution layer 810 is bonded on the substrate 500. Wherein the redistribution layer 810 is bonded to the nanowires 710, 720, respectively, and the heat spreader 400 is connected to the power conditioner 310, the first chip 100, and the second chip 200 through the thermally conductive layer 600, resulting in the electronic device 1000. Wherein for clarity of illustration, the heat sink 400 is shown in the top view of fig. 9B only at the location where the heat sink 400 is joined to the thermally conductive layer 600 and the substrate 500.

Fig. 10A to 14A are schematic cross-sectional structures at various stages of forming the electronic device 2000 shown in fig. 4A, and fig. 10B to 14B are schematic top views at various stages of forming the electronic device 1000 shown in fig. 4A.

As shown with reference to fig. 10A and 10B, a substrate 500 is provided. The substrate 500 includes a first region 510 and a second region 520 adjacent to the first region 510. The first chip 100 and the second chip 200 are disposed on the substrate 500, and the first circuit structure 910 bridges the first chip 100 and the second chip 200. The space between the first circuit structure 910 and the substrate 500 is filled with an underfill 730. The underfill 740 fills between the first circuit structure 910 and the first chip 100, between the first circuit structure 910 and the second chip 200, and between the first chip 100 and the second chip 200. The first chip 100, the second chip 200, and the underfill 740 on the first circuit structure 910 are encapsulated by the molding compound 750.

Then, referring to fig. 11A and 11B, a second circuit structure 920 is formed on the surfaces of the molding compound 750, the first chip 100, the second chip 200, and the underfill 740. In some embodiments, the second circuit structure 920 may cover the molding compound 750, and may cover peripheral areas of the first chip 100 and the second chip 200. Subsequently, a wire 850 connecting the substrate 500 and the second circuit structure 920 is formed. A wire 850 for a power path (e.g., power path Lp 'in fig. 4A) may be connected to the power contact region 508, and a wire 850 for a ground path (e.g., ground path Lg' in fig. 4A) may be connected to the ground contact region 509.

Referring to fig. 12A and 12B, a power conditioner 310 and a passive element assembly 320 are formed on a second circuit structure 920 on the first chip 100. Referring to fig. 13A and 13B, a heat conductive layer 600 is formed over the power conditioner 310, and the heat conductive layer 600 is formed in a region where the second circuit structure 920 is not formed over the first chip 100 and the second chip 200. In some embodiments, the region surrounding the second circuit structure 920 is first dispensed with glue, so as to define a boundary of the region where the heat conductive layer 600 is to be formed, and then the heat conductive material is filled into the boundary of the dispensed glue to form the heat conductive layer 600.

Then, referring to fig. 14A and 14B, the heat sink 400 is bonded to the substrate 500. Wherein the heat sink 400 is connected to the power conditioner 310, the first chip 100 and the second chip 200 through the heat conductive layer 600, thereby obtaining the electronic device 2000. Wherein for clarity of illustration, the heat sink 400 is shown in the top view of fig. 14B only at the location where the heat sink 400 is joined to the thermally conductive layer 600 and the substrate 500.

The foregoing description of the preferred embodiments of the present application is not intended to be limiting, but rather is intended to cover any and all modifications, equivalents, alternatives, and improvements within the spirit and principles of the present application.

Claims (10)

1. An electronic device, comprising:

a first chip;

a power conditioner arranged above the first chip;

the heat dissipation piece is used for providing power for the first chip, wherein the heat dissipation piece is provided with a space for accommodating the power regulator.

2. The electronic device of claim 1, wherein the heat sink provides power to the first chip through the power conditioner.

3. The electronic device of claim 1, wherein the heat sink has a bottom surface adjacent the power conditioner and the first chip, the bottom surface having redistribution lines disposed thereat to provide a line for transferring power to ground.

4. The electronic device of claim 3, further comprising a substrate supporting the heat sink and the first chip, wherein the substrate is electrically connected to the first chip through the redistribution line at the bottom surface of the heat sink.

5. The electronic device of claim 4, wherein the substrate is connected to the heat sink via nanowires.

6. The electronic device of claim 4, wherein the substrate has a first region adjacent an edge of the substrate and a second region disposed adjacent the first region, wherein power provided to the first chip is from the first region.

7. The electronic device of claim 6, wherein the active surface of the first chip is disposed opposite the second region and in signal communication with the second region.

8. An electronic device according to claim 3, characterized in that an insulating layer is arranged between the redistribution line and the heat sink.

9. The electronic device of claim 1, further comprising a second chip adjacent to the first chip and configured to receive power from the heat sink.

10. The electronic device of claim 1, wherein the power conditioner is connected to the heat sink through nanowires.