JPH0479262A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0479262A JPH0479262A JP2192726A JP19272690A JPH0479262A JP H0479262 A JPH0479262 A JP H0479262A JP 2192726 A JP2192726 A JP 2192726A JP 19272690 A JP19272690 A JP 19272690A JP H0479262 A JPH0479262 A JP H0479262A
- Authority
- JP
- Japan
- Prior art keywords
- lead wiring
- signal
- semiconductor device
- terminal
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 claims 1
- 239000004020 conductor Substances 0.000 claims 1
- 239000011521 glass Substances 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 230000008878 coupling Effects 0.000 description 8
- 238000010168 coupling process Methods 0.000 description 8
- 238000005859 coupling reaction Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 4
- 230000001939 inductive effect Effects 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- 230000001934 delay Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に係り、特にそのパッケージの構造
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a package thereof.
従来の半導体装置の構成をデュアル・インライン・パッ
ケージを使用した半導体装置を例として、第３図（Ａ）
および第３図（Ｅ）の平面図、側面図に示して説明する
。Figure 3 (A) shows the configuration of a conventional semiconductor device using a dual inline package as an example.
The explanation will be given with reference to the plan view and side view of FIG. 3(E).
アイランド部１１にチップ１２がマウントされており、
チップ内のパッドとリード配線１４の端部とはボンディ
ング線１３により接続されパッケージのリード配線１４
から外部ピンへと導かれる構成となっていた。A chip 12 is mounted on the island portion 11,
The pads inside the chip and the ends of the lead wires 14 are connected by bonding wires 13, and the lead wires 14 of the package are connected to each other by bonding wires 13.
The configuration was such that it was guided from the terminal to an external pin.
しかし、前述の従来技術では、リード配線が持つ寄生イ
ンダクタンスにより、近傍のリード配線や電子回路装置
配線に銹導結合によるノイズを与え半導体集積回路素子
の誤動作や速度の遅れが生じることがある。また、リー
ド配線と近傍のリード配線および電子回路装置配線との
間に生じる静電容量による静電結合によりノイズを与え
半導体集積回路素子の誤動作や速度の遅れが生じること
がある。However, in the above-mentioned conventional technology, the parasitic inductance of the lead wires may cause noise due to conductive coupling to the nearby lead wires or electronic circuit device wires, causing malfunctions or speed delays in the semiconductor integrated circuit elements. In addition, electrostatic coupling due to capacitance generated between the lead wiring and nearby lead wiring and electronic circuit device wiring may cause noise, which may cause malfunction or speed delay of the semiconductor integrated circuit element.
さらに、近傍の電子回路装置配線との間で生じる誘導結
合や静電結合により、半導体装置のリド配線にノイズを
受は半導体集積回路素子の誤動作や速度の遅れが生じる
ことがあるという問題点を有していた。Furthermore, due to inductive coupling and capacitive coupling that occur with nearby electronic circuit device wiring, noise in the lead wires of semiconductor devices can cause malfunctions and speed delays in semiconductor integrated circuit elements. had.
そこで本発明は、このような問題点を解決するもので、
その目的とするところは、ノイズを出しにくく、ノイズ
を受けにくい半導体装置を提供することにある。Therefore, the present invention aims to solve these problems.
The purpose is to provide a semiconductor device that is less likely to generate noise and less susceptible to noise.
本発明の半導体装置は、半導体素子が載置されたアイラ
ンドと、前記アイランド周囲からパッケージの外部へ向
かって延在する複数のリード配線と、前記半導体素子の
パッドと前記リード配線の端部とを接続するための金属
細線を具備し、前記リード配線の外部ピンを残してケー
スされた横道を有する半導体装置において、前記リード
配線のうち信号用のリード配線の両側面に電源電位また
は接地電位を持つリード配線を配置したことを特徴とす
る。The semiconductor device of the present invention includes an island on which a semiconductor element is mounted, a plurality of lead wires extending from the periphery of the island toward the outside of the package, and a pad of the semiconductor element and an end of the lead wire. In a semiconductor device comprising a thin metal wire for connection and having a side path encased leaving an external pin of the lead wiring, a signal lead wiring among the lead wirings has a power supply potential or a ground potential on both sides. It is characterized by the arrangement of lead wiring.
本発明の上記の構成によれば、信号用リード配線と近傍
の電子回路装置配線との間で発生する誘導結合によるノ
イズは、信号用リード配線の両側面に配置した電源電位
または接地電位を持つリード配線の中にノイズを導入し
、反抗電流と反抗磁束とを生じさせて、ノイズの作用を
打ち消すための電磁遮蔽となる。According to the above configuration of the present invention, noise due to inductive coupling generated between the signal lead wiring and the nearby electronic circuit device wiring is suppressed by the power supply potential or the ground potential placed on both sides of the signal lead wiring. Noise is introduced into the lead wiring to generate a countercurrent and countermagnetic flux, which acts as an electromagnetic shield to cancel the effect of the noise.
また、信号用リード配線と近傍の電子回路装置配線との
間で発生する静電結合によるノイズは、信号用リード配
線の両側面に配置した電源電位または接地電位を持つリ
ード配線により信号用リード配線とグランド間のインピ
ーダンスを低くし、雑音電圧を減少させるための静電遮
蔽となる。In addition, noise due to capacitive coupling that occurs between the signal lead wiring and nearby electronic circuit device wiring can be eliminated by connecting the signal lead wiring with lead wiring that has a power supply potential or ground potential placed on both sides of the signal lead wiring. It serves as an electrostatic shield to lower the impedance between the ground and the ground, reducing noise voltage.
以下に本発明の実施例を図面に基づき半導体装置のパッ
ケージを例に詳細に説明する。Embodiments of the present invention will be described in detail below with reference to the drawings, taking a semiconductor device package as an example.
（Ａ）第１実施例
第１図には第１実施例に係る、半導体装置のパッケージ
の平面図が示されている。(A) First Embodiment FIG. 1 shows a plan view of a package for a semiconductor device according to a first embodiment.
図中３は入力または出力の信号を外部に導くための信号
端子（信号用外部ピン）、ｌは電源端子（電源用外部ピ
ン）、２はＧＮＤ端子（ＧＮＤ用外郊外部ピンあり、そ
の他の端子は外部との接続を必要としない非接続端子（
非接続外部ピン）４であり、２つのＧＮＤ端子２のリー
ド配線１４が信号端子３のリード配線１４の両側面を蔽
うように配置しており、この２つのＧＮＤ端子２のリー
ド配線１４が電磁遮蔽、静電遮蔽となり、ノイズを出し
にくく、ノイズを受けにくくする。In the figure, 3 is a signal terminal (external signal pin) for guiding input or output signals to the outside, l is a power supply terminal (external pin for power supply), and 2 is a GND terminal (there is an external pin for GND, other The terminal is a non-connection terminal (
The lead wires 14 of the two GND terminals 2 are arranged so as to cover both sides of the lead wires 14 of the signal terminal 3, and the lead wires 14 of the two GND terminals 2 are It acts as a shield or electrostatic shield, making it difficult to emit noise or receive noise.
（Ｅ）第２実施例
第２図には第２実施例に係る、半導体装置のパッケージ
の平面図が示されている。(E) Second Embodiment FIG. 2 shows a plan view of a package for a semiconductor device according to a second embodiment.
この例では、アイランド部１１とＧＮＤ端子２のリード
配線１４とを一体にし、更に、各々の信号端子３のリー
ド配線１４をＧＮＤ端子２または１［Ｅ源端子１のリー
ド配線１４が蔽うように配置している。この第２実施例
の作用は第１実施例と同一であり、多くの信号端子を持
つ半導体装置に効果がある。In this example, the island portion 11 and the lead wire 14 of the GND terminal 2 are integrated, and the lead wire 14 of each signal terminal 3 is further connected to the GND terminal 2 or 1 so that the lead wire 14 of the E source terminal 1 covers it. It is placed. The operation of this second embodiment is the same as that of the first embodiment, and is effective for semiconductor devices having many signal terminals.
以上述べたように本発明によれば、誘導結合、容量結合
によるノイズを遮蔽できるので、ノイズを出しにくく、
ノイズを受けにくいという優れた効果を奏する。As described above, according to the present invention, noise due to inductive coupling and capacitive coupling can be shielded, making it difficult to generate noise.
It has the excellent effect of being less susceptible to noise.
第１図は本発明の第１実施例の半導体装置の平面図、第
２図は本発明の第２実施例の半導体装置の平面図、第３
図（Ａ）、 （Ｂ）は各々従来の半導体装置の平面図
および側面図である。
図中
１・・・電源端、子（電源用外部ピン）２・・・ＧＮＤ
端子（ＧＮＤ用外郊外部ビ３・・・信号端子（信号用外
部ピン）
４・・・非接続端子（非接続外部ピン）１１・・・アイ
ランド部
１２・・・搭載チップ
１３・・・チップのパッドとリード配線端とを結ぶボン
ディング線
１４・・・パッケージのリード配線（内部配線）以
上
出願人 セイコーエプソン株式会社
代理人 弁理士 鈴木 喜三部 他１名第１図
第ａ図＋Ａ）
第 ８ 図（Ｂ）FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a plan view of a semiconductor device according to a second embodiment of the present invention, and FIG.
Figures (A) and (B) are a plan view and a side view, respectively, of a conventional semiconductor device. In the diagram 1...Power terminal, child (external pin for power supply) 2...GND
Terminals (GND outer suburbs) 3...Signal terminals (signal external pins) 4...Non-connection terminals (non-connection external pins) 11...Island portion 12...Mounted chip 13...Chip Bonding wire 14 connecting the pad and the end of the lead wiring...The lead wiring (internal wiring) of the package
Applicant Seiko Epson Co., Ltd. Agent Patent attorney Kizobe Suzuki and 1 other person Figure 1 Figure a + A) Figure 8 (B)
Claims (1)
ンド周囲からパッケージの外部へ向かって延在する複数
のリード配線と、前記半導体素子のパッドと前記リード
配線の端部とを接続するための金属細線を具備し、前記
リード配線の外部ピンを残してケースされた構造を有す
る半導体装置において、前記リード配線のうち信号用の
リード配線の両側面に電源電位または接地電位を持つリ
ード配線を配置したことを特徴とする半導体装置。 ２、前記リード配線の部材が金属板、厚膜導体のいずれ
かであることを特徴とする請求項１記載の半導体装置。 ３、前記ケースの部材がセラミック、モールド樹脂、ガ
ラスのいずれかであることを特徴とする請求項１記載の
半導体装置。[Claims] 1. An island on which a semiconductor element is mounted, a plurality of lead wires extending from the periphery of the island toward the outside of the package, a pad of the semiconductor element, and an end of the lead wire. In a semiconductor device having a structure in which the external pins of the lead wiring are left and the lead wiring is cased, a power supply potential or a ground potential is applied to both sides of the signal lead wiring among the lead wiring. A semiconductor device characterized by having lead wiring arranged therein. 2. The semiconductor device according to claim 1, wherein the lead wiring member is either a metal plate or a thick film conductor. 3. The semiconductor device according to claim 1, wherein the member of the case is made of ceramic, molded resin, or glass.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2192726A JPH0479262A (en) | 1990-07-20 | 1990-07-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2192726A JPH0479262A (en) | 1990-07-20 | 1990-07-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0479262A true JPH0479262A (en) | 1992-03-12 |
Family
ID=16296047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2192726A Pending JPH0479262A (en) | 1990-07-20 | 1990-07-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0479262A (en) |
-
1990
- 1990-07-20 JP JP2192726A patent/JPH0479262A/en active Pending
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