JPH0793968A - Ferroelectric memory device - Google Patents

Abstract

PURPOSE:To nondestructively read out stored information and to make the life of the title memory device long by a method wherein, in a simple matrix memory structure, a readout pulse width or an amplitude or both of them are made variable in a readout operation. CONSTITUTION:A defect density N is investigated in advance as a degradation degree due to fatigue based on the count (n) of writing to a ferroelectric capacitor 1, and its relationship with a corresponding nondestructive readout critical pulse width (t*) is investigated. In addition, the pulse width (t*) is shorter than a switching time tsw. A write circuit 3 and a readout circuit 4 in which a readout pulse width can be made variable are connected to a changeover circuit 2 which is connected across both ends of the capacitor 1. A controller 5 whose readout pulse width is made variable by the counter of count (n) and by the table of n-t* is connected to the circuits 3, 4. Thereby, the count (n) is counted, and the readout pulse width is controlled optimally so as to correspond to it. In addition, since the pulse width (t*) depends on a pulse amplitude, the pulse width many be controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device using a ferroelectric material as an information recording medium.

[0002]

2. Description of the Related Art Generally, it is known that a ferroelectric material has a hysteresis characteristic and data can be stored as a non-volatile memory by utilizing this characteristic. There are roughly two types of device structures for ferroelectric memories. One is a simple matrix structure in which the crossing points of the orthogonal stripe electrodes attached to the front and back of the thin film form one memory cell, and the structure is complicated and there is a limit to high density. Conventionally, in the reading method of these memories, destructive reading utilizing a polarization reversal current which requires rewriting of a selected cell is performed.

On the other hand, Japanese Patent Application Laid-Open No. 2-1543 by the present applicant
In Japanese Patent Publication No. 89, a self-reversal phenomenon of a ferroelectric thin film itself in a simple matrix memory structure (here, a phenomenon of returning to an initial polarization state when an external pulse is applied is called).
There is proposed a ferroelectric memory capable of writing and reading while suppressing the influence of non-selected cells by writing and reading with low impedance.

[0004]

However, there are the following problems in the reading and writing of the above-mentioned conventional ferroelectric memory. First, in the destructive read method, the reversal of polarization is repeated, so that the deterioration of the ferroelectric property reduces the residual polarization, making it difficult to extend the life of the memory.
Not only the problem of fatigue but also rewriting by a complicated circuit is necessary.

Second, in Japanese Patent Laid-Open No. 2-154389, writing in a simple matrix memory,
Although it has a high possibility of being realized as a reading method, a specific mechanism and device structure for realizing the self-reversal phenomenon of spontaneous polarization have not been presented. Therefore, according to the present invention, the information to be stored can be read nondestructively,
An object of the present invention is to provide a ferroelectric memory which has a long life and is suitable for integration.

[0006]

In order to achieve the above-mentioned object, the present invention comprises a first conductive film formed on a substrate.
A ferroelectric memory device comprising: an electrode; a ferroelectric film formed on the first electrode for writing information; and a second electrode composed of a conductive film formed on the ferroelectric film, Provided is a ferroelectric memory device having either a means for varying a read pulse width, a means for varying a read amplitude, or a means for varying both a read pulse width and an amplitude when reading information from a ferroelectric film. .

[0007]

In the ferroelectric memory configured as described above, the number of times of writing n is counted, and the read pulse width t ^* corresponding to it is controlled to optimize the read pulse width. In addition, it is possible to associate the defect density with the DC resistance measurement, the capacitance measurement, or the pyrocurrent measurement, and the optimum read pulse width t ^* is set. In addition, the pulse amplitude is reduced without reducing the read pulse width t ^*, and the defect density due to fatigue due to memory writing or the like is reduced.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. First, a phenomenological theoretical analysis method for the ferroelectric memory device of the present invention will be described. For example,
Consider a two-dimensional lattice model in which M and N atoms are arranged. Here, if the dipole moment p _{m, n} of the (m, n) th atom is set and the strength of the external electric field is set to e, the total free energy f
Is

[0009]

[Equation 1] Considered in. κ ₁ , κ ₂ , and κ ₃ are interaction coefficients between dipoles, α is a temperature function, and α = a (T−T ₀ ) (where a>
0 and T ₀ are Curie temperatures). Since the ferroelectric phase is taken into consideration here, α <0 and β> 0.

Next, in the polarization reversal of the ferroelectric substance, it is necessary to consider the viscosity of each dipole moment which causes a delay in its movement. The formula considering viscosity with respect to the time change of dipole moment is

[0011]

[Equation 2] Becomes γ indicates a viscosity coefficient. The switching response of the pulsed electric field can be simulated by substituting the equation (1) into the equation (2) and obtaining the solution. The polarization P = Σp _{m, n} can be obtained by obtaining the solution of M × N dipole moments at each time. The current response may be calculated by i = d / dt (P).

Next, FIG. 1 shows and describes a ferroelectric memory device as a first embodiment according to the present invention. Figure 1 (a)
FIG. 1B shows a configuration example for driving the ferroelectric memory device of the first embodiment to perform writing and reading, and FIG.
Shows the simulation result by the configuration. Here, it is assumed that the defect density is examined in advance as the degradation degree of the fatigue depending on the number of times of writing to the ferroelectric capacitor 1 and the relation of the nondestructive read pulse width t ^* corresponding thereto is examined.

In this ferroelectric memory device, a switching circuit 2 is connected to both ends of a ferroelectric capacitor 1 for storing data. A write circuit 3 and a read circuit 4 whose read pulse amplitude is variable are connected to the switching circuit 2. The write circuit 3 and the read circuit 4 are connected to a counter for the number of times of writing n and a controller 5 for varying the read pulse amplitude based on a table of n−t ^* .
Here, t _max is the time when the polarization reversal current becomes maximum, t _sw is the time until the peak of the polarization reversal current becomes 1/10, and t _sw
^* Is defined as the critical pulse width that returns to the initial polarization state when a read pulse is applied.

Next, FIG. 1B shows the switching time t _sw for the ferroelectric memory device having the above-mentioned structure.
The simulation result of the dependency of the defect density N on the critical pulse width t ^{* which} is shorter and can be read nondestructively is shown.

It is generally considered that the cause of the fatigue of the ferroelectric memory is that the defect layer between the electrode and the ferroelectric substance increases with the application of an external electric field. That is, from the result shown in FIG. 1B, the read pulse width t ^* needs to be reduced because the defect layer increases as the number of polarization inversions such as writing increases.

In the ferroelectric memory device configured as described above, the number of times of writing n is counted and the read pulse width t ^* corresponding thereto is controlled, thereby optimizing the read pulse width and the number of nondestructive read times. Does not deteriorate.

Next, FIG. 2 shows and describes a ferroelectric memory device as a second embodiment according to the present invention. Figure 2 (a)
FIG. 8 shows a configuration for driving the ferroelectric memory device of the second embodiment for writing and reading, and FIG. 9B shows a simulation result by the configuration.

In this ferroelectric memory device, both ends of the ferroelectric capacitor 11 for storing data are
The switching circuit 12 is connected. A write circuit 13 and a read circuit 14 having a variable read pulse amplitude are connected to the switching circuit 12. The write circuit 13 and the read circuit 14 include a controller 1 for varying a read pulse amplitude based on a counter for writing times n and a table for n-t ^*.
5 is connected.

In this ferroelectric memory device, the read pulse amplitude of the read circuit 14 can be changed as a countermeasure against the critical pulse width t ^* of nondestructive read in response to a fatig caused by writing of a memory cell or the like.

In such a ferroelectric memory device,
From the simulation result shown in FIG. 2A, the critical pulse width t ^{* for} nondestructive read depends on the pulse amplitude, and becomes larger as the pulse amplitude becomes smaller at the same defect density. Therefore, as a measure to increase the defect density due to the fatigue caused by writing to the memory, the read pulse width t ^{* is set.}
It can be seen that the pulse amplitude can be reduced without decreasing. As a result, the number of nondestructive readings can be prevented from deteriorating.

Next, FIG. 3 shows and describes a ferroelectric memory device as a third embodiment according to the present invention. This ferroelectric memory device has a write / read control circuit 21 for controlling the whole, a ferroelectric capacitor 22 for storing data, and the write / read control circuit connected to both ends of the ferroelectric capacitor 22. A switching circuit 23 whose switching operation is controlled by 21, a linear capacitance measuring circuit 24 for measuring the linear capacitance of the ferroelectric capacitor 22 connected to the switching circuit 23, and a read pulse suitable based on the result of the measuring circuit 24. And a write pulse generator 26 that generates a write pulse.

In the ferroelectric memory device having such a configuration, the ferroelectric capacitor 22 and the linear capacitance measuring circuit 24 are connected via the switching circuit 23 by the read control signal from the control circuit 21. The linear capacitance measuring circuit 24 measures by a minute electric field that does not destroy the information stored in the ferroelectric capacitor 22. From the result, the optimum read pulse is generated in the read pulse generator 25.

At this time, the switching circuit 23 is controlled by the control circuit 21 by the read pulse generator 25 and the ferroelectric capacitor 22.
Is controlled to connect. Therefore, the relationship between the number of repetitions of polarization reversal due to the writing of information in the ferroelectric capacitor 22 and the linear capacitance (capacity in the vicinity of 0 V DC bias) is investigated in advance. It has been experimentally confirmed that this linear capacity decreases as the number of writing increases when a PZT film formed by the sol-gel method is used. Therefore, by measuring the capacitance, the defect density can be associated, that is, the optimum read pulse width t ^* can be set.

Next, FIG. 4 shows and describes a ferroelectric memory device as a fourth embodiment according to the present invention. In this ferroelectric memory device, a control circuit 31 for controlling the whole, a ferroelectric capacitor 32 for storing data, and a ferroelectric capacitor 32 connected to both ends of the ferroelectric capacitor 32 to control the switching operation to the control circuit 31. Switching circuit 33, a DC resistance measuring circuit 34 for measuring the DC resistance of the ferroelectric capacitor 32 connected to the switching circuit 33, and a reading for generating a suitable read pulse based on the result of the DC resistance measuring circuit 34. It is composed of a pulse generator 35 and a write pulse generator 36 that generates a write pulse.

In the ferroelectric memory device configured as described above, information is first written in the ferroelectric capacitor 32 via the write pulse generator 36 in accordance with a command from the control circuit 31.

Next, the read signal of the control circuit 31 connects the ferroelectric capacitor 32 and the DC resistance measuring circuit 34 via the switching circuit 33. This DC resistance measuring circuit 34
Is measured by a minute electric field that does not destroy the information in the ferroelectric capacitor 32. Based on the result, an optimum read pulse is generated in the read pulse generator 35. At that time, the switching circuit 33 is controlled by the control circuit 31 so as to connect the read pulse generator 35 and the ferroelectric capacitor 32.

Therefore, the relationship between the number of repetitions of polarization reversal due to writing to the ferroelectric capacitor 32 and the direct current resistance of the ferroelectric capacitor is investigated in advance. It has been experimentally confirmed that this DC resistance decreases as the number of times of writing increases when a PZT film formed by the sol-gel method is used. Therefore, by measuring the DC resistance, the defect density can be associated, that is, the optimum read pulse width t ^* can be set.

Next, FIG. 5 shows a ferroelectric memory device as a fifth embodiment according to the present invention and will be described. In this ferroelectric memory device, a control circuit 41 for controlling the whole, a ferroelectric capacitor 42 for storing data, and a switching operation to the control circuit 41 by connecting both ends of the ferroelectric capacitor 42. And a switching circuit 43 controlled by the switching circuit, a pyroelectric current measuring circuit 44 for measuring the pyroelectric current of the ferroelectric capacitor 42 connected to the switching circuit 43, and a reading for generating a suitable read pulse based on the result of the measuring circuit 44. It is composed of a pulse generator 45 and a write pulse generator 46 that generates a write pulse.

In the ferroelectric memory device having such a structure, the relationship between the number of repetitions of polarization reversal due to writing to the ferroelectric capacitor and the pyroelectric current is examined in advance. First, according to a command from the control circuit 41, information is written in the ferroelectric capacitor 42 via the write pulse generator 46.

Next, the ferroelectric capacitor 42 and the pyroelectric current measuring circuit 44 are connected via the switching circuit 43 by the read signal of the control circuit 41. The pyroelectric current measuring circuit 44 measures by a minute electric field which does not destroy the information of the ferroelectric capacitor 42. Based on the result, the read pulse generator 45
At, the optimal read pulse is generated. At this time, the switching circuit 43 is controlled by the control circuit 41 so as to connect the read pulse generator 45 and the ferroelectric capacitor 42.

Next, FIG. 6 shows and describes a ferroelectric memory device as a sixth embodiment according to the present invention. In the above-described first to fifth embodiments, the single memory cell composed of one ferroelectric capacitor has been described, but here, an array in which a plurality of memory cells are arranged in a matrix is described as an example.

In this ferroelectric memory device, a row decoder 52 and a column decoder 53 are connected to the memory array 51 when one memory cell can be selected. A defect density detection circuit 54 and a write / read pulse generator 55 are connected to the row decoder 52. In the ferroelectric memory device configured as above, in the memory array 51, one memory cell is selected by the row decoder 52 and the column decoder 53, and when writing information to the memory cell,
This is performed by applying the write pulse generated by the write / read pulse generator 55.

Next, when the information is read from the memory cell selected by the row and column decoders 52 and 53, the defect density detecting circuit 54 measures the state of the defect density. The measuring method is the same as in the third and fourth embodiments described above.

As a result, the write / read pulse generator 55 applies an optimum read pulse to the memory cell to read the information to be stored. As described above, according to the present embodiment, even if the stored information is read out by discriminating the storage states of the binary memory states “1” and “0” by applying the read drive voltage, the information is lost. Without being told
Non-destructive reading is performed and a rewriting circuit becomes unnecessary.
Further, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications and applications can be made without departing from the scope of the invention.

[0035]

As described in detail above, according to the present invention, the information to be stored can be read nondestructively, the life can be extended,
A ferroelectric memory suitable for integration can be provided.

[Brief description of drawings]

FIG. 1 is a diagram showing a ferroelectric memory device as a first embodiment according to the present invention.

FIG. 2 is a diagram showing a ferroelectric memory device as a second embodiment according to the present invention.

FIG. 3 is a diagram showing a ferroelectric memory device as a third embodiment according to the present invention.

FIG. 4 is a diagram showing a ferroelectric memory device as a fourth embodiment according to the present invention.

FIG. 5 is a diagram showing a ferroelectric memory device as a fifth embodiment according to the present invention.

FIG. 6 is a diagram showing a ferroelectric memory device as a sixth embodiment according to the present invention.

[Explanation of symbols]

1, 11, 22, 32, 42 ... Ferroelectric capacitor,
2, 12, 23, 33, 43 ... Switching circuit, 3, 13 ... Write circuit, 4, 14 ... Read circuit with variable read pulse amplitude, 5, 15 ... Controller, 21, 31, 41
... write / read control circuit, 24 ... linear capacitance measurement circuit,
25, 35, 45 ... Read-out pulse generator, 26, 36,
46 ... Write pulse generator, 34 ... DC resistance measuring circuit,
44 ... Pyrocurrent measuring circuit, 51 ... Memory array, 52 ... Row decoder, 53 ... Column decoder, 54 ... Defect density detection circuit, 55 ... Write / read pulse generator

Claims (1)

[Claims] 1. A first electrode made of a conductive film formed on a substrate, a ferroelectric film formed on the first electrode and in which information is written, and a conductive film formed on the ferroelectric film. In a ferroelectric memory device having a second electrode made of a body film, a means for varying a read pulse width, a means for varying a read amplitude, or a means for varying a read pulse width and an amplitude when reading information from the ferroelectric film. A ferroelectric memory device comprising any one of means for varying both.