JPH0792763B2 - Fault handling method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure processing method, and more particularly to a failure processing method when a correctable error occurs frequently in an arithmetic processing unit having an error-correctable control memory.

2. Description of the Related Art Conventionally, this type of information processing apparatus has an error correction circuit in the control memory, and when a correctable error occurs, even if a large number of errors occur, the processing is continued. Further, when an error occurs, error information is collected by the service processor or the like, but this error information overflows due to the occurrence of many correctable errors, and therefore some devices suppress the error acceptance.

In the above-described conventional information processing device, the operation is continued as it is even if a correctable error occurs in the control memory, and therefore the performance of the arithmetic processing device deteriorates when the correctable error occurs frequently. There is a drawback that Also,
Since many correctable errors occur, if the correctable error becomes an uncorrectable error, it becomes impossible to continue the operation of the arithmetic processing unit, and this information processing unit is stopped. There is.

In some cases, even correctable errors can render instructions unexecutable by steps of a microprogram in control store.

SUMMARY OF THE INVENTION Therefore, the present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to prevent system down of the entire information processing system when correctable errors occur frequently. It is to provide a fault handling method that

The failure processing method according to the present invention is a failure processing method that collects failure information and performs failure relief processing when a failure occurs in the arithmetic processing device, and this error processing method is performed for each report of occurrence of a correctable error from the arithmetic processing device. Counting means for counting the number of occurrences, deterring means for suppressing acceptance of the report of occurrence of the correctable error when the number of countings by the counting means reaches a predetermined number within a certain time, and the number of times is reached. Occasionally, an interrupt means for generating an interrupt to the arithmetic processing unit, and a means for disconnecting the arithmetic processing unit from the system after that are provided, and the contents of the software visible register in the arithmetic processing unit are frozen to obtain another normal state. The contents of the register are controlled to be transferred to another arithmetic processing unit.

Further, the inhibiting means is configured to release the inhibition after a predetermined time from the initiation of the inhibition, collect error information, and issue a warning to a maintenance person. It is configured to receive the interrupt at the break and suppress the execution of the next instruction, and to send a response to the interrupt to the interrupt means, and to perform the transfer control after receiving the response.

Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, a fault processing device 1 performs fault information collection and fault relief processing when a fault occurs in another device including the arithmetic processing device 2.

The control storage circuit 3 is a memory that stores the microprogram of the arithmetic processing unit 2, and also has an error correction code. The microprogram data read from the control storage circuit 3 is set in the microinstruction read register 5 to execute the command. Prior to that, the data correctness check is performed in the error correction circuit 4, and any error that can be corrected is detected. For example, the corrected data is set in the microinstruction read register 5. At this time, the error correction circuit 4
Notifies the error reception circuit 8 of the failure processing device 1 of an error occurrence. The error receiving circuit 8 issues an interrupt to the failure processing control unit 7. The error notification can be suppressed by the error suppression circuit 9.

The error counter 10 counts the number of error occurrence notifications received by the error receiving circuit 8 and is reset at a certain fixed time. Therefore, this error counter 10 counts the number of occurrences of correctable errors of the arithmetic processing unit 2 within the fixed time. When the content counted by the error counter 10 reaches a preset number of times, the failure processing device controller 7 controls the error suppression circuit 9 to suppress the acceptance of the error occurrence report. At the same time, an instruction stop interrupt to the arithmetic processing unit 2 is generated in the microprogram control unit 6 via the communication unit 11.

Next, the overall operation will be described using the operation flowchart of FIG. Upon receipt of the error occurrence report described above, the failure processing device control unit 7 updates the counter 10 and checks whether the counter has exceeded a predetermined value N. If it is not over, the operation is continued. Although not shown in FIG. 2, the counter 10 is reset when a predetermined time has elapsed from the first error occurrence. When the counter 10 exceeds N, the error suppression circuit 9 is set to temporarily suppress the error acceptance.

Next, it is checked whether there is an arithmetic processing device other than the arithmetic processing device 2, and if it does not exist, the operation is continued. In this case, although not shown, the error suppression circuit 9 is released after a lapse of a fixed time after setting, and error information is collected. This gives a warning to maintenance personnel.

Next, a case where another arithmetic processing device is present will be described. In this case, the arithmetic processing unit 2 is compared with the arithmetic processing unit communication unit.
The instruction stop interrupt is notified to the micro program control unit via 11. The microprogram of the arithmetic processing unit 2 executes a software instruction, receives the interrupt at the break of the instruction, suppresses the execution of the next instruction, and returns a response to the failure processing unit 1. Upon receiving the response, the failure processing device 1 extracts the software visible register of the arithmetic processing device 2 via the diagnostic interface and transfers it to another normal arithmetic processing device (not shown). The subsequent processing is an operation of processor relief processing, which is a well-known technique, and is not particularly described here.

As described above, according to the present invention, an arithmetic processing unit is detected by using the processor relief processing, which is a well-known technique, when a large number of correctable errors in the control memory circuit is detected and it is determined that the correctable errors occur frequently. By enabling the system to be separated from the system, a large number of correctable errors in the control memory will result in uncorrectable errors, or instructions will not be able to be executed due to the step of the microprogram in which the error has occurred, and the system will operate. It has the effect of eliminating the problem of stopping.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a flow chart showing the operation of the blocks of FIG. Description of symbols of main parts 1 ... Fault processing device 2 ... Arithmetic processing device 4 ... Error correction circuit 5 ... Micro instruction read register 8 ... Error acceptance circuit 9 ... Error suppression circuit 10 ... Error counter

Claims (2)

[Claims] 1. A failure processing method for collecting failure information and failure recovery processing when a failure occurs in an arithmetic processing unit, and counting the number of occurrences of each correctable error occurrence report from the arithmetic processing unit. Means, deterring means for deterring acceptance of the report of occurrence of the correctable error when the number of times of counting by the counting means reaches a predetermined number within a fixed time, and the arithmetic processing unit when the number of times reaches the number of times. Interrupting means for generating an interrupt to the system, and means for disconnecting the arithmetic processing unit from the system after that, freeze the contents of the software visible register in the arithmetic processing unit, and send it to another normal arithmetic processing unit. A failure processing method characterized in that each content of a register is controlled to be transferred. 2. The suppressing means is configured to cancel the suppression after a predetermined time from the start of the suppression and collect error information to warn a maintenance person.
The interrupt is received at the break of its own instruction execution, the execution of the next instruction is suppressed, and a response to the interrupt is sent to the interrupt means, and the transfer control is performed after receiving the response. The fault handling method according to claim 1, wherein the fault handling method is performed.