JPH0792494A - Active matrix substrate and its production - Google Patents

Abstract

PURPOSE:To provide an active matrix substrate capable of suppressing a height difference on a substrate as far as possible and the process for production thereof. CONSTITUTION:Gate electrode layers 1 are formed on a glass substrate 10 and an insulating layer 12 is formed over the entire surface of this substrate including the regions where these gate electrode layers are formed. Semiconductor layers 13a and ohmic contact layers 14a are formed atop this insulating layer 12 and wiring layers 2 are formed thereon. The semiconductor layers 13a and the ohmic layers 14a are constituted of the same patterns as the patterns of the wiring layers 2. The semiconductor layers 13a and the ohmic layers 14a are intrinsically necessary only in the transistor element regions but are deliberately formed in the wiring regions as well so as to function as 'sleeper' to the wiring layers 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate and a method of manufacturing the same, and more particularly to an active matrix substrate suitable for use in a liquid crystal display device and a method of manufacturing the same.

[0002]

2. Description of the Related Art Liquid crystal display devices have been used for a wide range of applications as power-saving displays, and active matrix substrates are generally used as substrates for driving such liquid crystal display devices. There is. In a typical liquid crystal display device, two substrates are arranged so as to face each other, liquid crystal is filled between both substrates, and optical characteristics of the filled liquid crystal are controlled for each pixel by a voltage applied between both substrates. Although it is made possible, an active matrix substrate is usually used as one of the substrates. On this active matrix substrate, a display electrode that serves as one electrode for applying a voltage and a transistor element for controlling the voltage applied to the display electrode are formed in each pixel region. By turning ON / OFF, the optical characteristics of the liquid crystal are controlled for each pixel.

A transistor element formed on an active matrix substrate has a source electrode layer and a drain electrode layer, a channel layer formed between these electrodes, a gate electrode layer for controlling the conduction state of the channel layer, Composed by. In the active matrix substrate, since it is necessary to provide a transistor element for each pixel vertically and horizontally arranged on the substrate, the electrode layer of each transistor element normally serves as the wiring layer of the entire substrate, and each display element The structure is such that the electrode is continuous with the electrode layer of each transistor element.

[0004]

As described above, one electrode layer (for example, the source electrode layer) of the transistor element in the general active matrix substrate also serves as the wiring layer of the entire substrate, and the other electrode layer of the transistor element serves as the wiring layer of the other substrate. The electrode layer (for example, the drain electrode layer) is continuous with the display electrode. However, the source electrode layer and the drain electrode layer are
Since it is necessary to electrically connect to the channel layer, a structure that intersects with the channel layer in the channel layer formation region is adopted. Therefore, for example, when a structure is used in which a part of the wiring layer of the entire substrate is used as the source electrode layer, only a part of the wiring layer that functions as the source electrode layer is crossed with the channel layer. Therefore, the wiring layer has a structure in which it partially extends over the channel layer. Similarly, when the display electrode layer has a structure in which the display electrode layer is continuous with the drain electrode layer, only a portion functioning as the drain electrode layer intersects with the channel layer in a three-dimensional manner. As described above, a structure in which the same layer partially bulges in order to straddle the channel layer causes a height difference on the substrate, which is not preferable. Such a difference in height becomes a factor in causing cracks in the layer, which easily causes disconnection.

Therefore, an object of the present invention is to provide an active matrix substrate capable of suppressing the height difference on the substrate as much as possible and a manufacturing method thereof.

[0006]

[Means for Solving the Problems]

(1) In the first invention of the present application, a gate electrode layer is formed on a substrate having an insulating surface at least on the upper surface, and the insulating layer is formed on the entire surface of the substrate including the gate electrode layer forming region. A channel layer made of a semiconductor is formed, a source electrode layer is formed on one side of the channel layer, and a drain electrode layer is formed on the other side.
An active element is formed which makes electrical contact with each other and controls the conduction state between the source electrode layer and the drain electrode layer according to the potential of the gate electrode layer. In the matrix substrate, an upper wiring layer that functions as a common source electrode layer or drain electrode layer for a plurality of active elements arranged in a line and linearly extends is formed, and a semiconductor is formed at least in a region below the upper wiring layer. A layer is formed and a part of this semiconductor layer is used as a channel layer.

(2) In the second invention of the present application, a gate electrode layer is formed on a substrate having an insulating surface at least on the upper surface, and the insulating layer is formed on the entire surface of the substrate including the gate electrode layer forming region. Forming a channel layer made of semiconductor on the upper surface of
An active element that electrically connects the source electrode layer to one of the channel layers and the drain electrode layer to the other, and controls the conduction state between the source electrode layer and the drain electrode layer by the potential of the gate electrode layer An active matrix substrate formed by forming a display electrode layer into and out of which electric charges are taken in and out by the active element, and arranging a large number of pixels constituted by the active element and the display electrode layer in a matrix. A semiconductor layer is formed in a region below a display electrode layer and an electrode layer of an active element connected to the display electrode layer, and a part of the semiconductor layer is used as a channel layer.

(3) A third invention of the present application is the method of manufacturing an active matrix substrate according to the first invention, which includes a step of forming a gate electrode layer on the substrate and a step of forming the gate electrode layer forming region. Forming an insulating layer on the entire surface of the substrate, forming a semiconductor layer on the entire surface of the insulating layer, forming a conductive layer on the entire surface of the semiconductor layer, patterning the conductive layer, and The step of forming a wiring layer and the step of patterning the semiconductor layer by an etching process using at least the upper wiring layer as a mask are performed.

(4) A fourth invention of the present application is the method for manufacturing an active matrix substrate according to the above-mentioned second invention, which includes a step of forming a gate electrode layer on the substrate and a step of forming the gate electrode layer forming region. Forming an insulating layer on the entire surface of the substrate, forming a semiconductor layer on the entire surface of the insulating layer, forming a conductive layer on the entire surface of the semiconductor layer, patterning the conductive layer, and displaying A step of forming an electrode layer and an electrode layer of an active element continuous with the electrode layer, and a step of patterning a semiconductor layer by an etching process using at least the display electrode layer and the electrode layer of an active element continuous with the display electrode layer as a mask. It is the one.

[0010]

[Operation] In the active matrix substrate according to the present invention, a region under the upper wiring layer extending linearly, or
A semiconductor layer is formed in a region below the display electrode layer and the electrode layer of the active element connected to the display electrode layer. That is, the semiconductor layer is formed not only in the original channel layer forming region required as an active element but also in the lower region of the upper wiring layer and the lower region of the display electrode layer. Since the semiconductor layers formed in these extra regions do not participate in the operation of the active element at all, it can be said as a useless layer as far as electronic functions are concerned, but it is important to suppress the height difference structurally. It will fulfill its function.

[0011]

The present invention will be described below based on illustrated embodiments. First, for reference, the structure of the active matrix substrate proposed so far will be described. FIG. 1 is a plan view showing the structure of a part of an active matrix substrate disclosed in Japanese Patent Application No. 5-148678. This active matrix substrate is one in which the number of photomasks to be used is reduced by performing backside exposure from the backside of the substrate in the manufacturing process. The first wiring layer 1 shown by the solid line in the figure is
It is arranged at equal intervals so as to extend in the left-right direction of the figure,
The second wiring layers 2 shown by broken lines in the figure are arranged at equal intervals so as to extend in the vertical direction of the figure. Moreover, the first wiring layer 1 and the second wiring layer 2 intersect three-dimensionally (second
Wiring layer 2 passes over the first wiring layer 1). In this way, a large number of first wiring layers 1 are arranged at equal intervals in the horizontal direction, a large number of second wiring layers 2 are arranged at equal intervals in the vertical direction, and these wirings are arranged vertically and horizontally. The layers form, so to speak, a grid-like section. This one section is an area corresponding to one pixel, and a substantially square display electrode layer 7 (shown by an alternate long and short dash line) is arranged in each section.

This active matrix substrate is characterized by the structure of each electrode layer for forming a transistor element. First, on the right side of the second wiring layer 2, an L-shaped third wiring layer 3 (shown by a broken line) is formed. The third wiring layer 3 three-dimensionally intersects the first wiring layer 1 (the third wiring layer 3 passes above the first wiring layer 1). Further, the upper left portion of the display electrode layer 7 in FIG. 3 extends upward in the drawing to form a fourth wiring layer 4 that three-dimensionally intersects with the first wiring layer 1 (fourth wiring layer 4). Is the first
Passing above the wiring layer 1). Eventually, the second wiring layer 2, the third wiring layer 3, and the fourth wiring layer 4 are three-dimensionally intersected with the first wiring layer 1 at points P, Q, and R, respectively. . Here, as shown by hatching the portion of the transistor element on the right side in FIG.
Of the wiring layer 2 (portion P ′) and the intersection of the third wiring layer 3 (portion Q ′) constitute the source electrode layer S, and the intersection of the fourth wiring layer 4 ( The portion at the point R ′) constitutes the drain electrode layer D. Further, the first wiring layer 1 partially constitutes the gate electrode layer G.

Such a structure is clearly shown in FIGS. 2 and 3. 2 is a side sectional view of the plan view of FIG. 1 taken along the horizontal cutting line XX, and FIG. 3 is a side sectional view of the plan view of FIG. 1 taken along the vertical cutting line YY. It is a figure. A metal layer 11 is formed on the upper surface of a translucent insulating substrate 10 made of glass or the like. This metal layer 11 is
It corresponds to the first wiring layer 1 shown by the solid line in the plan view of FIG. 1 and functions as the gate electrode layer G. The channel layer 1 is formed on the metal layer 11 via the insulating layer 12.
3a is formed. The channel layer 13a is a layer patterned by backside exposure, and is a metal layer 11
It has the exact same pattern as the plane pattern of. That is,
The channel layer 13a is a layer that is patterned as a result of performing light exposure from below the substrate in the figure using the metal layer 11 as a mask. Second wiring layer 2
(Functions as the source electrode layer S), the third wiring layer 3
The fourth wiring layer 4 (which functions as the other source electrode layer S) and the fourth wiring layer 4 (which functions as the drain electrode layer D) intersect with the upper surface of the channel layer 13a via the ohmic layer 14a. become.

With such a structure, the gate electrode layer G
By controlling the potential of the first wiring layer 1 that functions as the above, it is possible to control the conduction state between the source electrode layer S and the drain electrode layer D. That is, if a predetermined voltage is applied to the first wiring layer 1, the channel layer 1 shown in FIG.
A current channel as indicated by a thick arrow is formed in 3a, and conduction is established between the source electrode layer S and the drain electrode layer D. As the source electrode layer S, two parts, that is, a part of the second wiring layer 2 and a part of the third wiring layer 3 can be used. Therefore, as shown by two thick arrows in the figure, , Channels are formed on both sides of the drain electrode layer D which is a part of the fourth wiring layer 4. Since the fourth wiring layer 4 is connected to the display electrode layer 7, after all,
The signal charge supplied to the wiring layer 2 can be taken in and out of the display electrode layer 7, and the charge accumulation state can be controlled for each pixel.

Here, the source electrode layer S of each transistor element is formed as a part of the second wiring layer 2 and the third wiring layer 3, as shown in the plan view of FIG. A wiring layer including the second wiring layer 2 and the third wiring layer 3 (hereinafter, referred to as an upper wiring layer) serves as a common source electrode layer for a plurality of transistor elements arranged in a line in the vertical direction of the drawing. Will work. Further, the drain electrode layer D of each transistor element is configured as an electrode layer (fourth wiring layer 4) continuous with the display electrode layer 7, as shown in the plan view of FIG.

Now, in such an active matrix substrate, the formation region of the channel layer 13a will be confirmed in the plan view of FIG. As described above, in this active matrix substrate, the channel layer 13a
Are patterned by backside exposure using the first wiring layer 1 as a mask. Therefore, the channel layer 1
The pattern 3a is exactly the same as the pattern of the first wiring layer 1 shown by the solid line in FIG. In other words, the channel layer 13a is formed in the region directly above the first wiring layer 1 with the insulating layer 12 interposed therebetween. Therefore, as shown in FIG. 1, the wiring layers 2, 3 and 4 have such a structure that they straddle the channel layer 13a at points P, Q and R, respectively. This state is a side sectional view of FIG. 3 (the cutting line Y in FIG.
(Y cross section). The second wiring layer 2 crosses the channel layer 13a and the ohmic layer 14a in a three-dimensional manner. However, such a three-dimensional intersection causes a concavo-convex structure on the substrate, which causes a difference in height. In the structure shown in FIG. 3, there is a height difference d on the upper surface of the second wiring layer 2. If such a height difference d is generated, the second wiring layer 2 may be broken, and it may be an obstacle to uniformly forming a passivation film on the second wiring layer 2. The same problem occurs at the three-dimensional intersection between the third wiring layer 3 and the channel layer 13a or the three-dimensional intersection between the fourth wiring layer 4 and the channel layer 13a. The present invention proposes a new structure capable of suppressing such a height difference d.

Before explaining the structure according to the present invention, another structure of the active matrix substrate will be described. The active matrix substrate shown in FIG. 1 (hereinafter, referred to as back exposure type) is a substrate manufactured by using back exposure, while the active matrix substrate shown in FIG. 4 (hereinafter, referred to as non-back exposure type). Is a substrate manufactured without backside exposure. This non-backside exposure type active matrix substrate is another patent application (reference number A0 filed by the same applicant as the present applicant at the same time as the present application.
5045). The only difference from the back exposure type is the pattern of the channel layer. That is, in the back exposure type, the pattern of the channel layer 13a was exactly the same as that of the first wiring layer 1. However, in the non-back exposure type, as shown by the chain double-dashed line in FIG. Each transistor element has an independent island pattern.

Such a structure is clearly shown in FIGS. 5 is a side sectional view of the plan view of FIG. 4 taken along the horizontal cutting line XX, and FIG. 6 is a side sectional view of the plan view of FIG. 4 taken along the vertical cutting line YY. It is a figure. In order to form the channel layer C having such an island pattern, a dedicated photomask for the channel layer C is prepared, and normal front exposure (exposure from above the substrate) is performed.
Will be done. Therefore, the number of photomasks required is increased by one as compared with the back exposure type, but the channel layer C
Is an independent structure for each transistor element,
There is an advantage that the leak current between the adjacent transistor elements can be prevented.

However, even in such a non-rear-exposure type active matrix substrate, there is a problem that there is a difference in height due to a three-dimensional intersection with the channel layer C, which is the same as the above-mentioned rear-exposure type. . For example, a side cross-sectional view of FIG. 6 (cross-section taken along the section line Y-Y of FIG. 4)
As shown in FIG. 3, the second wiring layer 2 crosses the channel layer 13a and the ohmic layer 14a in a three-dimensional manner, and a height difference d is generated.

The basic idea of the present invention is to suppress the height difference by adopting a structure in which a semiconductor layer is formed even in an extra region which is not originally necessary. Contrary to the conventional wisdom that the semiconductor layer is used as a channel layer in a transistor element in the first place, it should be formed only in the transistor element formation region. It forms a layer. The present invention is applied to the above-mentioned back exposure type and non-back exposure type active matrix substrates as follows.

In the back exposure type active matrix substrate shown in FIG. 1, in the same region as the first wiring layer shown by the solid line,
The semiconductor layer 13a as a channel layer is formed. In order to apply the present invention to this active matrix substrate, the semiconductor is applied to all areas hatched in FIG. 7 (plan view corresponding to FIG. 1; reference numerals are omitted for avoiding complexity of the drawing). The layer 13a may be formed. In other words, the areas of the first wiring layer 1, the second wiring layer 2, the third wiring layer 3, the fourth wiring layer 4, and the display electrode layer 7 which are obtained by performing the logical OR of the respective areas. , The semiconductor layer 13a is formed. More specifically, the semiconductor layer 13a is formed below each of these layers with the ohmic layer 14a interposed therebetween. Similarly, in order to apply the present invention to the non-back exposure type active matrix substrate shown in FIG.
The plan view corresponding to: The semiconductor layer 13a may be formed in all the hatched regions in order to avoid the drawing from becoming complicated. In other words, first
Of the semiconductor layer in the respective regions of the wiring layer 1, the second wiring layer 2, the third wiring layer 3, the fourth wiring layer 4, the display electrode layer 7, and the channel layer C of FIG. 13a will be formed. More specifically, under each of these layers,
The semiconductor layer 13a is formed via the ohmic layer 14a.

As described above, by forming the semiconductor layer not only in the region originally required as the channel layer but also in the regions of the respective wiring layers and display electrode layers, it is possible to suppress the height difference between the respective wiring layers. it can. This can be easily understood with reference to FIG. FIG. 9 is a side view of the planar structure shown in FIGS. 7 and 8 taken along the section line YY. When the structure shown in FIG. 9 is compared with the structure shown in FIG. 3 or 6, it can be seen that the step d is considerably smaller. In the structure shown in FIG. 9, the semiconductor layer 13 a and the ohmic layer 14 a
Extend in the left-right direction together with the wiring layer 2. Originally Figure 9
The semiconductor layer 13a only in the "transistor element region" shown in
It is only necessary to form the ohmic layer 14a and the ohmic layer 14a. However, the semiconductor layer 13a and the ohmic layer 14a are also formed in an extra region indicated by "wiring region" in the drawing. The semiconductor layer 13a and the ohmic layer 14a in this wiring region are, so to speak, “sleepers” for the wiring layer 2.
It only fulfills the function as. Although FIG. 9 shows the structure of the region related to the wiring layer 2, the semiconductor layer 13a and the ohmic layer 14a functioning as “sleepers” are also formed below the wiring layers 3 and 4, After all, the effect of reducing the step d can be obtained.

By the way, the active matrix substrate is
It is usually used to drive a liquid crystal display device. The liquid crystal display device includes a transmissive type and a reflective type. The transmissive liquid crystal display device has a structure as shown in FIG. That is, the active matrix substrate 100 and the counter substrate 200 are arranged in parallel and face each other, the liquid crystal 300 is filled between the two substrates, and the light transmitted from the lower part of the figure can be observed from the upper part of the figure. It was done. On the other hand, as shown in FIG. 10B, the reflective liquid crystal display device has a structure in which light emitted from above is reflected by the active matrix substrate 100 and the reflected light can be observed from above. It is the one. Of these two types of liquid crystal display devices, the active matrix substrate having the semiconductor layer formed in the pattern shown in FIG. 7 or 8 can be used for the reflection type, but is not suitable for the transmission type. is there. This is because in these active matrix substrates, the semiconductor layer is also formed under the display electrode layer 7, so that the display electrode formation region does not have sufficient translucency. Therefore, when it is used for a transmissive liquid crystal display device, a semiconductor layer is formed only under the second wiring layer 2 and the third wiring layer 3, and the fourth wiring layer 4 and the display electrode layer 7 are formed. It is necessary to have a structure in which a semiconductor layer is not provided in the lower layer. In this case, the fourth
The height difference of the wiring layer 4 is not suppressed.

Finally, an embodiment of the manufacturing process of the above-mentioned active matrix substrate will be described. Here, the cutting line X-X or the cutting line Y-Y in the plan view shown in FIG.
The manufacturing process of the active matrix substrate, in which the present invention is applied to the above-mentioned back exposure type, will be described with reference to the side sectional view corresponding to the portion. First, as shown in FIG. 11A, a non-translucent metal layer 11 is formed on a translucent substrate 10 (for example, a glass substrate). This metal layer 1
1 corresponds to the first wiring layer 1 in the plan view of FIG. 1 and can be formed by performing a photolithography process using a photomask having a plane pattern shown by a solid line in FIG. Next, as shown in FIG.
An insulating layer 12, a semiconductor layer 13, a high concentration doped layer 14, and a conductive layer 15 are formed on the entire surface of this substrate. The insulating layer 12 is, for example, a silicon nitride film, the semiconductor layer 13 is a layer made of amorphous silicon, and the high-concentration doped layer 14 is used.
Is a layer (so-called n ⁺ layer) in which this amorphous silicon is doped with a high concentration of impurities, and the conductive layer 15 is made of Cr,
It is a metal layer such as ITO.

One of the advantages of the method of manufacturing the active matrix substrate according to the present invention is that the insulating layer 12 to the conductive layer 15 are formed.
The point is that the four layers up to the above can be continuously formed. Since a patterning process such as exposure or etching does not intervene in the process of forming these four layers, the substrate 10 can be placed in a vacuum chamber and four layers can be continuously formed while maintaining a vacuum state. is there. In the conventional active matrix substrate, there is an existing concept that the semiconductor layer is formed only in a region necessary as a channel layer, and therefore, the three layers from the insulating layer 12 to the high concentration doped layer 14 are formed.
The layers could be continuously formed while maintaining the vacuum state, but before forming the conductive layer 15, the substrate 10 was taken out of the vacuum chamber, and the semiconductor layer 13 and the high-concentration doped layer 14 were patterned, The process of forming a channel layer and an ohmic layer was performed, respectively. However, performing such a process outside the vacuum chamber adversely affects the electrical contact state between the patterned ohmic layer and the conductive layer 15 formed thereon due to factors such as dust adhering to the surface. Will be covered. In the method according to the present invention, since four layers up to the conductive layer 15 can be continuously formed, electrical contact between the high-concentration doped layer 14 (which becomes an ohmic layer in a later step) and the conductive layer 15 is formed. The condition is extremely good.

Now, as shown in FIG. 11B, after the four layers are continuously formed, the conductive layer 15 is subsequently patterned. As a result of this patterning, the conductive layer 15
Is the second wiring layer 2, the third wiring layer 3, the fourth wiring layer 3 shown in FIG.
The wiring layer 4 and the display electrode layer 7 are removed, leaving the respective portions. The state at this time is shown in the side sectional view (side sectional view taken along the section line XX) shown in FIG.
Next, back surface exposure is utilized to perform patterning on the semiconductor layer 13 and the high-concentration doped layer 14. That is,
A resist layer is formed on the structure shown in FIG. 11C, and the resist layer is exposed by irradiating light from below the substrate. In this exposure, the metal layer 11 having a perfect light blocking function functions as a mask, and the pattern of this metal layer 11 can be transferred to the resist layer. Therefore, development is performed so that only a resist layer having the same pattern as the metal layer 11 remains, and etching is performed using the remaining resist layer as a protective layer to partially remove the high-concentration doped layer 14 and the semiconductor layer 13. Remove. However, in this etching process, together with the resist layer, the wiring layer 2,
Since 3, 4 and the display electrode layer 7 function as a protective layer, after all, only the portion of the high-concentration doped layer 14 and the semiconductor layer 13 having the pattern shown by hatching in FIG.
It will remain without being etched. In FIG. 7, the insulating layer 12 is exposed in the unhatched region. Thus, according to the gist of the present invention, the semiconductor layer is formed not only in the region necessary for the original channel layer (the region above the wiring layer 1) but also in the lower region of each wiring layer 2, 3, 4 and the display electrode layer 7. The resulting structure will be obtained. After that, the heavily doped layer 14 is partially removed by etching to separate the ohmic layer 14a for each electrode.
By forming the above structure, the structure shown in FIG. 2 can be obtained from the structure shown in FIG. Finally, if a passivation layer is formed on this, an active matrix substrate is completed. The high-concentration doped layer 14 may be etched simultaneously with the patterning of the conductive layer 15.

The manufacturing method of the active matrix substrate to which the present invention is applied to the back exposure type shown in FIG. 1 has been described above. The active matrix substrate to which the present invention is applied to the non-back exposure type shown in FIG. The manufacturing method of is almost the same. However, the difference is that instead of the back exposure step, front exposure (exposure from above the substrate) is performed using a photomask having the pattern of the channel layer C shown by the chain double-dashed line in FIG.

The present invention has been described above based on the illustrated embodiments, but the present invention is not limited to these embodiments and can be implemented in various modes other than this. In the above-mentioned embodiment, the example in which the present invention is applied to the active matrix substrate having the structure shown in FIG. 1 or 4 is shown, but the present invention is not limited to such a structure, and various other It can be widely applied to the active matrix substrate having the above structure. Further, in the above-described embodiment, the semiconductor layers are formed under the wiring layers 2, 3, 4 and the display electrode layer 7, but it is not always necessary to form the semiconductor layers under the respective layers. For example, even when the semiconductor layer is formed only under the wiring layer 2,
The effect of reducing the height difference of the wiring layer 2 is obtained. Further, in the above-mentioned embodiments, the structure in which the drain electrode layer D is connected to the display electrode layer 7 is shown, but the present invention is also applied to the structure in which the source electrode layer S is connected to the display electrode layer 7. It is possible.

[0029]

As described above, according to the active matrix substrate of the present invention, not only the original channel layer forming region required as an active element but also the lower region of the upper wiring layer and the lower region of the display electrode layer are formed. Since the semiconductor layer is formed, it is possible to structurally suppress the height difference.

[Brief description of drawings]

FIG. 1 is a plan view showing a structure of a conventional general active matrix substrate manufactured by using backside exposure.

FIG. 2 is a side cross-sectional view showing a cross section of the active matrix substrate shown in FIG. 1 along the cutting line XX.

FIG. 3 is a side cross-sectional view showing a cross section of the active matrix substrate shown in FIG. 1 along the cutting line YY.

FIG. 4 is a plan view showing a structure of a conventional general active matrix substrate manufactured without using backside exposure.

5 is a side sectional view showing a section taken along a cutting line XX of the active matrix substrate shown in FIG.

6 is a side sectional view showing a section taken along a cutting line YY of the active matrix substrate shown in FIG.

7 is a plan view showing a semiconductor layer forming region when the present invention is applied to the active matrix substrate shown in FIG.

8 is a plan view showing a semiconductor layer forming region when the present invention is applied to the active matrix substrate shown in FIG.

9 is a side cross-sectional view showing a cross section of the active matrix substrate shown in FIG. 7 or 8 taken along the cutting line YY.

FIG. 10 is a side sectional view showing a basic structure of a transmissive liquid crystal display device and a reflective liquid crystal display device.

FIG. 11 is a side sectional view showing a manufacturing process of the active matrix substrate according to the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... 1st wiring layer 2 ... 2nd wiring layer 3 ... 3rd wiring layer 4 ... 4th wiring layer 7 ... Display electrode layer 10 ... Translucent substrate 11 ... Metal layer 12 ... Insulating layer 13 ... Semiconductor Layer 13a ... Channel layer 14 ... High concentration doped layer 14a ... Ohmic layer 15 ... Conductive layer 100 ... Active matrix substrate 200 ... Counter substrate 300 ... Liquid crystal d ... Height difference C ... Channel layer D ... Drain electrode layer G ... Gate electrode layer S ... Source electrode layer

Claims (4)

[Claims] 1. A gate electrode layer is formed on a substrate having an insulating surface at least on the upper surface, an insulating layer is formed on the entire surface of the substrate including the gate electrode layer forming region, and a channel layer made of a semiconductor is formed on the upper surface of the insulating layer. And a source electrode layer on one side of the channel layer and a drain electrode layer on the other side of the channel layer, respectively, and the potential between the source electrode layer and the drain electrode layer is changed by the potential of the gate electrode layer. As a common source electrode layer or drain electrode layer for a plurality of active elements arranged in a row in an active matrix substrate in which active elements for controlling the conduction state are formed and a large number of such active elements are arranged vertically and horizontally. An upper wiring layer that functions and extends linearly is formed, a semiconductor layer is formed at least in a region below the upper wiring layer, and a part of this semiconductor layer is used as a channel layer. The active matrix substrate characterized in that as adapted to use. 2. A gate electrode layer is formed on a substrate having an insulating surface at least, and an insulating layer is formed on the entire surface of the substrate including the gate electrode layer forming region, and a channel layer made of a semiconductor is formed on the upper surface of the insulating layer. And a source electrode layer on one side of the channel layer and a drain electrode layer on the other side of the channel layer, respectively, and the potential between the source electrode layer and the drain electrode layer is changed by the potential of the gate electrode layer. An active element for controlling a conductive state is formed, a display electrode layer in which electric charges are taken in and out is formed by the active element, and a large number of pixels formed by such an active element and a display electrode layer are arrayed vertically and horizontally. In an active matrix substrate, a semiconductor layer is formed at least in a region below a display electrode layer and an electrode layer of an active element connected to the display electrode layer, and a part of the semiconductor layer is a channel layer. The active matrix substrate characterized in that as adapted to use with. 3. The method for manufacturing an active matrix substrate according to claim 1, wherein a step of forming a gate electrode layer on the substrate, and forming an insulating layer on the entire surface of the substrate including the gate electrode layer forming region. A step of forming a semiconductor layer on the entire surface of the insulating layer, forming a conductive layer on the entire surface of the semiconductor layer, and patterning the conductive layer to form an upper wiring layer. And a step of patterning the semiconductor layer by an etching process using at least the upper wiring layer as a mask, the method for manufacturing an active matrix substrate. 4. The method for manufacturing an active matrix substrate according to claim 2, wherein a step of forming a gate electrode layer on the substrate, and forming an insulating layer on the entire surface of the substrate including the gate electrode layer forming region. The step of forming a semiconductor layer on the entire surface of the insulating layer, the step of forming a conductive layer on the entire surface of the semiconductor layer, and patterning the conductive layer to form a display electrode layer and an active layer connected to the display electrode layer. A step of forming an electrode layer of an element, and an etching process using at least the display electrode layer and an electrode layer of an active element connected to the display electrode layer as a mask,
Patterning the semiconductor layer, and a method of manufacturing an active matrix substrate, comprising: