JPH0792204A - Comparator circuit - Google Patents

Abstract

PURPOSE:To make an output voltage in a steady state constant by constituting a circuit by providing a comparator of which a potential difference between positive and negative input terminals in the steady state is made 0V and a resistor which is connected to an offset regulation terminal of the comparator so as to generate an offset. CONSTITUTION:This circuit features that an offset regulation terminal (s) which an analog comparator 4 has is utilized effectively, that both of bias resistors 2 and 3 of positive and negative input terminals of the comparator 4 are connected to GND, and that a resistor to Vcc is made inexistent and, instead, a resistor 5 for generating an offset is connected to the offset regulation terminal (s) of the comparator 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator circuit applied to electronic equipment using an analog comparator.

[0002]

2. Description of the Related Art Conventionally, the output voltage of an analog comparator in a steady state (no signal state) is "0" or "1".
When setting the level, as shown in FIG. 2, a method of applying a bias between the positive and negative input terminals has been adopted.

In FIG. 2, 01 is a capacitor for cutting the DC component of the output of the preceding stage. Reference numeral 02 is a resistor which is connected between Vcc and the negative input of the comparator and which is combined with the resistor 03 to bias the comparator 06. 03 is GND (ground) and comparator 06
Is a resistor that is connected between the negative input terminals of, and biases the comparator 06 by combining with the resistor 02. Reference numeral 04 is a resistor which is connected between Vcc and the positive input terminal of the comparator 06 and which is combined with the resistor 05 to bias the comparator 06. 05 is G
It is connected between ND and the positive input terminal of the comparator, and resistance 0
4 is a resistor for biasing the comparator 06 when combined with 4. 06 is a comparator,
The input signal applied to the negative input terminal is compared with the reference voltage applied to the positive input terminal, and the result is output to the output terminal at "0" and "1" levels.

In the above-mentioned conventional circuit configuration, when the input signal level is weak, the positive and negative bias voltage values are also small. However, considering the influence of the input bias current and the offset voltage of the comparator, the design is very strict. , The circuit configuration becomes complicated and high component accuracy is required,
There was a problem that it would lead to higher costs.

That is, in the circuit configuration shown in FIG. 1, the output of the comparator 06 when there is no input signal, that is, in the steady state is determined by the constant setting of the network consisting of the resistors 02, 03, 04 and 05. To be In such a configuration, there is no problem when the input signal amplitude is large, but when the signal to be handled becomes weak, the positive and negative input potential difference settings must be reduced, so the error of each resistor and the input bias of the comparator. The current, input offset voltage, etc. cannot be ignored. Therefore, it is necessary to add an amplifier in the previous stage to raise the signal level.

[0006]

As described above, in the conventional circuit configuration, when the input signal level is weak, the positive and negative bias voltage values are also reduced, but the influence of the input bias current and offset voltage of the comparator is reduced. Considering this, there is a problem that the design becomes very strict, the circuit configuration becomes complicated, high component accuracy is required, and the cost increases.

The present invention has been made in view of the above circumstances,
An object of the present invention is to provide a comparator circuit using low-cost circuit means for setting a steady output voltage of an analog comparator that handles a weak input signal.

That is, the present invention is in a steady state (no signal state).
In the comparator circuit for handling the weak input signal, the output voltage of which is set to "0" or "1" level,
An object of the present invention is to provide a comparator circuit that can be easily realized with a simple and inexpensive circuit configuration.

[0009]

According to the present invention, a comparator having a potential difference between positive and negative input terminals of 0 V in a steady state and a resistor connected to an offset adjusting terminal of the comparator for generating an offset are provided. The circuit configuration is characterized in that the output voltage in the steady state is constant.

That is, according to the present invention, as shown in FIG. 1, the offset adjusting terminal (s) of the analog comparator (4) is effectively used, and the bias resistance (2, 2) of the input terminal of the comparator (4) is used. 3) are both connected to GND and there is no resistance to Vcc. Instead, the offset generating resistor (5) is connected to the offset adjusting terminal (s) of the comparator (4).

[0011]

In FIG. 1, when the offset generating resistor (5) is not provided, the positive and negative inputs of the comparator (4) are both G
The output voltage is undefined because it is at the ND level, but if the offset generating resistor (5) is present, the comparator (4)
Offset occurs inside the output, and output is "0" or "1"
Can be fixed to. Since a normal comparator with an offset adjustment terminal has adjustment terminals in both positive and negative directions, it suffices to connect the resistor (5) to the adjustment terminal having the desired output. As a result, an analog comparator circuit that handles a weak input signal can be easily realized at a low cost with a simple circuit configuration.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of an embodiment according to the present invention. In FIG. 1, reference numeral 1 is a capacitor for cutting the DC component of the output of the preceding stage. Reference numeral 2 is a resistor that is connected between the GND and the negative input terminal of the comparator 4 and biases the comparator 4. Reference numeral 3 is a resistor which is connected between the GND and the positive input terminal of the comparator 4 and which biases the comparator 4.

Reference numeral 4 is a comparator with an offset adjusting terminal, which compares an input signal applied to the negative input terminal with a reference voltage applied to the positive input terminal, and outputs the result to the output terminal as "0" or "1". "Output at the level.

Reference numeral 5 denotes an offset generating resistor which is connected between Vcc and the offset adjusting terminal (s) of the comparator 4 and intentionally generates the offset of the comparator 4. The operation in one embodiment of the present invention will now be described with reference to the circuit diagram shown in FIG.

The bias resistors 2 and 3 of the positive and negative input terminals of the comparator 4 are both connected to GND, and there is no resistance to Vcc. Instead, the offset generating resistor 5 is connected to the offset adjusting terminal (s) of the comparator 4.

When the offset generating resistor 5 is not provided, the output of the comparator 4 is uncertain because both inputs are at the GND level. However, when the offset generating resistor 5 is provided, an offset is generated inside the comparator 4. However, the output can be fixed to "0" or "1". Since a normal comparator with an offset adjusting terminal has adjusting terminals in both positive and negative directions, the offset generating resistor 5 may be connected to the adjusting terminal having a desired output.

As an application example of the present invention, the reference operating voltage between the input and the output can be changed by applying it to an operational amplifier circuit to which feedback is applied in addition to the comparator.

[0018]

As described above in detail, according to the present invention, in the comparator circuit in which the output voltage in the steady state (no signal state) is set to the "0" or "1" level,
By effectively using the offset adjustment terminal of the analog comparator, the bias resistors of the positive and negative input terminals of the comparator are both connected to GND, and there is no resistance to Vcc. Instead, the offset generation resistor is used to adjust the offset of the comparator. By connecting to the terminal, the comparator circuit that handles weak input signals and that sets the output voltage to "0" or "1" level in the steady state (no signal state) is simple and inexpensive. It can be easily realized with a circuit configuration.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of an embodiment according to the present invention.

FIG. 2 is a circuit diagram showing a conventional circuit configuration.

[Explanation of symbols]

1 ... Capacitor, 2, 3 ... Resistor, 4 ... Comparator (s
… Offset adjustment terminal), 5… Offset generation resistance.

Claims (1)

[Claims] 1. A comparator having an offset adjusting terminal, and a resistor connected to the offset adjusting terminal of the comparator to generate an offset inside the comparator, wherein a connection form of the resistor to the offset terminal is selected. A comparator circuit characterized by arbitrarily setting a comparator output voltage in a steady state.