JPH0787733A - Stabilized power supply starting circuit - Google Patents

Stabilized power supply starting circuit

Info

Publication number
JPH0787733A
JPH0787733A JP23064793A JP23064793A JPH0787733A JP H0787733 A JPH0787733 A JP H0787733A JP 23064793 A JP23064793 A JP 23064793A JP 23064793 A JP23064793 A JP 23064793A JP H0787733 A JPH0787733 A JP H0787733A
Authority
JP
Japan
Prior art keywords
power supply
voltage
control system
stabilized power
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23064793A
Other languages
Japanese (ja)
Inventor
Yoshihiro Shigeta
善弘 重田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP23064793A priority Critical patent/JPH0787733A/en
Publication of JPH0787733A publication Critical patent/JPH0787733A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the loss of useless power generated in a starting circuit that supplies power through the input voltage Vi side to an output voltage control system when starting a stabilized power supply. CONSTITUTION:A starting circuit consists of a normal-on field-effect transistor 20 that extracts current from the input voltage Vi side and feeds it to a control system 10, voltage restricting means 9 to restrict a feed voltage Vs fed to the control system 10 to a specified value or less, and capacitor 8 charged through the feed voltage Vs. During start up of a stabilized power supply, the capacitor 8 is charged through the on-resistance of the transistor 20 to raise the feed voltage Vs. When the feed voltage reaches the specified value required for operating the control system 10, a gate bias is applied to the transistor 20 to sharply decrease the charge current (i) flowing through it from the peak value (ip). The feed current is kept at this decreased level throughout the operation of the stabilized power supply.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はスイッチング電源等の安
定化電源の起動に際して出力電圧の制御系に対して入力
電圧の側から給電するための起動回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a starting circuit for supplying power from a side of an input voltage to a control system of an output voltage when starting a stabilized power supply such as a switching power supply.

【0002】[0002]

【従来の技術】安定化電源では周知のように例えばその
スイッチングトランジスタのオンオフ動作をPWM制御
して出力電圧を一定に保持するための制御系が必要であ
るが、この制御系をトランジスタ等のかなり多数の回路
要素で構成する必要があるため1チップの集積回路に組
み込むのが通例である。この集積回路装置を動作させる
ための給電電圧は、安定化電源の起動完了後には例えば
その補助出力電圧として容易に得られるが、少なくとも
起動中には入力電圧から別途に作る必要があり、このた
め本発明が対象とする起動回路が用いられる。
2. Description of the Related Art As is well known in a stabilized power supply, for example, a control system for PWM-controlling the on / off operation of the switching transistor to maintain a constant output voltage is required. Since it is necessary to configure a large number of circuit elements, it is customary to incorporate it into a one-chip integrated circuit. The power supply voltage for operating this integrated circuit device is easily obtained, for example, as its auxiliary output voltage after completion of the startup of the stabilized power supply, but it must be separately generated from the input voltage at least during startup. The starting circuit targeted by the present invention is used.

【0003】図4(a) にこの起動回路の代表的な従来例
を安定化電源に組み込まれた状態で示す。図示の安定化
電源はスイッチング電源であって、 100〜220Vの商用周
波の交流電圧Vaを整流回路1で整流しかつキャパシタ2
により平滑化かつ安定化した入力電圧Viをフライバック
形の変圧器3に受け、その一次コイル3aに流す電流をス
イッチングトランジスタ4により断続しながら二次コイ
ル3bに誘起する電圧をダイオード5で整流しかつキャパ
シタ6により平滑化した上で出力電圧Voとして出力する
ものであり、図ではブロックで示す集積回路のチップ内
に組み込まれた制御系10はこの出力電圧Voの実際値を受
けて通例のようにそれを所定の設定値に保持するように
スイッチングトランジスタ4をオンオフ制御する。
FIG. 4 (a) shows a typical conventional example of this starting circuit in a state of being incorporated in a stabilized power supply. The stabilizing power supply shown in the figure is a switching power supply, which rectifies an AC voltage Va of a commercial frequency of 100 to 220 V by a rectifying circuit 1 and a capacitor 2
The flyback type transformer 3 receives the smoothed and stabilized input voltage Vi by means of the switching transistor 4, and the diode 5 rectifies the voltage induced in the secondary coil 3b while interrupting the current flowing in the primary coil 3a. The output voltage Vo is output after being smoothed by the capacitor 6. The control system 10 incorporated in the chip of the integrated circuit shown by the block in the figure receives the actual value of the output voltage Vo, and the output voltage Vo is as usual. Then, the switching transistor 4 is controlled to be turned on and off so as to hold it at a predetermined set value.

【0004】この制御系10に対するふつうは5〜15V程
度の低圧の給電電圧Vsは運転中には変圧器3の補助コイ
ル3cの誘起電圧をダイオード7で整流しかつキャパシタ
8により平滑化かつ安定化して作られるが、起動時にこ
の給電電圧Vsを作るため図のように入力電圧Viを受ける
高抵抗Rとツェナーダイオード9の直列回路からなる起
動回路を設け、後者のツェナー電圧以下に制限された給
電電圧Vsを制御系10に与える。スイッチSの投入による
安定化電源の起動時に給電電圧Vsが所定値まで立ち上が
ると、制御系10がスイッチングトランジスタ4に対する
オンオフ制御を開始するので、以後は変圧器3の補助コ
イル3cの方から制御系10に給電電圧Vsとその動作に必要
な電流が供給される。
The low-voltage power supply voltage Vs of about 5 to 15 V for the control system 10 is rectified by the diode 7 during the operation of the induced voltage of the auxiliary coil 3c of the transformer 3 and smoothed and stabilized by the capacitor 8. In order to generate this power supply voltage Vs at the time of start-up, a starter circuit consisting of a series circuit of a high resistance R receiving the input voltage Vi and a Zener diode 9 is provided as shown in the figure, and the power supply is limited to the latter Zener voltage or less. The voltage Vs is applied to the control system 10. When the power supply voltage Vs rises to a predetermined value at the time of starting the stabilized power supply by turning on the switch S, the control system 10 starts the on / off control for the switching transistor 4, and thereafter, the auxiliary coil 3c of the transformer 3 controls the control system. Supply voltage Vs and the current necessary for its operation are supplied to 10.

【0005】[0005]

【発明が解決しようとする課題】上述のように従来の起
動回路は主に抵抗Rからなるごく簡単な構成でよいが、
安定化電源の正常な運転中に抵抗R内に大きな電力損失
が発生する問題がある。これを図4(b) に示す抵抗Rに
流れる電流iの特性図を参照して説明する。図の縦軸が
この電流iであり、横軸が安定化電源の起動時に入力電
圧Viが立ち上がる電圧vである。スイッチSwの投入後に
電圧vが立ち上がる途中でキャパシタ8を充電しながら
制御系10に掛かる電圧が所定の給電電圧Vsの付近に達す
ると、その動作開始に伴って補助コイル3c側から電流が
供給されるので電流iは例えばその小さなピークipの経
過後に一旦は下がるが、電圧vがさらに立ち上がるに伴
って電流iはすぐ増加に転じて以後は図のように電圧v
が所定の入力電圧Viに達するまで直線的に増加して行
く。
As described above, the conventional starting circuit may have a very simple structure mainly composed of the resistor R.
There is a problem that a large power loss occurs in the resistor R during normal operation of the stabilized power supply. This will be described with reference to the characteristic diagram of the current i flowing through the resistor R shown in FIG. The vertical axis of the figure is the current i, and the horizontal axis is the voltage v at which the input voltage Vi rises when the stabilized power supply is started. When the voltage applied to the control system 10 reaches the vicinity of the predetermined power supply voltage Vs while charging the capacitor 8 while the voltage v rises after the switch Sw is turned on, a current is supplied from the auxiliary coil 3c side with the start of the operation. Therefore, the current i temporarily decreases after the passage of the small peak ip, but as the voltage v further rises, the current i immediately starts to increase and thereafter, as shown in the figure,
Increases linearly until it reaches a predetermined input voltage Vi.

【0006】電流iがこのように直線的に増加する結
果、電圧vが入力電圧Viである安定化電源の運転中に電
流iは容易にわかるように (Vi−Vs) /Rとなり、抵抗
R内に発生する定常的な電力損失は (Vi−Vs)2/Rとな
る。前述のように交流電圧Vaが100〜220Vのときその整
流電圧である入力電圧Viは 140〜310Vであり、かつ給電
電圧Vsは5〜15V程度に過ぎないから差Vi−Vsが大きく
なり、従って抵抗R内の電力損失が大きくなるわけであ
る。なお、安定化電源の運転中に制御系10の消費電流が
補助コイル3c側から供給されている状態では抵抗R中の
電流iはツェナーダイオード9の方にむだに流れること
になる。
As a result of the current i increasing linearly in this way, the current i becomes (Vi-Vs) / R and the resistance R becomes easy to understand during the operation of the stabilized power supply in which the voltage v is the input voltage Vi. The stationary power loss that occurs inside is (Vi-Vs) 2 / R. As described above, when the AC voltage Va is 100 to 220V, the rectified voltage, the input voltage Vi is 140 to 310V, and the power supply voltage Vs is only 5 to 15V, so the difference Vi-Vs becomes large. The power loss in the resistor R becomes large. It should be noted that the current i in the resistor R will wastefully flow toward the Zener diode 9 when the consumption current of the control system 10 is supplied from the auxiliary coil 3c side during operation of the stabilized power supply.

【0007】この電力損失を減少させるには抵抗Rを高
抵抗にすればよいが、安定化電源の起動時に制御系10に
その動作に必要な電流を供給できる限界よりは低く抵抗
値を選定する必要があり、この限界抵抗値でも安定化電
源の運転中に抵抗Rに流れる電流iが制御系10の消費電
流より大きくなり、抵抗R内の電力損失は制御系10の消
費電力よりふつう1桁以上大きくなってしまう。
To reduce this power loss, the resistance R may be set to a high resistance, but the resistance value is selected to be lower than the limit that can supply the current required for its operation to the control system 10 at the time of starting the stabilized power supply. Even with this limit resistance value, the current i flowing through the resistor R during operation of the stabilized power supply becomes larger than the current consumption of the control system 10, and the power loss in the resistor R is usually one digit higher than the power consumption of the control system 10. It becomes bigger than that.

【0008】本発明は従来の技術がもつかかる問題点を
解決して起動回路に発生するむだな消費電力を減少させ
ることを目的とする。
An object of the present invention is to solve the above problems of the conventional technique and reduce the wasteful power consumption generated in the starting circuit.

【0009】[0009]

【課題を解決するための手段】本発明によれば上述の目
的は、安定化電源の起動時に出力電圧の制御系に入力電
圧側から給電するために、入力電圧から電流を抽出して
制御系に供給する常時導通形の電界効果トランジスタ
と,制御系に対する給電電圧を設定値以下に制限する電
圧制限手段と,給電電圧により常時充電されるキャパシ
タとを設け、給電電圧が制御系の動作に必要な所定値に
達した後には電界効果トランジスタに対しゲートバイア
スを掛けてそれに流れる電流を絞ることにより達成され
る。
According to the present invention, the above-mentioned object is to control a control system by extracting a current from the input voltage in order to supply power to the control system of the output voltage from the input voltage side at the time of starting the stabilized power supply. An always-on field effect transistor to be supplied to the control system, a voltage limiting means for limiting the power supply voltage to the control system to a set value or less, and a capacitor constantly charged by the power supply voltage are provided, and the power supply voltage is necessary for the operation of the control system. After reaching such a predetermined value, it is achieved by applying a gate bias to the field effect transistor to reduce the current flowing therein.

【0010】上記構成中の常時導通形の電界効果トラン
ジスタには、接合形電界効果トランジスタやディプリー
ション形電界効果トランジスタを用いることができ、電
圧制限手段には、ツェナーダイオード等の定電圧回路素
子を利用するのが好適である。また、安定化電源の起動
後には本発明の起動回路から制御系の消費電力を供給す
ることも可能であるが、従来と同様に安定化電源の補助
出力からこの消費電流を供給するのが望ましく、この場
合は起動後に電界効果トランジスタに対しそれをピンチ
オフ状態にするようにゲートバイアスを掛けるのがよ
い。
A junction field effect transistor or a depletion type field effect transistor can be used as the always conducting field effect transistor in the above structure, and the voltage limiting means is a constant voltage circuit element such as a Zener diode. Is preferably used. Further, it is possible to supply the power consumption of the control system from the starting circuit of the present invention after starting the stabilized power supply, but it is desirable to supply this consumption current from the auxiliary output of the stabilized power supply as in the conventional case. In this case, it is preferable to apply a gate bias to the field effect transistor so as to bring it into a pinch-off state after starting.

【0011】電界効果トランジスタにその電流を絞るよ
うにゲートバイアスを掛けるには、例えばそのドレイン
に入力電圧を与えかつそのソースを制御系に対する給電
点に接続した状態でゲートを接地することにより、安定
化電源の起動時に給電電圧が立ち上がったときそれを利
用して電界効果トランジスタのゲートに逆バイアスを掛
けることでよい。なお、安定化電源がスイッチング電源
であってスイッチングトランジスタを制御系とともに1
チップの集積回路に組み込む場合は、本発明の起動回路
も同じチップ内に組み込むのが、常時導通形の電界効果
トランジスタをスイッチングトランジスタと共通の工程
で作り込める点で有利である。
In order to apply a gate bias to the field effect transistor so as to reduce its current, for example, by applying an input voltage to its drain and grounding the gate with its source connected to the feeding point for the control system, stability is achieved. The reverse bias may be applied to the gate of the field effect transistor by utilizing the rise of the power supply voltage at the time of activation of the switching power supply. In addition, the stabilizing power supply is a switching power supply, and the switching transistor is used together with the control system.
When incorporated in an integrated circuit of a chip, it is advantageous to incorporate the start-up circuit of the present invention in the same chip because a field-effect transistor of a constant conduction type can be manufactured in the same process as a switching transistor.

【0012】[0012]

【作用】本発明は電界効果トランジスタが低いオン抵抗
状態から高いオフ抵抗状態までゲートにより容易に制御
できる点に着目して従来の給電用抵抗のかわりにこれを
用い、かつそれを常時導通形とすることによって安定化
電源の起動開始時にその低抵抗状態によりキャパシタの
充電を促進し,かつ電圧制限手段により上限値を制限し
ながら制御系に対する給電電圧の立ち上がりを速め、給
電電圧が制御系の動作に必要な所定値に達した後はゲー
トバイアスにより電界効果トランジスタを高抵抗状態に
してそれに流れる電流を絞ることにより、給電電圧より
入力電圧がずっと高くなる安定化電源の運転中に起動回
路に発生する電力損失を従来回路と比べて無視できる程
度にまで減少させるものである。
The present invention uses the field-effect transistor in place of the conventional resistance for power supply, and pays attention to the fact that the field-effect transistor can be easily controlled by the gate from a low on-resistance state to a high off-resistance state, and makes it a continuous conduction type. By so doing, the charging of the capacitor is promoted due to its low resistance state at the start of starting the stabilized power supply, and the rising of the power supply voltage to the control system is accelerated while the upper limit value is limited by the voltage limiting means, and the power supply voltage operates as the control system operates. After reaching the predetermined value required for the gate bias, the field effect transistor is put into a high resistance state and the current flowing through it is throttled, so that the input voltage is much higher than the power supply voltage. The power loss is reduced to a negligible level compared with the conventional circuit.

【0013】[0013]

【実施例】以下、図を参照しながら本発明の実施例を説
明する。図1は図4と同じ要領で本発明の実施例を示す
もので、同図(a) は本発明の起動回路を含む安定化電源
の回路図,同図(b) は起動回路の電界効果トランジスタ
に流れる電流の特性線図であり、図4に対応する部分に
は同じ符号が付けられているので重複部分に対する説明
は適宜に省略することとする。図2は本発明回路に接合
形の電界効果トランジスタを利用する場合に関し、同図
(a) はその構造例を,同図(b) はこれと対比してDMO
S形のスイッチングトランジスタの構造例をそれぞれ示
す集積回路のチップの要部拡大断面図である。図3は本
発明回路にディプリーション形の電界効果トランジスタ
を利用する場合のその構造例を図2(a) と同じ要領で示
す集積回路のチップの要部拡大断面図である。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention in the same manner as FIG. 4, where FIG. 1 (a) is a circuit diagram of a stabilized power supply including a starting circuit of the present invention, and FIG. 1 (b) is a field effect of the starting circuit. FIG. 6 is a characteristic diagram of a current flowing through a transistor, and the portions corresponding to those in FIG. 4 are denoted by the same reference numerals, and the description of the overlapping portions will be appropriately omitted. FIG. 2 shows the case where a junction type field effect transistor is used in the circuit of the present invention.
Figure (a) shows an example of the structure, and Figure (b) compares it with DMO.
It is a principal part expanded sectional view of the chip of an integrated circuit which each shows the constructional example of an S-type switching transistor. FIG. 3 is an enlarged cross-sectional view of a main part of an integrated circuit chip showing an example of the structure in the case where a depletion type field effect transistor is used in the circuit of the present invention in the same manner as FIG. 2 (a).

【0014】図1(a) に示す安定化電源はフライバック
形の変圧器3を用いるスイッチング電源であって主回路
の構成は前に説明した図4(a) と同じであるが、この実
施例ではスイッチングトランジスタ4が本発明の起動回
路とともに制御系10用の集積回路装置30の図では一点鎖
線で囲んで示すチップ内に組み込まれ、さらに図示の例
では変圧器3の補助コイル3cの誘起電圧を受ける補助出
力用のダイオード7もこれに組み込まれる。スイッチン
グトランジスタ4は入力電圧Viが例えば310Vの場合、そ
れに対するマージンと変圧器3の一次コイル3aに発生す
る逆起電力とをこれに加えて 600〜650V程度の高耐圧が
必要になるので、DMOSないしは二重拡散形の電界効
果トランジスタとするの通例である。
The stabilized power supply shown in FIG. 1 (a) is a switching power supply using a flyback type transformer 3 and the main circuit has the same configuration as that shown in FIG. In the example, the switching transistor 4 is incorporated together with the starting circuit of the present invention in the chip of the integrated circuit device 30 for the control system 10 which is surrounded by a dot-dash line in the figure, and further, in the example shown, the induction of the auxiliary coil 3c of the transformer 3 is induced. The diode 7 for the auxiliary output which receives the voltage is also incorporated therein. When the input voltage Vi is, for example, 310V, the switching transistor 4 needs a high withstand voltage of about 600 to 650V in addition to the margin for the input voltage Vi and the counter electromotive force generated in the primary coil 3a of the transformer 3, so that the DMOS is required. Or, it is customary to use a double diffusion type field effect transistor.

【0015】駆動回路は従来の給電抵抗に代わる常時導
通形の電界効果トランジスタ20と,従来と同じキャパシ
タ8と, 電圧制限手段9とから構成され、この図1の実
施例では電界効果トランジスタ20には接合形電界効果ト
ランジスタを用い、かつ電圧制限手段9には従来と同じ
ツェナーダイオードを用いる。接合形電界効果トランジ
スタ20は例えばそのドレインに入力電圧Viを受け、ソー
スを制御系10に対する給電点に接続し、かつゲートを図
のように接地して給電電圧Vsが確立された時に逆バイア
スが掛かるようにするのがよい。また、ダイオード7と
キャパシタ8と電圧制限手段9はもちろん上述の給電点
に接続する。なお、入力電圧Viが前述のように310Vの場
合、接合形電界効果トランジスタ20にマージンを見て45
0V程度の耐圧値をもたせるのがよい。
The drive circuit is composed of a field effect transistor 20 of a constant conduction type which replaces the conventional feeding resistor, a capacitor 8 which is the same as the conventional one, and a voltage limiting means 9. In the embodiment of FIG. Is a junction field effect transistor, and the voltage limiting means 9 is the same Zener diode as the conventional one. For example, the junction field effect transistor 20 receives an input voltage Vi at its drain, has its source connected to a feeding point for the control system 10, and has its gate grounded as shown to establish a reverse bias when the feeding voltage Vs is established. It is better to hang it. Further, the diode 7, the capacitor 8 and the voltage limiting means 9 are of course connected to the above-mentioned feeding point. When the input voltage Vi is 310V as described above, the junction field-effect transistor 20 has a margin of 45V.
It is desirable to have a breakdown voltage value of about 0V.

【0016】安定化電源の起動に際してスイッチSwを投
入すると図1(a) の電圧vが所定の入力電圧値Viに向け
て立ち上がって行き、この立ち上がりの初期に常時導通
形の電界効果トランジスタ20を流れる電流iによりキャ
パシタ8が電圧制限手段9により設定される給電電圧Vs
にまで充電されるが、本発明の起動回路では電界効果ト
ランジスタ20のオン抵抗値が図4の抵抗Rよりかなり低
いので従来より大きな電流iにより給電電圧Vsの立ち上
がりと制御系10への電流の供給が促進される。このた
め、電圧vが給電電圧Vsの付近にまで立ち上がる時点で
制御系10が動作を開始してスイッチングトランジスタ4
をオンオフ制御するので、補助コイル3c側からダイオー
ド7を介し図1(b) では破線で示された電流isの制御系
10に対する供給が開始される。
When the switch Sw is turned on at the time of starting the stabilized power supply, the voltage v shown in FIG. 1 (a) rises toward a predetermined input voltage value Vi, and the normally-conducting field effect transistor 20 is turned on at the beginning of this rise. The power supply voltage Vs which is set by the voltage limiting means 9 in the capacitor 8 by the flowing current i
However, in the starting circuit of the present invention, since the on-resistance value of the field effect transistor 20 is considerably lower than the resistance R of FIG. 4, a larger current i than the conventional one causes the rise of the feeding voltage Vs and the current to the control system 10. Supply is promoted. Therefore, the control system 10 starts operating at the time when the voltage v rises up to near the power supply voltage Vs, and the switching transistor 4
Is controlled on and off, the control system for the current is indicated by the broken line in FIG. 1 (b) via the diode 7 from the auxiliary coil 3c side.
Supply to 10 is started.

【0017】一方、給電電圧Vsの立ち上がりと同時に電
界効果トランジスタ20のゲートに逆バイアスが掛かるの
で、これにより電流iが絞られて補助出力側から制御系
10に上述の電流isの供給が開始されるに伴って図のよう
にピークipの経過後は急速に小さな一定電流icにまで減
少し、この状態が電圧vが所定の入力電圧値Viに立ち上
がるまで, およびそれ以降の安定化電源の運転中を通じ
て保持される。これを図4(b) の電流iの特性と比較す
ると、本発明により安定化電源の定常運転中に起動回路
に流れる電流iを従来よりも格段に減少させ得ることが
わかる。また、これに伴い電圧制限手段9は給電電圧Vs
を設定値以下に保つ役目だけを果たせばよく、従来のよ
うに運転中に大電流を流す必要がなくなる。
On the other hand, since a reverse bias is applied to the gate of the field effect transistor 20 at the same time when the power supply voltage Vs rises, the current i is throttled by this, and the control system is controlled from the auxiliary output side.
As shown in the figure, as the supply of the above-mentioned current is started at 10, after the peak ip has elapsed, it rapidly decreases to a small constant current ic, and this state causes the voltage v to rise to a predetermined input voltage value Vi. It is maintained until and after the operation of the stabilized power supply. Comparing this with the characteristics of the current i shown in FIG. 4 (b), it can be seen that the present invention can significantly reduce the current i flowing in the starting circuit during the steady operation of the stabilized power supply as compared with the conventional case. Further, along with this, the voltage limiting means 9 causes the power supply voltage Vs
Need only fulfill the role of keeping the value below the set value, and there is no need to supply a large current during operation as in the conventional case.

【0018】この図1の実施例では、安定化電源の運転
中に制御系10が消費する電流が補助出力側から一定の電
流isとして供給されるので、電界効果トランジスタ20を
そのゲートに掛かる逆バイアスにより運転中はいわゆる
ピンチオフ状態にして前述の一定電流icをごく低いレベ
ルに絞るのが有利であり、この実施態様では運転中の起
動回路内の電力損失を制御系10の消費電力の数〜10分の
1に減少させることができる。なお、補助出力が省かれ
る場合は、電界効果トランジスタ20をもちろんゲートバ
イアスを受けた状態でそれに流す電流iを制御系10の消
費電流値に絞るよう容易に構成することができる。
In the embodiment of FIG. 1, since the current consumed by the control system 10 is supplied as a constant current is from the auxiliary output side during the operation of the stabilized power supply, the field effect transistor 20 is reversely applied to its gate. It is advantageous to make the so-called pinch-off state during operation by the bias to narrow down the above-mentioned constant current ic to a very low level, and in this embodiment, the power loss in the starting circuit during operation is reduced to the number of power consumptions of the control system 10. It can be reduced to 1/10. When the auxiliary output is omitted, it is possible to easily configure the field effect transistor 20 so that the current i flowing in the gate biased state is narrowed down to the current consumption value of the control system 10.

【0019】図2(a) に図1の接合形の電界効果トラン
ジスタ20の具体構造例を示す。この実施例では電界効果
トランジスタ20を集積回路装置30のチップ内にスイッチ
ングトランジスタ4とともに組み込むので、それを図2
(b) に示されたスイッチングトランジスタ4のDMOS
構造と類似の構造として共通工程で作り込めるようにす
る。このため、図2(b) のDMOS構造をまず説明す
る。集積回路装置30用のの基板31には例えばp形の 100
〜200 Ωcmの高抵抗性のものを用い、その表面にL0COS
膜32を付けてそれによって取り囲まれた範囲内にn形の
ウエル21を例えば1016原子/cm3 の不純物濃度で数μm
の深さに拡散する。次にウエル21の表面の所定個所の上
にゲート22を薄いゲート酸化膜22aを介して配設した上
で、p形のチャネル層23とオフセット層25を拡散する。
前者は1017原子/cm3 程度の不純物濃度で例えば 1.5μ
mの深さに, 後者は1016原子/cm3 程度の不純物濃度で
やや浅い1μmの深さにそれぞれ作り込まれる。
FIG. 2A shows an example of a concrete structure of the junction type field effect transistor 20 of FIG. In this embodiment, the field effect transistor 20 is incorporated in the chip of the integrated circuit device 30 together with the switching transistor 4, so that
DMOS of switching transistor 4 shown in (b)
The structure will be similar to the structure so that it can be created in a common process. Therefore, the DMOS structure of FIG. 2B will be described first. The substrate 31 for the integrated circuit device 30 has, for example, a p-type 100
Use a high resistance material of ~ 200 Ωcm and L0COS on the surface.
An n-type well 21 is provided within a range surrounded by the film 32 and having an impurity concentration of, for example, 10 16 atoms / cm 3 of several μm.
Diffuse to the depth of. Next, a gate 22 is provided on a predetermined portion of the surface of the well 21 via a thin gate oxide film 22a, and then a p-type channel layer 23 and an offset layer 25 are diffused.
The former has an impurity concentration of about 10 17 atoms / cm 3 and is , for example, 1.5 μm.
The latter is made to have a shallow depth of 1 μm with an impurity concentration of about 10 16 atoms / cm 3 .

【0020】さらに、ゲート22の両側にn形のソース層
26を1020原子/cm3 以上の高不純物濃度で 0.5μm程度
の深さに拡散し、かつ同時にドレイン用のコンタクト層
28を同じn形でかつ同じ不純物濃度および深さで拡散す
る。次にアルミの電極膜33を要所に配設してチャネル層
23とソース層26からソース端子Sを, コンタクト層28か
らドレイン端子Dをそれぞれ導出しかつゲート22からゲ
ート端子Gを導出して図示の完成状態とする。
Further, an n-type source layer is provided on both sides of the gate 22.
26 is diffused at a high impurity concentration of 10 20 atoms / cm 3 or more to a depth of about 0.5 μm, and at the same time, a contact layer for drain.
Diffuse 28 with the same n-type and the same impurity concentration and depth. Next, the aluminum electrode film 33 is arranged in the required places to form the channel layer.
The source terminal S is derived from 23 and the source layer 26, the drain terminal D is derived from the contact layer 28, and the gate terminal G is derived from the gate 22 to complete the illustrated state.

【0021】このDMOSトランジスタ4はnチャネル
形であり、通例のようにそのソース端子Sを接地しドレ
イン端子Dを変圧器3の一次コイル3aに接続した状態で
使用する。ゲート端子Gに正の制御電圧を受けたときゲ
ート22の下のチャネル層23の表面に形成されるチャネル
を介しソース端子Sから電子電流がドレイン端子Dに流
れる。また、オフ時には空乏層がチャネル層23に対する
二重拡散層であるオフセット層25の下側のウエル41内に
主に広がって数百Vの高耐圧が得られる。このトランジ
スタ4には1A程度ないしそれ以上の電流容量を賦与で
き、数百kHzの高周波でスイッチング動作を行なわせる
ことができる。
The DMOS transistor 4 is an n-channel type, and is used in a state where the source terminal S is grounded and the drain terminal D is connected to the primary coil 3a of the transformer 3 as usual. When the gate terminal G receives a positive control voltage, an electron current flows from the source terminal S to the drain terminal D through the channel formed on the surface of the channel layer 23 below the gate 22. Further, at the time of off, the depletion layer mainly spreads in the well 41 below the offset layer 25, which is a double diffusion layer for the channel layer 23, and a high breakdown voltage of several hundred V is obtained. The transistor 4 can be provided with a current capacity of about 1 A or more, and a switching operation can be performed at a high frequency of several hundred kHz.

【0022】図2(a) に示す接合形電界効果トランジス
タ20は、このDMOS構造と同様にn形のウエル21とp
形のオフセット層25を図示のように備え、トランジスタ
4のチャネル層23のかわりにp形のゲート層24を,ソー
ス層26のかわりにn形のコンタクト層27をそれぞれそれ
らと共通の工程で拡散した上で、電極膜33を配設してコ
ンタクト層27と28からソース端子Sとドレイン端子Dを
それぞれ導出し、かつゲート層24からゲート端子Gを導
出してなる。
The junction field effect transistor 20 shown in FIG. 2 (a) has an n-type well 21 and a p-type well 21 similar to the DMOS structure.
Type offset layer 25 is provided as shown in the figure, and a p-type gate layer 24 is diffused in place of the channel layer 23 of the transistor 4 and an n-type contact layer 27 is diffused in place of the source layer 26 in the same process. Then, the electrode film 33 is provided to lead out the source terminal S and the drain terminal D from the contact layers 27 and 28, respectively, and lead out the gate terminal G from the gate layer 24.

【0023】かかる構造の電界効果トランジスタ20はド
レイン端子Dに入力電圧Viを受ける状態で使用され、安
定化電源の起動当初のゲート端子Gにバイアスが掛から
ない状態ではそのソース端子Sとドレイン端子Dの間が
導通した常時導電形のいわば1個の抵抗体として前述の
電流iを流すが、その後にバイアスがゲート端子Gに掛
かるとp形のゲート層24およびオフセット層25から下側
のn形のウエル21内に空乏層が縦方向に延びて電流iを
絞って行き、そのソース端子Sに給電電圧Vsが掛かって
ゲート端子Gがその分逆バイアスされると、例えば前述
のようにピンチオフの状態に入って電流iをごく僅かな
値にまで絞り、この状態を安定化電源の運転中を通じて
もちろん保持する。
The field-effect transistor 20 having such a structure is used in a state in which the drain terminal D receives the input voltage Vi, and the source terminal S and the drain terminal D thereof are not biased to the gate terminal G when the stabilized power source is started. The current i described above flows as a constant-conductivity-type resistor which is electrically connected between the two, but when a bias is applied to the gate terminal G after that, the n-type on the lower side from the p-type gate layer 24 and the offset layer 25. When a depletion layer extends vertically in the well 21 of FIG. 2 and narrows the current i, and the source terminal S is applied with the power supply voltage Vs and the gate terminal G is reverse biased by that amount, for example, as described above, pinch-off occurs. After entering the state, the current i is narrowed down to a very small value, and this state is of course maintained throughout the operation of the stabilized power supply.

【0024】以上のように、図2(a) の接合形の電界効
果トランジスタ20はDMOS構造のスイッチングトラン
ジスタ4とともに共通の工程で集積回路装置30に容易に
組み込むことができ、そのソース端子Sを制御系10に対
する給電点に接続してゲート端子Gを接地するだけで安
定化電源の起動後および運転中にそれに流れる電流を充
分に絞り込むことができる。なお、この電界効果トラン
ジスタ20では、前述のプリセット層24の横方向長さによ
りそのピンチオフ状態で必要な数百Vの耐圧を適宜設定
することができる。また、その電流容量は比較的少なく
てよいので図の前後方向の寸法が小で横方向に細長な形
状に形成することでよい。
As described above, the junction-type field effect transistor 20 shown in FIG. 2A can be easily incorporated into the integrated circuit device 30 in the same process as the switching transistor 4 having the DMOS structure, and the source terminal S thereof can be incorporated. The current flowing through the stabilized power supply after starting and during operation can be sufficiently narrowed down only by connecting the gate terminal G to the power supply point for the control system 10 and grounding the gate terminal G. In this field effect transistor 20, the withstand voltage of several hundreds of V required in the pinch-off state can be appropriately set by the lateral length of the preset layer 24 described above. Further, since the current capacity thereof may be relatively small, it may be formed in a laterally elongated shape having a small dimension in the front-back direction in the drawing.

【0025】図3の態様では常時導通形の電界効果トラ
ンジスタ20をディプリーション形に構成する。図からわ
かるようにこのディプリーション形トランジスタ20の構
造は図2(b) のDMOS構造とゲート22の下側にn形の
チャネル導通層29を拡散した点が異なるのみであり、こ
のチャネル導通層29は例えば1016〜1017原子/cm3 の不
純物濃度で 0.5μm以下の深さに拡散するのがよい。こ
のディプリーション形電界効果トランジスタ20でも、そ
のゲート端子Gにバイアスが掛からない状態で導通して
電流iを流す抵抗として機能し、これに給電電圧Vsが逆
バイアスとして掛かるとチャネル導通層29のチャネルを
導通させる効果が減殺されるので非導通状態ないしそれ
に近くなって電流iを絞り、安定化電源の運転中を通じ
この電流制限状態を保持する。このように図3の態様で
は、常時導通形の電界効果トランジスタをスイッチング
トランジスタとほとんど同じ構造にして集積回路への組
み込みを容易にし、チャネル導通層29の表面の不純物濃
度を適切に設定することによって電流iに対する絞り効
果を容易に制御できる。
In the embodiment of FIG. 3, the field effect transistor 20 of the always conducting type is constructed in the depletion type. As can be seen from the figure, the structure of this depletion type transistor 20 is different from the DMOS structure of FIG. 2 (b) only in that an n-type channel conductive layer 29 is diffused below the gate 22. The layer 29 is preferably diffused to a depth of 0.5 μm or less with an impurity concentration of 10 16 to 10 17 atoms / cm 3 , for example. The depletion type field effect transistor 20 also functions as a resistor that conducts in a state where the gate terminal G is not biased and allows the current i to flow, and when the feed voltage Vs is applied as a reverse bias to the channel conduction layer 29. Since the effect of conducting the channel is diminished, the current i is throttled in the non-conducting state or close to the non-conducting state, and this current limiting state is maintained throughout the operation of the stabilized power supply. As described above, according to the embodiment of FIG. 3, the field-effect transistor of the always conducting type has almost the same structure as the switching transistor to facilitate the incorporation into the integrated circuit, and the impurity concentration on the surface of the channel conducting layer 29 is appropriately set. The diaphragm effect for the current i can be easily controlled.

【0026】[0026]

【発明の効果】以上説明したとおり本発明の起動回路で
は、安定化電源の起動時に出力電圧の制御系に入力電圧
側から給電するため、入力電圧側から電流を抽出して制
御系に供給する常時導通形の電界効果トランジスタと,
制御系に対する給電電圧を所定設定値以下に制限する電
圧制限手段と, 給電電圧により充電されるキャパシタを
設け、給電電圧が制御系の動作に必要な所定値に達した
状態では電界効果トランジスタに対しゲートバイアスを
掛けてそれに流れる電流を絞ることにより、次の効果を
上げることができる。
As described above, in the start-up circuit of the present invention, the control system for the output voltage is supplied from the input voltage side when the stabilized power supply is started, so that the current is extracted from the input voltage side and supplied to the control system. An always-on field effect transistor,
A voltage limiting means for limiting the power supply voltage to the control system to a predetermined value or less and a capacitor charged by the power supply voltage are provided, and when the power supply voltage reaches the predetermined value necessary for the operation of the control system, By applying a gate bias and narrowing the current flowing through it, the following effects can be achieved.

【0027】(a) 常時導通形の電界効果トランジスタを
低抵抗の状態から高抵抗の状態までゲートバイアスによ
って容易に制御できることを利用して、安定化電源の起
動後および運転中にそれに流れる電流を減少させ、起動
回路の電力損失を従来回路と比べて無視できる程度にま
で減少させることができる。 (b) 常時導通形の電界効果トランジスタの導通時の比較
的低いオン抵抗を利用して安定化電源の起動開始時にキ
ャパシタの充電を促進しながら制御系に対する給電電圧
の立ち上がりを速めて安定化電源の起動時間を短縮でき
る。
(A) Taking advantage of the fact that a normally conducting field-effect transistor can be easily controlled by a gate bias from a low resistance state to a high resistance state, the current flowing through the stabilized power supply after starting and during operation is The power loss of the starting circuit can be reduced to a negligible level as compared with the conventional circuit. (b) A stabilized power supply that accelerates the rise of the power supply voltage to the control system while accelerating the charging of the capacitor at the start of starting the stabilized power supply by using the relatively low on-resistance when the field-effect transistor of the always-on type is on The startup time of can be shortened.

【0028】(c) 安定化電源の運転中に起動回路に流れ
る電流が減少するため従来のように制御系の消費電流を
越す余分な電流が電圧制限手段に流れ込むことがなくな
り、電圧制御手段の電流負担を軽減してそれ用のツェナ
ーダイオード等の電流容量を従来より小さく設定するこ
とができる (d) 常時導通形の電界効果トランジスタとして接合形や
ディプリーション形の電界効果トランジスタを用いるこ
とにより、DMOS構造のスイッチングトランジスタと
ともに制御系用の集積回路装置内に組み込む際に共通の
工程で容易かつ経済的に作り込むことができる。
(C) Since the current flowing through the starter circuit during the operation of the stabilized power supply decreases, an extra current exceeding the current consumption of the control system does not flow into the voltage limiting means as in the conventional case, and the voltage controlling means operates. The current load can be reduced and the current capacity of the Zener diode for it can be set smaller than before. (D) By using a junction type or depletion type field effect transistor as an always conducting field effect transistor. , The DMOS structure and the switching transistor can be easily and economically manufactured in a common process when incorporated in an integrated circuit device for a control system.

【0029】このように本発明は、起動回路内の電力損
失を従来と比べて無視できる程度にまで減少させて安定
化電源の電力変換効率を向上させ、起動時間を短縮して
その性能を改善し、さらには起動回路とスイッチングト
ランジスタを制御系とともに1チップの集積回路に組み
込んで経済性を高める著効を奏するものである。
As described above, according to the present invention, the power loss in the starting circuit is reduced to a negligible level as compared with the conventional case, the power conversion efficiency of the stabilized power source is improved, and the starting time is shortened to improve its performance. In addition, the starter circuit and the switching transistor are incorporated into a one-chip integrated circuit together with the control system, which is highly effective in increasing the economical efficiency.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による安定化電源用起動回路の実施例を
示し、同図(a) は本発明回路を含む安定化電源の回路
図,同図(b) は起動回路の電界効果トランジスタに流れ
る電流の特性線図である。
1 shows an embodiment of a starting circuit for a stabilized power supply according to the present invention, FIG. 1 (a) is a circuit diagram of a stabilized power supply including the circuit of the present invention, and FIG. 1 (b) is a field effect transistor of the starting circuit. It is a characteristic diagram of flowing current.

【図2】本発明回路を構成する常時導電形の電界効果ト
ランジスタとして接合形の電界効果トランジスタを用い
る実施例に関し、同図(a) はその構造例を,同図(b) は
これと対比してDMOS形のスイッチングトランジスタ
の構造例をそれぞれ示す集積回路のチップの要部拡大断
面図である。
FIG. 2 relates to an embodiment in which a junction type field effect transistor is used as a field effect transistor of a constant conductivity type which constitutes a circuit of the present invention. FIG. 2A is a structural example thereof, and FIG. FIG. 4 is an enlarged cross-sectional view of a main part of a chip of an integrated circuit showing a structural example of a DMOS type switching transistor.

【図3】本発明回路を構成する常時導電形の電界効果ト
ランジスタにディプリーション形電界効果トランジスタ
を利用する場合のその構造例を示す集積回路のチップの
要部拡大断面図である。
FIG. 3 is an enlarged cross-sectional view of a main part of an integrated circuit chip showing an example of the structure when a depletion type field effect transistor is used as the always conductive type field effect transistor constituting the circuit of the present invention.

【図4】従来技術による起動回路の例を示し、同図(a)
は起動回路を含む安定化電源の回路図,同図(b) は起動
回路の給電抵抗に流れる電流の特性線図である。
FIG. 4 is a diagram showing an example of a starting circuit according to the related art, and FIG.
Is a circuit diagram of the stabilized power supply including the starter circuit, and Fig. 6 (b) is a characteristic diagram of the current flowing through the power supply resistance of the starter circuit.

【符号の説明】[Explanation of symbols]

8 起動回路を構成するキャパシタ 9 起動回路を構成する電圧制限手段 10 制御系 20 起動回路を構成する常時導通形の電界効果トラ
ンジスタ i 起動回路に流れる電流 Vi 安定化電源の入力電圧 Vo 安定化電源の出力電圧 Vs 制御系に対する給電電圧
8 Capacitor constituting start-up circuit 9 Voltage limiting means constituting start-up circuit 10 Control system 20 Field effect transistor of conduction type constituting start-up circuit i Current flowing in start-up circuit Vi Stabilized power supply input voltage Vo Stabilized power supply Output voltage Vs Power supply voltage for control system

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】安定化電源の起動時に出力電圧の制御系に
対し入力電圧側から給電するための回路であって、入力
電圧側から電流を抽出して制御系に供給する常時導通形
の電界効果トランジスタと、制御系に対する給電電圧を
所定の設定値以下に制限する電圧制限手段と、給電電圧
により常時充電されるキャパシタとを備えてなり、給電
電圧が制御系の動作に必要な所定値に達した状態では電
界効果トランジスタに対しゲートバイアスを掛けてそれ
に流れる電流を絞るようにしたことを特徴とする安定化
電源用起動回路。
1. A circuit for supplying power to a control system of an output voltage from an input voltage side at the time of starting a stabilized power supply, wherein a current is extracted from the input voltage side and supplied to the control system. An effect transistor, a voltage limiting means for limiting the power supply voltage to the control system to a predetermined set value or less, and a capacitor constantly charged by the power supply voltage are provided, and the power supply voltage becomes a predetermined value necessary for the operation of the control system. In the reached state, the starting circuit for the stabilized power supply is characterized in that the gate bias is applied to the field effect transistor so that the current flowing therein is narrowed.
【請求項2】請求項1に記載の回路において、安定化電
源の起動後にはその補助出力電圧を制御系に給電するよ
うにし、かつ電界効果トランジスタにゲートバイアスを
掛けてピンチオフの状態に入れるようにしたことを特徴
とする安定化電源用起動回路。
2. The circuit according to claim 1, wherein after activation of the stabilized power supply, the auxiliary output voltage of the stabilized power supply is supplied to the control system, and the field effect transistor is gate-biased to be in a pinch-off state. The starting circuit for the stabilized power supply is characterized in that
【請求項3】請求項1に記載の回路において、電界効果
トランジスタとして常時導通形の接合形電界効果トラン
ジスタが用いられることを特徴とする安定化電源用起動
回路。
3. The stabilized power supply start-up circuit according to claim 1, wherein a normally conductive junction field effect transistor is used as the field effect transistor.
JP23064793A 1993-09-17 1993-09-17 Stabilized power supply starting circuit Pending JPH0787733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23064793A JPH0787733A (en) 1993-09-17 1993-09-17 Stabilized power supply starting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23064793A JPH0787733A (en) 1993-09-17 1993-09-17 Stabilized power supply starting circuit

Publications (1)

Publication Number Publication Date
JPH0787733A true JPH0787733A (en) 1995-03-31

Family

ID=16911076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23064793A Pending JPH0787733A (en) 1993-09-17 1993-09-17 Stabilized power supply starting circuit

Country Status (1)

Country Link
JP (1) JPH0787733A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10031191A1 (en) * 2000-06-27 2002-01-17 Infineon Technologies Ag Power supply unit, e.g. for discharge lamp, includes controlled semiconductors and capacity supplying current as function of output potential from more than one input potential
US7491611B2 (en) 2004-07-08 2009-02-17 Power Integrations, Inc. Method and apparatus for controlling a circuit with a high voltage sense device
JP2009177983A (en) * 2008-01-25 2009-08-06 Sharp Corp Switching power circuit
WO2010037455A1 (en) * 2008-10-01 2010-04-08 Robert Bosch Gmbh Voltage supply
CN102355134A (en) * 2011-09-23 2012-02-15 成都芯源系统有限公司 Switch conversion circuit and conversion method
US8144484B2 (en) 2003-05-27 2012-03-27 Power Integrations, Inc. Electronic circuit control element with tap element
WO2017075111A1 (en) * 2015-10-26 2017-05-04 Dialog Semiconductor Inc. Switching power converter with zero current at startup

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10031191A1 (en) * 2000-06-27 2002-01-17 Infineon Technologies Ag Power supply unit, e.g. for discharge lamp, includes controlled semiconductors and capacity supplying current as function of output potential from more than one input potential
US8264858B2 (en) 2003-05-27 2012-09-11 Power Integrations, Inc. Electronic circuit control element with tap element
US8611108B2 (en) 2003-05-27 2013-12-17 Power Integrations, Inc. Electronic circuit control element with tap element
US8144484B2 (en) 2003-05-27 2012-03-27 Power Integrations, Inc. Electronic circuit control element with tap element
US7491611B2 (en) 2004-07-08 2009-02-17 Power Integrations, Inc. Method and apparatus for controlling a circuit with a high voltage sense device
US7696566B2 (en) 2004-07-08 2010-04-13 Power Integrations, Inc. Method and apparatus for controlling a circuit with a high voltage sense device
US7872304B2 (en) 2004-07-08 2011-01-18 Power Integrations, Inc. Method and apparatus for controlling a circuit with a high voltage sense device
US8120097B2 (en) 2004-07-08 2012-02-21 Power Integrations, Inc. Method and apparatus for controlling a circuit with a high voltage sense device
US8236656B2 (en) 2004-07-08 2012-08-07 Power Integrations, Inc. Method and apparatus for controlling a circuit with a high voltage sense device
JP2009177983A (en) * 2008-01-25 2009-08-06 Sharp Corp Switching power circuit
WO2010037455A1 (en) * 2008-10-01 2010-04-08 Robert Bosch Gmbh Voltage supply
US8767412B2 (en) 2008-10-01 2014-07-01 Robert Bosch Gmbh Voltage supply
CN102355134A (en) * 2011-09-23 2012-02-15 成都芯源系统有限公司 Switch conversion circuit and conversion method
WO2017075111A1 (en) * 2015-10-26 2017-05-04 Dialog Semiconductor Inc. Switching power converter with zero current at startup
US10180697B2 (en) 2015-10-26 2019-01-15 Dialog Semiconductor Inc. Switching power converter with zero current at startup

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