JPH0787347B2 - Monostable multi vibrator - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monostable multivibrator triggered by rising and falling of an input signal.

[Outline of Invention]

This invention is a monostable multivibrator triggered by rising and falling of an input signal,
An emitter follower transistor is connected to a pair of output terminals of the differential circuit to which the input signal is supplied, and the value of the current source connected to each of the emitter follower transistors is set by an external resistor. A capacitor is connected to the capacitor, and an output signal is formed by using the voltage across the capacitor to reduce the number of elements and obtain good temperature characteristics.

[Conventional technology]

A bi-directional monostable multivibrator (hereinafter abbreviated as bi-directional monostable multi-vibrator) triggered by rising and falling of an input pulse signal has conventionally been configured as shown in FIG.

In FIG. 6, an input signal is supplied to the differentiating circuit 102 from the input terminal 101, and a differentiating pulse is output from the differentiating circuit 102 at the rising and falling edges of this input signal. This differential pulse is supplied to the monomulti 103, and the monomulti 103 is triggered by this differential pulse. The output of the monomulti 103 is taken out from the output terminal 104.

When the input signal shown in FIG. 7A is supplied to the input terminal 101, the differentiating circuit 10 rises and falls at the input signal.
The differential pulse is output from 2 as shown in FIG. 7B.
Mono Multi 103 is triggered by this differential pulse,
As shown in FIG. 9C, an output having a predetermined pulse width τ ₅₀ is output from the output terminal 104.

The differentiating circuit 102 is configured as shown in FIG. 8th
In the figure, one input terminal of the EX-OR gate 105 is
The input signal from the input terminal 106 is supplied, and the EX-OR gate 1
The other input terminal of 05 is connected to the delay circuit 107 from the input terminal 106.
An input signal delayed by a minute delay time τ ₆₀ is supplied via the. The output of the EX-OR gate 105 is output from the output terminal 108.

When the input signal shown in FIG. 9A is supplied to the input terminal 106, the input signal shown in FIG. 9A is supplied to one input terminal of the EX-OR gate 106, and the other of the EX-OR gate 106 is supplied. As shown in FIG. 9B, this input signal is supplied to the input terminal of with a delay of τ ₆₀ . Therefore, as shown in FIG. 9C, the differential pulse having the pulse width τ ₆₀ is output terminal 108.
Is output from.

When the above-mentioned differentiating circuit 102 is realized by ECL based on a differential circuit, a configuration as shown in FIG. 10 is obtained.

In FIG. 10, 111 and 112 denote transistors, the emitters of the transistors 111 and 112 are commonly connected, and this connection point is connected to one end of the current source 113. The other end of the current source 113 is connected to the ground terminal 114. Transistor
The base of 111 is connected to the input terminal 115. Transistor
The base of 112 is connected to the input terminal 116.

The collector of the transistor 111 receives a DC voltage via the resistor 117.
Connected to Vcc DC power supply terminal 119. Transistor 112
Is connected to the power supply terminal 119 via the resistor 118. The capacitor 120 is connected between the collector of the transistor 111 and the collector of the transistor 112.

The emitters of the transistors 121 and 122 are commonly connected, and this connection point is connected to one end of the current source 123. The other unit of the current source 123 is connected to the ground terminal 114. Transistor
The base of 121 is connected to the input terminal 115. Transistor
The base of 122 is connected to the input terminal 116.

The collector of the transistor 121 is connected to the emitters of the transistor 124 and the transistor 125. Transistor 122
Is connected to the emitters of the transistors 126 and 127. The bases of the transistor 124 and the transistor 127 are commonly connected to each other, and this connection point is connected to the collector of the transistor 112. Transistor 1
25 and the base of the transistor 126 are commonly connected to each other, and this connection point is connected to the collector of the transistor 111.

The collector of the transistor 124 and the collector of the transistor 126 are commonly connected to each other, and this connection point is connected to the power supply terminal 119 via the resistor 128. The collector of the transistor 125 and the collector of the transistor 127 are commonly connected, and this connection point is connected to the power supply terminal 119 via the resistor 129 and the base of the transistor 130.

The collector of the transistor 130 is connected to the power supply terminal 119. The emitter of the transistor 130 is connected to one end of the current source 131 and the output terminal 132. Current source 131
The other end of is connected to the ground terminal 114.

A delay circuit is configured by the differential circuit including the transistors 111 and 112 and the capacitor 120. That is, for example, when the input signal supplied to the input terminal 115 changes from a low level to a high level and the input terminal supplied to the input terminal 116 changes from a high level to a low level, the transistor 111 immediately turns on and the transistor Although 112 is turned off, the collector voltage of the transistor 112 gradually rises by charging the capacitor 120 with the current flowing through the resistor 118. Therefore, the time required for the output voltage output from the collectors of the transistors 111 and 112 to reach a predetermined level with respect to changes in the input signals supplied to the input terminals 115 and 116 is related to the time constant of the capacitor 120. Be late.

The differential circuit composed of the transistors 124 and 125, the differential circuit composed of the transistors 126 and 127, and the differential circuit composed of the transistors 121 and 122 connected to these differential circuits form a double balanced connection EX- The OR gate is configured.

That is, when a high level is supplied to the base of the transistor 121 and a low level is supplied to the base of the transistor 122, the transistor 121 is turned on and the transistor 122 is turned off. At this time, when a high level is supplied to the bases of the transistors 125 and 126 and a low level is supplied to the bases of the transistors 124 and 127, the transistor 125 is turned on and the transistor 124 is turned off. Therefore, the connection point of the collectors of the transistors 125 and 127 becomes low level, and the connection point of the collectors of the transistors 124 and 126 becomes high level.

When the transistor 121 is on and the transistor 122 is off, a high level is supplied to the bases of the transistors 124 and 127, and a low level is supplied to the bases of the transistors 125 and 126. 125 turns off. Therefore, the connection point of the collectors of the transistors 124 and 126 becomes low level, and the connection point of the collectors of the transistors 125 and 127 becomes high level.

When a high level is supplied to the base of the transistor 122 and a low level is supplied to the base of the transistor 121,
The transistor 122 is turned on and the transistor 121 is turned off. At this time, when a high level is supplied to the bases of the transistors 125 and 126 and a low level is supplied to the bases of the transistors 124 and 127, the transistor 126 is turned on,
The transistor 127 is turned off. Therefore, transistor 1
The connection point of the collectors of 24 and 126 goes low, and the connection point of the collectors of transistors 125 and 127 goes high.

When the transistor 122 is on and the transistor 121 is off, a high level is supplied to the bases of the transistors 124 and 127, and when a low level is supplied to the bases of the transistors 125 and 126, the transistor 127 is turned on and the transistor 126 turns off. Therefore, the connection point of the collectors of the transistors 125 and 127 becomes low level, and the connection point of the collectors of the transistors 124 and 126 becomes high level.

Input signals are supplied to the bases of the transistors 121 and 122 from the input terminals 115 and 116. Transistor 124 and
The connection point of the base of 127 and the connection point of the bases of the transistors 125 and 126 are the transistor 111 and the transistor 112.
The outputs of the collectors of are respectively supplied. Transistor 111
The outputs of the collectors of 112 and 112 gradually change as the capacitor 120 is charged and discharged, as described above. Therefore, when the input signal shown in FIG. 9A and its inverted input signal are supplied to the input terminals 115 and 116, the output signal shown in FIG. 9C is taken out from the output terminal 132.

By connecting the output terminal 132 to the trigger input terminal of the mono-multi, a bi-directional mono-multi is constructed.

[Problems to be solved by the invention]

In order to realize bi-directional mono-multi,
If the differentiating circuit that forms the differential pulse of the input signal is composed of ECL, a very large number of elements are required as shown in FIG. Therefore, there is a problem that the circuit scale of the bi-directional mono-multi which is formed by connecting the mono-multi to the differentiating circuit becomes very large.

In the circuit shown in FIG. 10, if the time constant of the capacitor 120 is appropriately set, a pulse having a predetermined width is output from the output terminal 132 at the rising and falling edges of the input signals supplied to the input terminals 115 and 116. It In this way, it is conceivable to construct a bi-directional mono-multi.

However, the charging current of the capacitor 120 flows through the resistor 117 or the resistor 118. Within the integrated circuit, the resistance value varies widely, and good temperature characteristics cannot be obtained. Therefore, even if the time constant of the capacitor 120 is changed to form the bi-directional mono-multi, good characteristics cannot be obtained.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a monostable multivibrator, which is suitable for integration into an integrated circuit, has a small number of elements, and has a good temperature characteristic and which is triggered by rising and falling of an input signal. .

[Means for solving problems]

The present invention connects a pair of output terminals of a differential circuit to which an input signal is supplied to an emitter follower transistor,
Connect a capacitor between the emitters of the emitter-follower transistor, connect a current source with the same current value to each emitter of the emitter-follower transistor, set the current value of the current source with an external resistor, and connect both ends of the capacitor. It is a monostable multivibrator that utilizes a voltage to form an output signal having a predetermined pulse width determined by a capacitor and an external resistor from the rising and falling edges of an input pulse.

[Action]

An emitter follower transistor is connected to each of the output terminals of the differential circuit to which the input signal is supplied, and a capacitor is connected between the emitters of the emitter follower transistor. When the input signal changes due to the terminal voltage of this capacitor, one emitter follower transistor turns off, and the emitter voltage of one emitter follower transistor becomes higher than the emitter voltage of the other emitter follower transistor by a voltage equal to the terminal voltage of this capacitor. Be lifted. The pulse width of the output pulse is determined by the time when the electric charge stored in the capacitor is gradually discharged and the emitter voltage of one emitter follower transistor falls to a predetermined level.

〔Example〕

Embodiments of the present invention will be described in the following order.

Structure of one embodiment b. Description of operation of one embodiment c. Structure of another embodiment d. Description of operation of another embodiment a. Structure of one embodiment FIG. 1 shows an embodiment of the present invention. It is shown. In FIG. 1, reference numerals 1 and 2 denote transistors, the emitters of the transistors 1 and 2 are commonly connected, and the connection point is connected to the collector of the transistor 3 that operates as a constant current source. The base of the transistor 3 is connected to the power supply terminal 4 of the reference voltage Vr. The emitter of the transistor 3 is connected to the connection terminal 6 via the resistor 5.

The base of the transistor 1 is connected to the input terminal 7. The base of the transistor 2 is connected to the input terminal 8. The collector of the transistor 1 is connected to the power supply terminal 11 of the DC voltage Vcc through the resistor 9 and the base of the emitter follower transistor 12. The collector of the transistor 2 is connected to the power supply terminal 11 via the resistor 10 and the base of the emitter follower transistor 13. The resistance values of the resistors 9 and 10 are set to the same value.

The collector of the emitter follower transistor 12 is the power supply terminal
Connected to 11. The emitter of the emitter follower transistor 12 is connected to the collector of the transistor 14 which operates as a constant current source. The collector of the emitter follower transistor 13 is connected to the power supply terminal 11. The emitter of the emitter follower transistor 13 is connected to the collector of the transistor 15 which operates as a constant current source. A capacitor 16 is connected between the emitters of the emitter follower transistors 12 and 13.

The base of the transistor 14 and the base of the transistor 15 are connected to the power supply terminal 4. The emitter of the transistor 14 and the emitter of the transistor 15 are connected to the resistance mounting terminal 17. An external resistor 18 is externally attached to the resistor mounting terminal 17.

Transistors in which the emitters of the transistors 21 and 22 are commonly connected and the connection point operates as a constant current source
Connected to 23 collectors. The base of the transistor 23 is connected to the power supply terminal 4. The emitter of the transistor 23 is connected to the ground terminal 6 via the resistor 24.

The collector of transistor 21 is connected to the emitters of transistors 25 and 26, and the collector of transistor 22 is connected to the emitters of transistors 27 and 28. Transistor
The base of 25 and the base of the transistor 28 are commonly connected,
This connection point is connected to the base of the emitter follower transistor 12. Base of transistor 26 and transistor
The bases of 27 are commonly connected, and this connection point is connected to the base of the emitter follower transistor 13.

The collector of the transistor 25 and the collector of the transistor 27 are commonly connected, this connection point is connected to the power supply terminal 11 via the resistor 29, and the output terminal 31 is derived from this connection point. The collector of the transistor 26 and the collector of the transistor 28 are commonly connected, this connection point is connected to the power supply terminal 11 via the resistor 30, and the output terminal 32 is derived from this connection point.

b. Description of Operation of One Embodiment The operation of this one embodiment will be described.

The output of the differential circuit composed of the transistors 1 and 2 is supplied to the emitter follower transistors 12 and 13, respectively.
A capacitor 16 is connected between the emitters of the emitter follower transistors 12 and 13, and these transistors 1 and 2 and the emitter follower transistors 12 and 1,
The capacitor 16 constitutes a delay circuit.

Double balanced by a differential circuit composed of transistors 25 and 26, a differential circuit composed of transistors 27 and 28, and a differential circuit composed of transistors 21 and 22 connected to these differential circuits. The connected EX-OR gate is configured.

In FIG. 2, before reaching time t ₀₁ , input terminal 7
Is supplied to the input terminal 8 and a low level is supplied to the input terminal 8. Therefore, as shown in FIG. 2A, the base voltage V ₁ of the transistor 1 becomes high level, the base voltage V ₂ of the transistor ₂ becomes low level, the transistor 1 is turned on, and the transistor 2 is turned off. As a result, as shown in FIG. 2B, the collector voltage V ₃ of the transistor 2 becomes high level and the collector voltage V ₄ of the transistor 1 becomes low level.

Since the transistor 2 is off, the collector voltage V ₃ of the transistor 2 at this time is V ₃ = Vcc, where Vcc is the power supply voltage supplied to the power supply terminal 11. On the other hand, the collector voltage V ₄ of the transistor 1, the resistance value of the resistor 9 R _9, when the current value set by the transistors 3 and the resistor 5 and I _1, the _{V 4 = Vcc-I 1 R} 9.

At this time, the emitter voltages V ₆ and V ₅ of the emitter follower transistors 12 and 13 are greater than those of the collector voltages V ₄ and V ₃ of the transistors 1 and 2, respectively.
A voltage lower than the base-emitter voltage V _{BE of} 13 is V ₆ = Vcc−I ₁ R ₉ −V _BE V ₅ = Vcc−V _BE .

A capacitor 16 is connected between the emitters of the emitter follower transistors 12 and 13, and the capacitor 16 stores electric charges. The voltage Vc across the capacitor 16 is the emitter follower transistors 12 and 13
It is found by the potential difference between the emitter voltages V ₆ and V ₅ of V.sub.2, and the voltage Vc across this is Vc = V ₅ −V ₆ = I ₁ R ₉ .

The emitter follower transistor 13 has an emitter voltage V ₅ (V ₅ = Vcc−V _BE ), and the emitter follower transistor 12
When the emitter voltage V ₆ is _{(V 6 = Vcc-I 1} R 9 -V BE) of,
The transistor 21 turns on and the transistor 22 turns off.
Moreover, the collector voltage V ₃ of the transistor 2 is (V ₃ = Vcc)
Then, the collector voltage V ₄ of the transistor 1 becomes (V ₄ = Vcc−I ₁ R
₉ ), transistor 26 turns on and transistor 2 turns on.
5 turns off. Therefore, as shown in FIG.
Before reaching ₀₁ , output Q taken from output terminal 32
Is low level, and the output taken out from the output terminal 31 is high level.

When the input changes at time t ₀₁ , a low level is supplied to the input terminal 7 and a high level is supplied to the input terminal 8, the second
As shown in FIG. A, the base voltage V ₁ of the transistor 1 becomes low level, the base voltage V ₂ of the transistor ₂ becomes high level, the transistor 1 is turned off, and the transistor 2 is turned on. Therefore, the resistance value of the resistor 10 is changed to R ₁₀ (=
R ₉ ), as shown in FIG. 2B, the transistor 2
The collector voltage V ₃ of the transistor becomes V ₃ = Vcc-I ₁ R ₁₀ , and the collector voltage V ₄ of the transistor 1 becomes V ₄ = Vcc.

At time t ₀₁ immediately after this input changes, as shown in FIG. 3, the electric charge accumulated before the time t ₀₁ remains in the capacitor 16. The emitter voltage V ₆ of the emitter follower transistor 12 is lower than this voltage V ₄ by the base-emitter voltage V _{BE of the} emitter follower transistor 12 because the collector voltage V ₄ of the transistor 1 is (V ₄ = Vcc). V ₆ = Vcc-V _BE . On the other hand, the emitter voltage V ₅ of the emitter follower transistor 13 becomes higher than the emitter voltage V ₆ of the emitter follower transistor 12 by that amount because the charge is stored in the capacitor 16. Since the voltage Vc across the capacitor 16 is (Vc = I ₁ R ₉ ) as described above, the emitter voltage V ₅ of the emitter follower transistor 13 is V ₅ = V ₆ + Vc = Vcc−V _BE + I ₁ R ₉ Becomes

The emitter voltage V ₅ of this emitter follower transistor 13
Is the collector voltage V ₃ (V ₃ = Vc) of the transistor 2 applied to the base of the emitter follower transistor 13 at this time.
c-I ₁ R ₁₀ ) higher. Therefore, the emitter follower transistor 13 is turned off immediately after the input is changed.

At time t ₀₁ immediately after this input changes, the emitter voltage V ₆ of the emitter follower transistor 12 becomes (V ₆ = Vcc−
V _BE ), the emitter voltage V ₅ of the emitter follower transistor 13 is (V ₅ = Vcc−V _BE + I ₁ R ₉ ), so that the transistor 21 is turned on and the transistor 22 is turned off. Since the collector voltage V ₃ of the transistor 2 is (V ₃ = Vcc-I ₁ R ₁₀ ) and the collector voltage V ₄ of the transistor 1 is (V ₄ = Vcc), the transistor 25 is turned on and the transistor 26 is turned off. . Therefore, as shown in FIG. 2D, the output Q changes to the high level and the output changes to the low level.

At the time (t _{01 to} t ₀₃ ), the emitter follower transistor
13 is off, and the electric charge stored in the capacitor 16 is the current I ₃ flowing through the transistor 15 as shown in FIG.
Is discharged by. Therefore, the emitter voltage V ₅ of the emitter follower transistor 13 gradually drops. When the emitter voltage V ₅ of the emitter follower transistor 13 becomes lower than the emitter voltage V ₆ of the emitter follower transistor 12 at the time t ₀₂ between the times (t _{01 to} t ₀₃ ), the transistor
22 turns on and transistor 21 turns off. At this time, the collector voltage V ₃ of the transistor 2 is (V ₃ = Vcc−I ₁ R ₁₀ ),
Since the collector voltage V ₄ of the transistor 1 is (V ₄ = Vcc), the transistor 28 turns on and the transistor 27 turns off. As a result, the output Q changes to the low level and the output changes to the high level at time t ₀₂ .

When the emitter follower transistor 13 is turned on at time t ₀₃ , the emitter voltage V ₅ of the emitter follower transistor 13
However, as shown in FIG. 2C, (V ₅ = Vcc−V _BE −I ₁ R ₁₀ ).
And the electric charge is stored in the capacitor 16.

At time t ₀₄ , the input changes and the base voltage of transistor 1, V
₁ goes high and the base voltage V _{2 of} transistor ₂
Goes low, the collector voltage of transistor 2
V ₃ becomes (V ₃ = Vcc), and the collector voltage V ₄ of the transistor 1 becomes (V ₄ = Vcc−I ₁ R ₉ ). Then, the emitter voltage V ₅ of the emitter follower transistor 13 becomes (V ₅ = Vcc−V
_BE ) and the emitter voltage V ₆ of the emitter follower transistor 12 is stored in the capacitor 16, so that the emitter voltage V ₅ of the emitter follower transistor 13 is
The more the capacitor 16 terminal voltage _{Vc (Vc = I 1 R 10} ) increased by a voltage _{(V 6 = Vcc-V BE} -I 1 R 10). Therefore, the emitter follower transistor 12 is turned off.

Since the emitter voltage V ₆ of the emitter follower transistor 12 is (V ₆ = Vcc−V _BE −I ₁ R ₁₀ ), and the emitter voltage V ₅ of the emitter follower transistor 13 is (V ₅ = Vcc−V _BE ), 22 turns on and transistor 21 turns off. The collector voltage V _{3 of} transistor 2 is (V ₃ = Vcc)
Then, the collector voltage V ₄ of the transistor 1 becomes (V ₄ = Vcc−I ₁ R
₉ ), transistor 27 turns on and transistor 28 turns off. Therefore, at time t ₀₄ , the output Q changes to the high level and the output changes to the high level.

The emitter voltage V ₆ of the emitter follower transistor 12 is
The current I ₂ flowing through the transistor 14 gradually decreases. When this voltage V ₆ becomes lower than the emitter voltage V ₅ (V ₅ = Vcc−V _BE ) of the emitter follower transistor 13, the transistor 21 turns on and the transistor 22 turns off. At this time, the collector voltage V ₃ of the transistor 2 is (V ₃ = Vcc)
Then, the collector voltage V ₄ of the transistor 1 is (V ₄ = Vcc−I ₁ R
₉ ), transistor 26 turns on and transistor 25 turns off. Therefore, at time t _{05 when} the emitter voltage V ₆ of the emitter follower transistor 12 becomes lower than the emitter voltage V ₅ of the emitter follower transistor 13, the output Q changes to the low level and the output changes to the high level.

When the emitter voltage V ₆ of the emitter follower transistor 12 drops to (V ₆ = Vcc−V _BE −I ₁ R ₉ ) at time t ₀₆ , the emitter follower transistor 12 turns on. Then, the emitter voltage V ₆ of the emitter follower transistor 12 becomes (V ₆ =
Vcc−V _BE −I ₁ R ₉ ) and the electric charge is stored in the capacitor 16.

Similarly, the input changes at sustain t ₀₇ , and transistor 1
Base voltages V ₁ goes low, the base voltage V ₂ of the transistor 2 becomes high level, the output Q to be output from the output terminal 32 is changed from low level to high level,
The output output from the output terminal 31 changes from high level to low level.

In this way, when the input signal supplied to the input terminal 7 rises from the low level to the high level and the input signal supplied to the input terminal 8 falls from the high level to the low level,
From the output terminals 32 and 31, a pulse output having a pulse width τ ₁ and its inverted pulse output appear. Also, input terminal 7
When the input signal supplied to the input terminal 8 falls from the high level to the low level and the input signal supplied to the input terminal 8 rises from the low level to the high level, the output terminal 32 and the output terminal 32
A pulse output having a pulse width τ ₁ and its inverted pulse output appear from 31.

The pulse width τ ₁ of this output pulse is obtained as follows.

In FIG. 2, when the input signal changes at time t ₀₁ , a pulse having a pulse width τ ₁ is output during the time (t _{01 to} t ₀₂ ). This pulse width τ ₁ is the emitter voltage V ₅ of the emitter follower transistor 13 after the input signal changes.
Is equal to the time until it becomes lower than the emitter voltage V ₆ of the emitter follower transistor 12. The emitter voltage V ₅ of the emitter follower transistor 13 is (V ₅ = Vcc−V _BE −I
_The current I ₃ flowing from ₁ R ₉ ) to the transistor 15 gradually decreases, and the emitter voltage V ₆ of the emitter follower transistor 12 is held at (V ₆ = Vcc−V _BE ). Therefore, assuming that the capacitance of the capacitor 16 is C ₁ , C ₁ × I ₁ R ₉ = I ₃ × τ ₁ . Therefore, the pulse width τ ₁ is obtained by τ ₁ = C ₁ I ₁ R ₉ / I ₃ ...

The current I ₁ is set by the transistor 3 and the resistor 5. The current I ₁ is the resistance value of the resistor 5 R ₅ , the reference voltage from the power supply terminal 4 is Vr, and the base-emitter voltage of the transistor 3 is
_Letting V _BE , I ₁ = (Vr−V _BE ) / R ₅ . Current I _3, when the resistance of the external resistor 18 Re _18, the base-emitter voltage of the transistor 15 and V _BE, is _{I 5 = (Vr-V BE} ) / Re 18. If (Vr-V _BE = Vr '), then I ₁ = Vr' / R ₅ ...... I ₃ = Vr '/ Re ₁₈ ...... Substituting this equation equation, the current I ₁ and I ₃ obtained by the formula in the formula, the _{τ 1 = C 1 Re 18 R} 9 / R 5 .......

By setting the resistance value Re ₁₈ of the external resistor 18 appropriately,
An output having a desired pulse width τ ₁ is obtained.

As shown in the equation, the pulse width τ ₁ is determined by the electrostatic capacitance C ₁ , the resistance ratio R ₉ / R _5, and the resistance value Re ₁₈ . When integrated into an integrated circuit, the variations in resistance within the integrated circuit are equal,
It has similar temperature characteristics. Therefore, the resistance ratio R ₉ / R ₅
Is approximately constant. Further, MOS capacitors and MIS capacitors are generally used for the capacitors in the integrated circuit and have good temperature characteristics. The resistance value (Re ₁₈ is the resistance value of the external resistor 18 and thus has good temperature characteristics.
The pulse width τ ₁ hardly changes even if the temperature changes. Further, as shown in the equation, the pulse width τ ₁ does not depend on the reference voltage Vr at all. Therefore, the pulse width τ ₁ does not change even if the reference voltage Vr changes.

c. Structure of another embodiment FIG. 4 shows another embodiment of the present invention. Fourth
In the figure, 51 and 52 represent transistors, the emitters of the transistors 51 and 52 are commonly connected, and this connection point is connected to the collector of the transistor 53 that operates as a constant current source. The base of the transistor 53 is connected to the power supply terminal 54 of the reference voltage. The emitter of the transistor 53 is connected to the ground terminal 56 via the resistor 55.

The base of the transistor 51 is connected to the input terminal 57. The base of the transistor 52 is connected to the input terminal 58. The collector of the transistor 51 is connected to the power supply terminal 61 via the resistor 59, and is also connected to the base of the emitter follower transistor 62. The collector of transistor 52 is resistor 60
And the base of the emitter follower transistor 63. Resistance 59 and
60 is set to the same resistance value.

The collector of the emitter follower transistor 62 is the power supply terminal
Connected to 61. The collector of the emitter follower transistor 63 is connected to the power supply terminal 61. A capacitor is placed between the emitters of the emitter follower transistors 62 and 63.
64 is connected.

The emitter of the emitter follower transistor 62 is connected to the base and collector of a diode-connected transistor 65. The emitter of the transistor 65 is connected to the collector of the transistor 66 which operates as a constant current source and the base of the transistor 68. The base of the transistor 66 is connected to the power supply terminal 54.

The emitter of the emitter follower transistor 63 is connected to the collector of the transistor 67 which operates as a constant current source. The base of the transistor 67 is connected to the power supply terminal 54.

Transistors in which the emitters of the transistors 68 and 69 are commonly connected and the connection point operates as a constant current source
Connected to 73 collectors. The base of the transistor 73 is connected to the power supply terminal 54. The emitter of the transistor 73 is connected to the ground terminal 56 via the resistor 74.

The collector of transistor 68 is connected to the emitters of transistors 70 and 71. The collector of the transistor 69 is connected to the collector of the transistor 71. The collector of the transistor 70 is connected to the power supply terminal 61 via the resistor 75, and the output terminal 85 is derived from the collector of the transistor 70. The collector of the transistor 71 is connected to the power supply terminal 61 via the resistor 76, and the output terminal 86 is led out from the collector of the transistor 71. The resistors 75 and 76 are set to the same resistance value.

The base of the transistor 71 is connected to the emitter of the transistor 77, and the diode-connected transistor is connected.
Connected to 78 collectors and bases. Transistor 77
Is connected to the power supply terminal 61. Transistor 77
A resistor 79 is connected between the base of and the power supply terminal 61.

The connection point between the base of the transistor 77 and the resistor 79 is connected to the collector of the transistor 80 that operates as a constant current source.
The base of the transistor 80 is connected to the power supply terminal 54. The emitter of the transistor 80 is connected to the ground terminal 56 via the resistor 81.

The emitter of the diode-connected transistor 78 is connected to the collector of the transistor 82 which operates as a constant current source. The base of the transistor 82 is connected to the power supply terminal 54.

The emitters of the transistors 66, 67 and 82 that operate as constant current sources are commonly connected, and this connection point is connected to the external resistance mounting terminal 83. An external resistor 84 is connected to the external resistor mounting terminal 83.

d. Description of Operation of Other Embodiments The output of the differential circuit including the transistors 51 and 52 is taken out by the emitter follower transistors 62 and 63. The transistors 70, 71 and 68, 69 form an AND gate. A capacitor 64 is connected between the emitters of the emitter follower transistors 62 and 63, and the output of the emitter follower transistor 62 is supplied to one input terminal of this AND gate via a diode-connected transistor 65. The output of the transistor 63 is supplied to the other input terminal of this AND gate.

In FIG. 5, before reaching time t ₁₁ , the input terminal 57
Is supplied with a high level, and the input terminal 58 is supplied with a low level. Therefore, as shown in FIG. 5A, the base voltage V ₁₁ of the transistor 51 becomes high level, the base voltage V ₁₂ of the transistor 52 becomes low level, the transistor 51 is turned on, and the transistor 52 is turned off.
As a result, the collector voltage V ₁₃ of the transistor 52 becomes high level as shown in FIG.
The collector voltage V _{14 of} goes low. The collector voltage V ₁₃ of the transistor 52 at this time is V ₁₃ = Vcc, where Vcc is the voltage supplied to the power supply terminal 61. On the other hand, the collector voltage V ₁₄ of the transistor 51 is
When the resistance value R 59 of the resistor ₅₉ and the current value set by the transistor 53 and the resistor 55 is I ₁₁ , V ₁₄ = Vcc−I ₁₁ R ₅₉ .

At this time, the emitter voltages V ₁₆ and V ₁₅ of the emitter follower transistors 62 and 63 are
If the base-emitter voltage of 62 and 63 is V _BE , then V ₁₆ = Vcc-I ₁₁ R ₅₉ -V _BE V ₁₅ = Vcc-V _BE .

A capacitor 64 is connected between the emitters of the emitter follower transistors 62 and 63, and an electric charge is stored in the capacitor 64. The voltage Vc ₁₀ across the capacitor 64 is the emitter follower transistor 62 and
It is determined by the potential difference between the emitter voltages V ₁₆ and V ₁₅ of 63, and this both-end voltage Vc ₁₀ is Vc ₁₀ = V ₁₅ −V ₁₆ = I ₁₁ R ₅₉ .

Emitter follower transistor 63 emitter voltage V
₁₅ is supplied to the base of the transistor 70. The emitter voltage V ₁₆ of the emitter follower transistor 62 is level-shifted by V _BE by the diode-connected transistor 65 and supplied to the base of the transistor 68. Therefore, the base voltage V ₁₇ of the transistor 68 is V ₁₇ = Vcc−2V _BE −I ₁₁ R ₅₉ .

The emitter voltage V ₁₉ of the transistor 77 is supplied to the base of the transistor 71. A voltage V ₂₀ (V ₂₀ = V ₁₉ −V _BE ) obtained by level-shifting the emitter voltage V ₁₉ of the transistor 77 by V _BE by the diode-connected transistor 78 is supplied to the base of the transistor 69.

The emitter voltage V ₁₇ of this transistor 77 is (Vcc-
V _BE ) and (Vcc-V _BE- I ₁₁ R ₅₉ ) are set at a level approximately in the center. Base voltage of transistor 69 V ₂₀
Is lower than this voltage V ₁₉ by V _BE , (Vcc−2V _BE ) and (V
A level approximately midway between cc-2V _BE- I ₁₁ R ₅₉ ) is provided.

The voltage V ₁₉ causes the current flowing through the transistor 80 to be I ₁₅ , the resistance 79
Assuming that the resistance value of R ₇₉ is R ₇₉ , V ₁₉ = Vcc−I ₁₅ R ₇₉ −V _BE . The voltage V ₂₀ is V _BE lower than this voltage V ₁₉ by V _BE , that is, V ₂₀ = Vcc−I ₁₅ R ₇₉ −2V _BE .

Before the time t ₁₁ , the base of the transistor 70 is supplied with (V ₁₅ = Vcc−V _BE ), and the base of the transistor 68 is (V ₁₆ −V _BE = Vcc−2V _BE −I ₁₁ R ₅₉ ) is being supplied. Therefore, the transistor 68 is turned off and the transistor 69 is turned on. Since transistor 68 is off, transistors 70 and 71 are off. Therefore,
As shown in FIG. 5E, the output from the output terminal 85 is at a high level and the output Q from the output terminal 86 is at a low level.

At time t ₁₁ , the input changes, the low level is supplied to the input terminal 57, and the high level is supplied to the input terminal 58.
As shown in FIG. A, the base voltage V ₁₁ of the transistor 51 becomes low level, the base voltage V ₁₂ of the transistor 52 becomes high level, the transistor 52 is turned on, and the transistor 51 is turned off. Therefore, if the collector voltage V ₁₄ of the transistor 51 becomes (V ₁₄ = Vcc), and the collector voltage V ₁₃ of the transistor 52 becomes the resistance value of the resistor 60 R ₆₀ (V ₁₃ = Vcc
cc-I ₁₁ R ₆₀ ).

Emitter follower transistor 62 emitter voltage V
_Since the collector voltage V ₁₄ (V ₁₄ = Vcc) of the transistor 51 is applied to the base of the emitter follower transistor 62, the ₁₆ is lower than this voltage V ₁₄ by the base-emitter voltage V _{BE of the} emitter follower transistor 62. The voltage V ₁₆ = Vcc-V _BE . On the other hand, the emitter voltage V ₁₅ of the emitter follower transistor 63 is higher than the base voltage V ₁₆ of the emitter follower transistor 62 by that amount because the charge is stored in the capacitor 64. Voltage across capacitor 64 Vc ₁₀
Since is _{(Vc 10 = I 11 R 59} , emitter voltage V ₁₅ of the emitter follower transistor 63 will _{V 15 = Vcc-V BE -I} 11 R 59.

The emitter voltage V of this emitter follower transistor 63
₁₅ is the collector voltage of the transistor 62 applied to the base of the emitter follower transistor 63 at this time V ₁₃ (V ₁₃
= Vcc-I ₁₁ R ₆₀ ). Therefore, the emitter follower transistor 63 is turned off immediately after the input is changed.

At time t ₁₁ immediately after this input changes, the emitter voltage V ₁₆ of the emitter follower transistor 62 becomes (V ₁₆ = Vcc−V
_BE ), the emitter voltage V ₁₅ of the emitter follower transistor 63 is (V ₁₅ = Vcc−V _BE + I ₁₁ R ₅₉ ). For this reason,
The emitter follower transistor 63 has an emitter voltage V ₁₅ (V ₁₅ = Vcc-V _BE + I ₁₁ R ₅₉ ) at the base of the transistor 70.
Is supplied to the base of the transistor 68, which is supplied with the emitter voltage V ₁₇ (V ₁₇ = Vcc−2V _BE ) of the diode-connected transistor 65, which is lower than the voltage V ₁₆ by V _BE .

The base voltage V ₁₉ of the transistor 71 is the emitter voltage V ₁₅ (V ₁₅ = Vcc of the emitter follower transistor 63 at this time).
-V _BE + I ₁₁ R ₅₉ ), the base voltage V ₂₀ of the transistor 68 is the emitter voltage V of the transistor 65 at this time.
_It is lower than ₁₇ (V ₁₇ = Vcc-2V _BE ). This causes transistor 68 to turn on, transistor 69 to turn off, and transistor 70 to turn off.
Turns on and the transistor 71 turns off. As a result, the fifth
As shown in FIG. E, the output taken from the output terminal 85 changes to the low level, and the output Q taken from the output terminal 86 changes to the high level.

Since the emitter follower transistor 63 is off, the charge stored in the capacitor 64 is
It is discharged by the current I ₁₃ flowing through it. Therefore, the emitter voltage V ₁₅ of the emitter follower transistor 63 is
As shown in FIG. C, it gradually descends. The emitter voltage V ₁₇ of the diode-connected transistor 65 is constant (V ₁₇ = Vcc−2V _BE ) because the emitter follower transistor 62 is on, as shown in FIG. 5D. When the emitter voltage V ₁₅ of the emitter follower transistor 63 becomes lower than the base voltage V _{19 of the} transistor 71, the transistor 70 turns off and the transistor 71 turns on. For this reason,
As shown in FIG. 5E, at time t ₁₂ , the output taken from the output terminal 85 changes to high level, and the output Q taken from the output terminal 86 changes to low level.

At time t ₁₃ , the emitter voltage V ₁₅ of the emitter follower transistor 63 becomes (V ₁₅ = Vcc−V _BE − as shown in FIG. 5C.
When it drops to (I ₁₁ R ₆₀ ), the emitter follower transistor 63 is turned on, and the emitter voltage V ₁₅ of the emitter follower transistor 63 is held at this voltage. Then, the electric charge is stored in the capacitor 64.

At time t ₁₄ , the input changes, the high level is supplied to the input terminal 57, and the low level is supplied to the input terminal 58.
As shown in FIG. A, the base voltage V ₁₁ of the transistor 51 goes high, the base voltage V ₁₂ of the transistor 52 goes low, and the transistor 51 is turned on and the transistor 52 is turned off. Therefore, the collector voltage V ₁₄ of the transistor 51 becomes (V ₁₄ = Vcc-I ₁₁ R ₅₉ ) and the collector voltage V ₁₃ of the transistor 52 becomes (V ₁₃ = Vcc).

Emitter follower transistor 63 emitter voltage V
_Since the collector voltage V ₁₃ (V ₁₃ = Vcc) of the transistor 52 is applied to the base of the emitter follower transistor 63, ₁₅ is lower than this voltage V ₁₃ by the base-emitter voltage V _{BE of the} emitter follower transistor 63. It becomes the voltage V ₁₅ = Vcc-V _bE. On the other hand, the emitter voltage V ₁₆ of the emitter follower transistor 62 becomes higher than the base voltage V ₁₅ of the emitter follower transistor 63 by that amount because the charge is stored in the capacitor 64. Since the voltage across Vc ₁₀ of the capacitor 64 is _{(Vc 10 = I 11 R 60} , emitter voltage V ₁₆ of the emitter follower transistor 62 will _{V 16 = Vcc-V BE +} I 11 R 60.

The emitter voltage V of this emitter follower transistor 62
₁₆ is the collector voltage V _{14 of the} transistor 51 (V ₁₄ which is added to the base of the emitter follower transistor 62 at this time).
= Vcc-I ₁₁ R ₅₉ ). Therefore, the emitter follower transistor 62 is turned off immediately after the input is changed.

At time t ₁₄ immediately after this input changes, the emitter voltage V ₁₅ of the emitter follower transistor 63 becomes (V ₁₅ = Vcc−V
_BE ), the emitter voltage V ₁₆ of the emitter follower transistor 62 is (V ₁₆ = Vcc−V _BE + I ₁₁ R ₆₀ ). For this reason,
The emitter voltage V ₁₅ (V ₁₅ = Vcc-V _BE ) of the emitter follower transistor 63 is supplied to the base of the transistor 70, and the base of the transistor 68 is connected between the base and the emitter of the transistor 65, which is diode-connected, from the voltage V ₁₆ to the base of the transistor 68. Voltage V
The emitter voltage of the transistor 65 which is lower than _{BE by} V ₁₇ (V ₁₇ = Vc
c-2V _BE + I ₁₁ R ₆₀ ) is supplied.

The base voltage V ₁₉ of the transistor 71 is the emitter voltage V ₁₅ (V ₁₅ = Vcc of the emitter follower transistor 63 at this time).
-V _BE ), the base voltage V ₂₀ of transistor 68 is
The emitter voltage of the transistor 65 at this time V ₁₇ (V ₁₇ = Vcc
Lower than −2V _BE ＋ I ₁₁ R ₆₀ ). Therefore, the transistor 68
Is on, the transistor 69 is off, the transistor 70 is on, and the transistor 71 is off. As a result, FIG.
As shown in, the output Q from the output terminal 85 changes to the low level, and the output Q from the output terminal 86 is output.
Changes to high level.

Since the emitter follower transistor 62 is off, the charge stored in the capacitor 64 is
It is discharged by the current I ₁₂ flowing through it. Therefore, the emitter voltage V ₁₆ of the emitter follower transistor 62 gradually decreases, and the emitter voltage V ₁₇ of the diode-connected transistor 65 gradually decreases as shown in FIG. 5D. When the emitter voltage V ₁₇ of the transistor 65 becomes lower than the base voltage V _{20 of the} transistor 69, the transistor 68 turns off and the transistor 69 turns on.

On the other hand, the emitter voltage of the emitter follower transistor 63
V ₁₅ is constant at (V ₁₅ = Vcc−V _BE ) as shown in FIG. 5C. Thus, at time t ₁₅ the transistor 68 is turned off, the transistor 69 is turned on, as shown in FIG. 5 E, the output Q of output taken from the output terminal 85 is changed to the high level, it is taken out from the output terminal 86 Changes to low level.

Lowered emitter voltage V ₁₆ of the emitter follower transistor 62 to _{(V 16 = Vcc-V BE} -I 11 R 59) at time t _16, the emitter voltage V ₁₇ of the transistor 65 is _{(V 17 = Vcc-2V BE} -I ₁₁
R ₅₉ ), the emitter follower transistor 6
2 is turned on and the emitter voltage V ₁₆ of the emitter follower transistor 62 is maintained at a constant voltage. And capacitor 6
Electric charge is stored in 4.

This output pulse width τ ₁₁ is obtained as follows.

In FIG. 5, when the input signal changes at time t ₁₁ , a pulse having a pulse width τ ₁₁ is output during the time (t _{11 to} t ₁₂ ). This pulse width τ ₁₁ is, as shown in FIG. 5C,
After the input signal changes, the emitter follower transistor 63 emitter voltage V _15
It is equal to the time until it becomes lower than ₁₉ . The emitter voltage V ₁₅ of the emitter follower transistor 63 immediately after the change of the input signal is (V ₁₅ = Vcc−V _BE + I ₁₁ R ₅₉ ). Therefore, the potential difference between the emitter voltage V ₁₅ of the emitter follower transistor 63 and the base voltage V ₁₉ of the transistor 71 immediately after the input is changed is that the current flowing through the transistor 80 is I ₁₅ , the resistance 79 is
The resistance value of R ₇₉ is V ₁₅ −V ₁₉ = (Vcc−V _BE + I ₁₁ R ₅₉ ) − (Vcc−I ₁₅ R ₇₉ −V _BE ) = I ₁₁ R ₅₉ + I ₁₅ R ₇₉ . Therefore, assuming that the capacitance of the capacitor 64 is C ₁₁ , the pulse width τ ₁₁ can be obtained by τ ₁₁ = C ₁₁ (I ₁₁ R ₅₉ + I ₁₅ R ₇₉ ) / I ₁₃ ...

The pulse width of the pulse output when the input signal changes at time t ₁₄ is equal to the time from when the input signal changes until the emitter voltage V _{17 of the} transistor 65 becomes lower than the base voltage V _{19 of the} transistor 71. Current flowing through transistor 66
I ₁₂ , current through transistor 67 I ₁₃ , transistor 82
The currents I ₁₄ flowing through are equal. Therefore, the pulse width is similarly obtained by the equation.

Similarly to the currents I ₁₁ and I ₁₃ , the current I ₁₅ is also formed from the reference voltage Vr supplied to the power supply terminal 54.

Let Vr ′ = Vr−V _BE, and set the resistance values of the resistor 55, external resistor 84, and resistor 84 to R ₅₅ and Re, respectively.
₈₄ and R ₈₁ , the currents I ₁₁ , I ₁₃ and I ₁₅ are shown by I ₁₁ = Vr ′ / R ₅₅ , I ₁₃ = Vr ′ / Re ₈₄ and I ₁₅ = Vr ′ / R ₈₁ , respectively. Substituting these into the equation gives t ₁₁ = C ₁₁ ((R ₅₉ / R ₅₅ ) + (R ₇₉ / R ₈₁ )) Re ₈₄ ……. As shown in the equation, the pulse width τ ₁₁ is the capacitance C ₁₁ of the capacitor 64, the resistance ratio R ₅₉ / R ₅₅ , R ₇₉ / R ₈₄ ,
Determined by the resistance value Re ₈₄ of the external resistor 84. Therefore, a pulse having a constant width can be obtained with almost no influence of temperature characteristics.

〔The invention's effect〕

According to the present invention, a bi-directional monostable multivibrator having a small number of elements and having a simple configuration and triggered by rising and falling of an input signal can be constructed. Further, according to the present invention, when integrated into a circuit, the pulse width is determined by the external resistance, the capacitance of the capacitor in the integrated circuit, and the resistance ratio in the integrated circuit. Therefore, there is little variation and the temperature characteristics are extremely good.

[Brief description of drawings]

FIG. 1 is a connection diagram of one embodiment of the present invention, FIG. 2 is a waveform diagram used to explain one embodiment of the present invention, and FIG. 3 is a connection diagram used to explain one embodiment of the present invention. FIG. 7 is a connection diagram of another embodiment of the present invention, FIG. 5 is a waveform diagram used to explain another embodiment of the present invention, FIG. 6 is a block diagram of a conventional mono-multi, and FIG. 7 is a conventional mono-multi. FIG. 8 is a waveform diagram used for explaining the multi, FIG. 8 is a block diagram of an example of a differentiation circuit in the conventional mono-multi, FIG. 9 is a waveform diagram used for explaining the differentiation circuit in the conventional mono-multi, and FIG. 10 is a conventional mono-multi. It is a connection diagram of an example of a differentiation circuit in the multi. Description of main symbols in the drawings 7,8,57,58: Input terminals, 1,2,51,52: Transistors that make up a differential circuit, 12,13,62,63: Emitter follower transistors, 16,64: Capacitors, 31, 32, 85, 86: output terminals.

Claims (1)

[Claims] 1. A differential circuit comprising first and second transistors whose emitters are commonly connected, an input terminal derived from the bases of the first and second transistors, and the first and second transistors. The base of the second transistor is connected to the collector of the second transistor, and a predetermined current flows through the third and fourth transistors that form the emitter follower circuit and the third and fourth transistors,
A current source whose current value is set by an external resistor, a capacitor connected between the emitters of the third and fourth transistors, and outputs of both ends of the capacitor are supplied to change the voltage across the capacitor. It consists of a pulse forming circuit that forms a pulse with a pulse width according to the above, and an output terminal that is derived from the above pulse forming circuit.An input pulse is applied to the above input terminal and the voltage across the capacitor is applied to the above pulse forming circuit. A monostable multivibrator which is supplied to form an output signal having a predetermined pulse width determined by the capacitor and an external resistor from rising and falling edges of the input pulse.