JPH0787245B2 - Tunnel transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor utilizing a tunnel phenomenon, which can be highly integrated, operate at high speed, and have multiple functions.

[0002]

2. Description of the Related Art A tunnel transistor has been proposed as a transistor having multiple functions by utilizing a tunnel phenomenon at a p ⁺ -n ⁺ junction on a semiconductor surface. Regarding this device, for example, Japanese Patent Application No. 3-1
No. 96321, "Semiconductor Device". This tunnel transistor can form a functional circuit with a small number of elements, and enables high integration.

FIG. 5 is a sectional view showing an example of a conventional tunnel transistor. 1 is a GaAs substrate, 2 is GaAs
An i-Al _0.5 Ga _0.5 As layer (where i is an abbreviation that means an undoped semiconductor that can be regarded as intrinsic or substantially intrinsic; the same applies to the following) formed on the substrate 1 is 3 having a thickness of about 20 nm. semiconductor channel layer made of GaAs layer, n ⁺ including n ⁺ -GaAs layer degenerated 10 - source regions in the diffusion layer, p ⁺ including p ⁺ -GaAs layer having degenerated 11 - drain region in the diffusion layer, 6 i-Al _0.5 Ga
Insulating layer made of _0.5 As layer, 7 is a gate electrode made of an Al film, 8 is a source electrode, 9 is a drain electrode of AuGe.
/ Au multilayer film. When the source electrode 8 is set to the ground potential, no voltage is applied to the gate electrode 7, and a positive voltage is applied to the drain electrode 9, n ⁺ -GaA of the source region is applied.
A forward bias is provided between the s layer and the p ⁺ -GaAs layer in the drain region through the very thin semiconductor channel layer (3). In this forward bias, the drain current flows more easily than in the reverse bias, but if the carrier diffusion current is not higher than a voltage (0.7 V or less for GaAs), almost no current flows. Now, when a large positive voltage is applied to the gate electrode, a high concentration of electrons is induced in the semiconductor channel layer (3). As a result, this semiconductor channel layer is in a degenerated state in which the electron concentration is very large, and can be equivalently regarded as an n ⁺ -GaAs layer. For this reason,
The source region (10) and the semiconductor channel layer (3) are brought into complete conduction. On the other hand, a junction (tunnel junction) similar to an Esaki diode (tunnel diode) is formed between the semiconductor channel layer (3) and the drain region (11). Therefore, a large tunnel current flows due to the tunnel effect between the drain and source to which the forward bias is applied, and differential negative resistance appears in the current-voltage characteristic. Since the magnitude of the tunnel current depends on the concentration of electrons induced in the semiconductor channel layer, this differential negative resistance characteristic is controlled by the voltage applied to the gate electrode, and the operation of a functional transistor can be obtained. To be

[0004]

The most important junction formation between the semiconductor channel layer and the drain region in this device utilizes ion implantation. Alternatively, it can be formed by utilizing selective regrowth. In any case, the recombination sensor is likely to occur in the vicinity of the tunnel junction due to such a process, and the large negative recombination current through this center adversely affects the negative differential resistance characteristics. was there. In order to obtain high reliability as a functional element, suppression of this generation / recombination center is desired.

It is an object of the present invention to provide a tunnel transistor which is not easily affected by generation / recombination centers and therefore has an improved differential negative resistance characteristic.

[0006]

A tunnel transistor according to the present invention has a semiconductor channel layer having at least a surface portion provided on a surface of an insulating substrate and different conductivity types for selectively covering the semiconductor channel layer. A first semiconductor layer and a second semiconductor layer, and the first and second semiconductor layers.
An insulating layer provided on the surface of the semiconductor channel layer sandwiched by the semiconductor layer, a gate electrode on the insulating layer, a source electrode and a drain in contact with the first semiconductor layer and the second semiconductor layer, respectively. It has an electrode.

[0007]

Since the tunnel junction is formed in the semiconductor channel layer, this junction characteristic is not easily affected by the generation / recombination center.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a first embodiment of the present invention.

In this embodiment, the surface of the GaAs substrate 1 is an i-Al _0.5 Ga _0.5 As layer 2 having a thickness of 500 nm, which is epitaxially grown. The i-Al _0.5 Ga _0.5 As layer 2 has a thickness of 2 on the surface.
The 0 nm i-GaAs layer 3 is epitaxially grown. The i-GaAs layer 3 has a space of 1 μm and n
^{The +} -GaAs layer 4a and the p ⁺ -GaAs layer 5a are selectively formed. n ⁺ -GaAs layer 4a and p ⁺
All are degenerate with i-GaA layer 5a
It has an epitaxial junction with the s layer. n ⁺ -GaAs
I-GaA sandwiched between the layer 4a and the p ⁺ -GaAs layer 5a
A 20 nm-thick i-Al _0.5 Ga _0.5 A layer is formed on the surface of the s layer 3.
The s layer 6 is provided in a heterojunction. n ⁺ -GaA
AuGe / A is used for the s layer 4a and the p ⁺ -GaAs layer 5a.
A source electrode 8 and a drain electrode 9 made of a u multilayer film are provided in contact with each other. i-Al _0.5 Ga
_A gate electrode 7 made of an Al film is provided in contact with the surface of the _0.5 As layer 6.

First semiconductor layer (n ⁺ -GaAs layer 4a)
Is a degenerate semiconductor in which high-concentration electrons exist, so that high-concentration electrons spread to the semiconductor channel layer (i-GaAs layer 3) below this layer, and the semiconductor channel below the first semiconductor layer. The layer is a degenerate semiconductor with a high concentration of electrons. Similarly, the second semiconductor layer (p ⁺ -Ga
Since the As layer 5a) is a degenerate semiconductor in which a high concentration of holes exists, holes also spread to the semiconductor channel layer below this layer, and the semiconductor channel layer below the second semiconductor layer has a high concentration. It is a degenerate semiconductor in which a certain number of holes exist. Therefore, when a positive voltage is applied to the gate electrode 7 to induce a high concentration of electrons in the semiconductor channel layer below the insulating layer (i-Al _0.5 Ga _0.5 As layer), this region and the first semiconductor layer Complete conduction with the semiconductor channel layer,
A tunnel junction is formed with the semiconductor channel layer below the second semiconductor layer. Therefore, it is possible to realize the transistor operation having the differential negative resistance characteristic like the conventional transistor. Note that the first semiconductor layer does not necessarily have to be degenerated, but is preferably degenerated in order to reduce parasitic resistance.

In the structure of the tunnel transistor of the present invention, since the tunnel junction is formed in the single semiconductor channel layer as described above, the tunnel junction is generated and recombined as in the heterogeneous semiconductor junction forming process. Not easily affected by the center. For this reason, the recombination current is small and the differential negative resistance characteristic which is more remarkable than that of the conventional structure is obtained.

Next, the manufacturing method of the embodiment of the present invention will be described.

First, a 500 nm i-Al _0.5 Ga _0.5 As layer 3 (semiconductor channel layer) on a (100) plane of a GaAs substrate 1 and a 20 nm thick p ⁺ GaAs layer 5 a (concentration 5).
X contains 10 ¹⁹ cm ^-3 of Be as a dopant)
Were formed by a molecular beam epitaxy (MBE) method. The substrate temperature was set to 520 ° C. in order to suppress surface unevenness and diffusion of impurities.

P ⁺ -GaAs other than the portion to be the drain
After removing 5a, a 20 nm-thick n ⁺ -
A GaAs layer 4a (containing a concentration of 1 × 10 ¹⁹ cm ⁻³ of Si as a dopant) was selectively grown. Furthermore, after growing an i-Al _0.5 Ga _0.5 layer 6 having a thickness of 20 nm and depositing an Al film having a thickness of 50 nm, the Al film and the i-Al _0.5 Ga _0.5 As layer 6 thereunder are processed into a gate electrode shape. did. Finally, by lift-off method, AuGe / A
A source electrode 8 and a drain electrode 9 made of a u multilayer film were formed. Ohmic contact was obtained without the alloying step of the electrodes.

With the device having this structure, it was found that the peak-valley ratio of the differential negative resistance characteristic was 10 or more, which is an improvement over the conventional structure. The same characteristics as a tunnel transistor were obtained when high-concentration holes were induced in the i-GaAs layer 3 below the gate electrode by reversing the polarities of the voltages applied to the source, drain, and gate.

Next, a second embodiment of the present invention will be described with reference to FIG.
Will be described with reference to. In this embodiment, as a second semiconductor device, a p-type semiconductor having a valence band edge energy lower than that of the semiconductor channel layer (i-GaAs layer 3) has a thickness of 20 n.
m, Be concentration of 5 × 10 ¹⁹ cm ⁻³ of p ⁺ -Al _0.3 Ga
_{The 0.7} As layer 5b is used and the thickness of the first semiconductor layer is 20.
nm, Si concentration 1 × 10 ¹⁹ cm ⁻³ n ⁺ -Al _0.3 Ga
_The difference from the first embodiment is that the _0.7 As layer 4b is used. A p ⁺ -Al _0.3 Ga _0.7 As / GaAs modulation-doped structure is provided between the second semiconductor layer and the semiconductor channel layer.

3 (a) and 3 (b) schematically show energy band diagrams on the source side and the drain side in this embodiment.

On the source side, n ⁺ -Al _0.3 Ga _0.7 As
An electron storage layer A is formed at the junction between the layer 4b and the i-GaAs layer 3. On the drain side, p ⁺ -Al _0.3 G _0.7 As
A hole storage layer B is formed at the junction between the layer 5b and the i-GaAs layer 3.

The holes in the p ⁺ -Al _0.3 Ga _0.7 As layer 5b move to the i-GaAs layer 3, and the second semiconductor layer (5
b) Holes having a concentration higher than that of the second semiconductor layer (5b) will be accumulated in the lower semiconductor channel layer (3).

When a positive voltage is applied to the gate electrode 7, i-
An electron storage layer similar to that shown in FIG. 3A is formed at the junction between the Al _0.5 Ga _0.5 As layer 6 and the i-GaAs layer 3.

When the gate voltage is 1 volt, about 1 × 10 ¹²
A charge of cm ^-2 is accumulated. Assuming an ideal heterojunction, the maximum charge density is estimated to be about 1 × 10 ¹⁹ cm ⁻³ . In the i-GaAs layer 3 on the drain side, p ⁺ -Al
Impurity concentration of _0.3 Ga _0.7 As layer 5b 5 × 10 ¹⁹ cm ⁻³
Since a larger number of holes are present, it can be considered that a tunnel junction (p ⁺ -n ⁺ junction) having a thickness of about 12 nm or less is formed.

In this embodiment, since holes having a higher concentration than the second semiconductor layer (5b) are accumulated on the drain side, in addition to the improvement of the negative differential characteristic as in the first embodiment, the tunnel current is increased. The density can be improved, and a tunnel current larger than that of the first embodiment by at least one digit was obtained.

The first semiconductor layer may be an n ⁺ -GaAs layer as in the first embodiment. The manufacturing method is similar to that of the first embodiment and will not be described again.

Next, a third embodiment of the present invention will be described with reference to FIG.
Will be described with reference to. In this example, p ⁺ -Al having a thickness of 20 nm and a Be concentration of 5 × 10 ¹⁹ cm ⁻³ was used as the first semiconductor layer.
_{The 0.3} Ga _0.7 As layer 4c is used as the second semiconductor layer, the energy of the conduction band edge is higher than that of the semiconductor channel layer (i-GaAs layer 3), the thickness is 20 nm, and the Si concentration is 1 × 10 ¹⁹ c.
It differs from the first embodiment in that the n ⁺ -Al _0.3 Ga _0.7 As layer 5c of m ⁻³ is used. In this structure, the source,
Since the conductivity type of the drain is opposite to that of the first and second embodiments, it is necessary to apply a negative voltage to the gate to induce a high concentration of holes in the channel layer to operate, but the drain end is also operated. A tunnel junction is formed in the, and similar characteristics of the tunnel transistor are obtained.

An n-type modulation-doped structure of n ⁺ -Al _0.3 Ga _0.7 As / i-GaAs is provided between the second semiconductor layer and the semiconductor channel layer. Therefore, n ⁺ -Al _0.3
Electrons in the Ga _0.7 As layer 5c move to the i-GaAs layer 3, and electrons having a concentration higher than that of the second semiconductor layer are accumulated in the semiconductor channel layer below the second semiconductor layer. Therefore, the second
As in the case of Example 1, the improvement of the negative differential characteristic and the improvement of the tunnel current could be achieved. The first semiconductor layer is p ⁺ -G
It may be an aAs layer. The manufacturing method is similar to that of the first embodiment and will not be described again.

As described above, a substrate obtained by epitaxially growing an i-AlGaAs layer on a GaAs substrate is used as an i-GaA substrate.
The example in which the s layer is used as the semiconductor channel layer has been described. As the insulating film on the substrate surface, in addition to AlGaAs,
Other semiconductors with wide bandgap, SiO ₂ , Si
₃ N ₄ , silicon oxynitride, Al ₂ O ₃ , TiO ₂ , Pb
An insulator such as ZrTiO ₃ or CaF can be used. The semiconductor channel layer and the first and second semiconductor layers are not only a single semiconductor such as Si, Ge, GaAs, InP, but also GaAs-GaAlAs, Ge-SiGe, S.
i-SiGeC, Si-GaP, Ge-GaAs, In
AsP-GaAs, InGaAs-InAlAs, In
GaAs-InP, GaSb-AlGaSb, InAs
-AlGaSb, InSb-InAs, HgCdTe-
A semiconductor having a heterojunction such as CdTe can also be used.

[0028]

As described above, according to the present invention, it is possible to realize a tunnel transistor having an improved differential negative resistance characteristic which is less susceptible to the influence of recombination centers.
high speed. It enables low power consumption, room temperature operation, and ultra-high-density tunnel device integrated circuits.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

FIG. 3 is an energy band diagram showing the source side and the drain side used in the description of the second embodiment, which are divided into (a) and (b), respectively.

FIG. 4 is a sectional view showing a third embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a conventional example.

[Explanation of symbols]

1 GaAs substrate 2 i-Al _0.5 Ga _0.5 As layer 3 i-GaAs layer 4 a n ⁺ GaAs layer 4 b n ⁺ -Al _0.3 Ga _0.2 As layer 4 cp ⁺ -Al _0.3 Ga _0.7 As layer 5 ap ⁺ -GaAs layer 5 bp ⁺ -Al _0.3 Ga _0.7 As layer 5c n ⁺ -Al _0.3 Ga _0.5 As layer 6 i-Al _0.5 Ga _0.5 As layer 7 Gate electrode 8 Source electrode 9 Drain electrode 10 n ⁺ -Diffusion layer 11 p ⁺ -Diffusion layer

Claims (4)

[Claims] 1. A semiconductor channel layer having at least a surface portion provided on a surface of an insulating substrate, and a first semiconductor layer and a second semiconductor layer having different conductivity types for selectively covering the semiconductor channel layer. An insulating layer provided on the surface of the semiconductor channel layer sandwiched between the first and second semiconductor layers, and a gate electrode on the insulating layer,
A tunnel transistor having a source electrode and a drain electrode respectively in contact with the first semiconductor layer and the second semiconductor layer. 2. The tunnel transistor according to claim 1, wherein at least the second semiconductor layer contains a high concentration of impurities and is degenerated. 3. The tunnel transistor according to claim 1, wherein at least the second semiconductor layer has a p-type conductivity type and has a lower valence band edge energy than the semiconductor channel layer. 4. The tunnel transistor according to claim 1, wherein at least the second semiconductor layer has an n-type conductivity, and the energy of the conduction band edge is higher than that of the semiconductor channel layer.