JPH0787155A - Voltage detection circuit - Google Patents

Abstract

PURPOSE:To reduce the detection delay by outputting the result of comparison between the input voltage from one of a pair line and the earth and a threshold. CONSTITUTION:A clock output part 2 outputs the clock having the center value point of an inputted AC induced voltage as the change point, and this clock is inputted to a clock switching part 3, and when the input of this clock is broken, the switching part 3 outputs a clock whose frequency is higher than the frequency of the AC induced voltage. When an FF 20 of a decision part 4 is set/reset by the rise and the fall of the clock, the output is in the high level when a negative DC voltage which has the AC induced voltage superposed and is earthed in one end is not applied, but the output is in the low level when it is applied; and thus, it is detected whether the negative DC voltage which is earthed in one end is applied or not. Since it is detected whether the negative voltage is applied or not at the time of the rise and the fall of the clock in this case, the detection delay is a half period or shorter of the AC induced voltage, and the delay is made very shorter than conventional.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a terminal device when an AC induction voltage (hereinafter referred to as an AC induction voltage) having a commercial power frequency is superimposed on a subscriber line between a subscriber line terminal device and a terminal device. Then, when one side of the subscriber line is applied with a negative DC voltage of ground, an AC induced voltage is applied to detect whether a negative DC voltage is applied on the side of the subscriber line terminal equipment. One of the pair wires is related to an improvement of a voltage detection circuit for detecting whether a negative DC voltage of the ground is applied between the pair wire and one of the pair wires.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional voltage detection circuit. In FIG. 5, R1, R2, R3, and R4 are equivalent resistances of the subscriber line 60, and AC from the AC induction source 52.
The induced voltage is applied to the subscriber line 60, and the terminal SW connected to one end of the subscriber line 60 turns on and off the switch SW, so that one end has a negative DC voltage V of ground (for example, -5V). ) Is applied or not applied, the voltage detecting circuit 61 on the subscriber line terminal equipment side detects whether or not the negative DC voltage is applied.

The voltage detection circuit 61 divides the voltage between one side of the subscriber line 60 and the ground by resistors R5 and R6, attenuates the AC induced voltage by the low pass filter 50, and outputs only a negative DC voltage. It is passed and input to the comparator 51, and the comparator 51 uses a negative voltage close to 0 as a threshold value and compares it with this. If the absolute value is larger than the threshold value, it is detected that a negative DC voltage is applied. Outputting a signal.

Taking the case where the frequency of the AC induction voltage is 60 Hz as an example, the AC induction voltage of 60 Hz is attenuated to
Low-pass filter 50 that passes only negative DC voltage
Has a resistance of 100KΩ and a capacitance of 0.3μ.
It is composed of an F capacitor C3.

[0005]

However, since the low-pass filter 50 is used in the voltage detection circuit of the conventional example, it is delayed so that only the negative DC voltage is passed. For example, when the frequency of the AC induction voltage is 60 Hz. It takes about 30 ms to detect whether a negative DC voltage is applied.

That is, there is a problem that detection of whether or not a negative DC voltage is applied is delayed. An object of the present invention is to provide a voltage detection circuit that can detect whether or not a negative DC voltage is applied without delay.

[0007]

FIG. 1 is a block diagram showing the principle of the present invention. As shown in FIG. 1, in a pair of wires on which an AC induced voltage is superposed, one of the pair wires is connected to the ground in a voltage detecting circuit for detecting whether or not a negative DC voltage of the ground is applied. A negative DC voltage whose absolute value is smaller than the negative DC voltage applied to the line is used as a threshold value, and a comparison unit 1 that compares the voltage input between one of the pair lines and ground and outputs a comparison result; A clock output section 2 for selectively inputting an AC induced voltage from a voltage inputted between one side and ground, and outputting a clock having a change point at the center value point of the inputted AC induced voltage, and an output clock of the clock output section 2. When the clock is no longer input, the clock switching unit 3 outputs a clock having a frequency higher than at least the frequency of the AC induction voltage, and outputs the clock switching unit 3 to a flip-flop (hereinafter referred to as F (Referred to as “20”), outputs a hit value at a rising edge and a falling edge, and determines whether or not a negative DC voltage is applied at the output of the FF 20. To do.

[0008]

According to the present invention, since the comparison unit 1 compares the voltage input between one of the pair wires and the ground with the threshold value and outputs the comparison result, the AC induced voltage is superposed on the pair wire. On the other hand, when the negative DC voltage of the ground is not applied, the output of the comparison unit 1 has the same cycle as the AC induction voltage, and the AC induction voltage of the AC induction voltage is centered around the beak value of the AC induction voltage. H level wider than 1/2 cycle and others become L level, and when negative DC voltage of ground is applied to one, the AC induction voltage and the cycle are equal, and the peak value of the AC induction voltage is centered. , The H level having a width narrower than 1/2 cycle of the AC induction voltage and the L level other than the AC induction voltage are input to the FF 20 of the determination unit 4.

The clock output unit 2 outputs a clock having a change point at the center value point of the input AC induced voltage, and inputs the clock to the clock switching unit 3. The clock switching unit 3 inputs the clock. When the clock is output and is no longer input, a clock having a frequency higher than at least the frequency of the AC induced voltage is output, and the input of the FF 20 of the determination unit 4 is a value that is struck by rising and falling. Input as a clock.

In the FF 20 of the judging section 4, when the clock is struck at the rising edge and the falling edge of the clock, the AC induced voltage is superimposed, and when the negative DC voltage of the ground is not applied, the output is at the H level. Then, one of them outputs the L level when the negative DC voltage of the ground is applied, so that it is possible to detect whether the one of the negative DC voltage of the ground is applied or not. In this case, since the detection of whether or not a negative DC voltage is applied is performed at the rising and falling edges of the clock, the detection delay is less than 1/2 cycle of the AC induction voltage, and the conventional low-pass voltage is low. The delay is much less than when using a filter.

When the AC induction voltage is not applied, and when one side is not applied with the negative DC voltage of the ground, the output of the comparison unit 1 is at H level, and when the negative DC voltage is applied,
The output of the comparison unit 1 becomes L level and is input to the FF 20,
Since the clock switching unit 3 outputs a tapped value at the rising and falling edges of a clock having a frequency higher than at least the frequency of the AC induced voltage, a delay for detecting whether a negative DC voltage is applied or not. Is less than 1/2 cycle of the AC induced voltage.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a circuit diagram of a voltage detecting circuit according to an embodiment of the present invention, FIGS. 3 and 4 are time charts of waveforms of respective portions of FIG. 2, and FIG. 4 shows a continuation of FIG. 3 in terms of time. Cage, (A) ~
(N) corresponds to points a to n in FIG.

In the voltage detection circuit of FIG. 2 as well, like the conventional voltage detection circuit 61 of FIG. 5, the AC induction voltage from the AC induction source 52 is applied to the subscriber line 60, and one end of the subscriber line 60 is connected. By turning on / off the switch SW in the connected terminal device, one end may or may not be applied with a negative DC voltage V (for example, -5V) of ground, but this negative DC voltage is applied. The subscriber line terminal equipment side detects whether or not it has been done.

In the comparison unit 1 of FIG. 2, one is generated between one of the subscriber lines 60 and the ground, one is the AC induced voltage when the negative DC voltage of the ground is not applied, and one is the negative voltage of the ground. AC induced voltage when DC voltage is applied,
The voltage shown in FIG. 3 and FIG. 4 (A), which is divided by the resistors R9 and R10, is input, and the absolute value is smaller than the input negative DC voltage equivalent voltage. The operational amplifier 5 compares the negative DC voltage with the threshold voltage, and outputs the comparison result shown in FIGS. 3 and 4B.

This comparison result shows that, as shown in FIG. 3 and FIG. 4A, the AC induction voltage is superimposed, but on the other hand, when the negative DC voltage of the earth is not applied, the AC induction voltage is applied. The voltage and the cycle are equal, and the output is at the H level, which is wider than the 1/2 cycle of the AC induction voltage, and at the L level, other than the beak value of the AC induction voltage. As shown in D, the AC induction voltage is superposed, but on the other hand, when a negative DC voltage of the earth is applied, the cycle is equal to the AC induction voltage, and the peak value of the AC induction voltage is the center. The H level narrower than the half cycle of the AC induction voltage and the other L level outputs are output to the FF 20 of the determination unit 4.

In the clock output section 2, the clock output section 2 shown in FIG.
From the input voltage shown in (1), the direct current component is cut by the capacitor C1, only the alternating current component is taken out and input to the operational amplifier 7, and the voltage inverted by the operational amplifier 6 is also applied to the operational amplifier 7
3 and 4E, a clock having a center point of the input AC induction voltage as a change point is output and input to the clock switching unit 3.

In the clock switching unit 3, the input clock is amplified by the transistor Tr and the time constant circuit of the capacitor C2 and the resistor R16 smooths the waveform, and then the waveforms shown in FIGS.
As shown in (F), a waveform which does not become 0 at the next rising edge of the clock is input to the operational amplifier 8, and in the operational amplifier 8, +5 V is divided by the resistors R17 and R18. As shown in Fig. 3 (a), compared with the voltage when the blunted voltage is slightly higher than that when no voltage is input,
A signal as shown in (G) is obtained and input to the AND circuit 10 and its inverted signal to the AND circuit 11, and a clock as shown in FIG. 3 and FIG. 4 (H) is output and input to the OR circuit 13.

On the other hand, rather than the clock source 9, FIG.
As shown in (I), a clock having a frequency higher than at least the frequency of the AC induction voltage is output and input to the AND circuit 11, the AC induction voltage is no longer superimposed, and the output of the operational amplifier 8 is as shown in FIG. When the L level is reached as shown in G), the AND circuit 11 outputs the clock from the clock source 9 as shown in FIG. As shown in (K), when the AC induced voltage is present, the clock output unit 2
When the AC induced voltage is not multiplied, the output clock of the clock source 9 is output and input as the clock of the FF 20-1 of the determination unit 4, and
Inverted and input as the clock of FF20-2,
Tap the input shown in FIG.

Then, the output of the FF 20-1 is as shown in FIGS.
As shown in (L) of FIG. 3, when the negative DC voltage is not applied, it is at H level, and when applied, it becomes L level and is input to the AND circuit 12, and the output of the FF 20-2 is as shown in FIG. As shown in (M), when the negative DC voltage is not applied, it is at H level and when it is applied, it is at L level and is input to the AND circuit 12.

Then, the output of the AND circuit 12 is shown in FIGS.
(N) of FIG. That is, in order to detect whether a negative DC voltage is applied,
Since it is performed at the falling edge, the detection delay is less than 1/2 cycle of the AC induced voltage. If the frequency of the AC induced voltage is, for example, 60 Hz, the detection delay is 8 ms or less, and the delay is very small as compared with the case of using the conventional low pass filter.

Incidentally, as shown in FIG. 3 and FIG.
When the induced voltage is not superposed, and when the negative DC voltage of the ground is not applied, the output of the comparison unit 1 is H.
When a level, negative DC voltage is applied, the output of the comparison unit 1 becomes L level as shown in FIG. 4 (B), which is input to the FFs 20-1 and FF 20-2, and the output from the clock source 9 shown in FIG. , A clock having a frequency higher than at least the frequency of the AC induced voltage shown in (I) of FIG. 4 is output from the OR circuit 13 as shown in (K) of FIG. Input as 2 clock.
Also in this case, since the detection of whether or not the negative DC voltage is applied is performed at the rising and falling edges of the clock, the detection delay is less than 1/2 cycle of the AC induction voltage.

[0022]

As described in detail above, according to the present invention, whether or not an AC induced voltage is superposed on a subscriber line, whether a negative DC voltage of which one is grounded is applied to the subscriber line. In order to detect, the detection can be performed with a delay of 1/2 cycle or less of the AC induction voltage, and the detection delay can be extremely reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention,

FIG. 2 is a circuit diagram of a voltage detection circuit according to an embodiment of the present invention,

3 is a time chart of waveforms of each part of FIG. 2 (No. 1),

FIG. 4 is a time chart (No. 2) of the waveform of each part of FIG.

FIG. 5 is a block diagram of a conventional voltage detection circuit.

[Explanation of symbols]

1 is a comparison unit, 2 is a clock output unit, 3 is a clock switching unit, 4 is a determination unit, 5-8 are operational amplifiers, 9 is a clock source, 10-12 are AND circuits, 13 is an OR circuit, 20,
20-1 and 20-2 are flip-flops, 50 is a low-pass filter, 51 is a comparator, 52 is an AC induction source, 60 is a subscriber line, 61 is a voltage detection circuit, R1 to R20 are resistors,
SW is a switch, V is a negative DC voltage, C1 to C3 are capacitors, D1 and D2 are diodes, and Tr is a transistor.

Claims (1)

[Claims] 1. A pair line on which an AC induction voltage is superimposed,
One is a voltage detection circuit that detects whether a negative DC voltage of the ground is applied between one of the pair wires and the ground, and a negative DC voltage whose absolute value is smaller than the negative DC voltage applied to the pair wire. A comparator (1) that outputs a comparison result by comparing with a voltage that is input between one of the paired wires and the ground, and an AC induction voltage that is selectively input from the voltage that is input between one of the paired wires and the ground. , A clock output section (2) for outputting a clock having a center point of the input AC induced voltage as a change point, and an output clock of the clock output section (2) for input and output, and the clock for input When it disappears, a clock switching unit (3) that outputs a clock having a frequency at least higher than the frequency of the AC induction voltage and a flip-flop (2) that outputs the clock switching unit (3).
0) as the clock, and outputs the value hit at the rising edge and the falling edge of the flip-flop (20).
A voltage detection circuit comprising a determination unit (4) for determining whether or not a negative DC voltage is applied at the output of 1.