JPH0786932A - Oscillator - Google Patents

Abstract

PURPOSE:To miniaturize the oscillator, to reduce the cost and to improve the stability by composing a feedback circuit of a digital circuit. CONSTITUTION:The feedback circuit for feeding back the partial output of a VCO 2 is composed of a frequency divider 4, frequency counter 5 and D/A converter 6. After an oscillation frequency fs of the VCO 2 is counted by a divided frequency fx (=fs/n) divided at a frequency dividing ratio (n), the digital count value of N bits is converted into an analog signal at a prescribed level and fed back to the VCO 2 as a control signal Vc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator in which a control signal is generated from a partial output of a voltage controlled oscillator circuit and fed back to the voltage controlled oscillator circuit to stabilize the oscillation frequency.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional oscillator. The oscillator 100 in the figure is a PLL (Phase Locked Loo).
p) Synthesizer-based oscillator, VCO (Voltage Con
trolled oscillator (voltage controlled oscillator circuit) 101, VC
A divider 102 that divides the output signal fs into two in order to feed back a part of the oscillation output fs of O101, divides the output signal fs by a predetermined division ratio n, and divides the signal of frequency fx = fo / n. , A frequency divider 103 for generating the phase difference, a phase comparator 104 for comparing the frequency-divided signal fx with a reference signal fr and detecting a phase difference Δθ (= fx−fr), and a phase difference detected by the phase comparator. The control signal V of the VCO 101 is obtained by integrating Δθ.
It is configured by an LPF (low-pass filter) 105 that generates c.

In the above structure, the phase comparator 104 and the LPF 105 generate a control signal Vc that provides a phase difference Δθ = 0, that is, fr = fx, and this control signal Vc is VCO1.
01 is fed back to the oscillator 100.
Stable oscillation is performed at a frequency fs (= n · fr) multiplied by n.

[0004]

The above-mentioned conventional oscillator 10
In the case of 0, the control signal to be fed back to the VCO 101 is generated by filtering the output signal of the phase comparator 104 by the LPF 105, so that the filter characteristic and transient response characteristic of the LPF 105 greatly affect the oscillation characteristic of the oscillator 100. That is, if the filter characteristic of the LPF 105 is not good, the high frequency component of the output signal of the phase comparator 104 is not sufficiently removed, the accuracy of oscillation control of the VCO 101 is lowered, and if the transient response characteristic of the LPF 105 is not good, VC
It takes a long time to stabilize O101. Therefore, in designing the oscillator 100, it is necessary to suitably design the filter characteristic and the delay characteristic of the LPF 105, but it is generally difficult to design both characteristics in a well-balanced manner.

Further, in the actual LPF 105, taking into consideration the stability against changes over time and vibration, 0.01 μF to 0.1 μF.
A film capacitor having a relatively large F is used, which hinders miniaturization and monolithicization of the oscillator 100.

The present invention has been made in view of the above problems, and an object thereof is to provide an oscillator which is highly stable and can be miniaturized.

[0007]

According to the present invention, there is provided a voltage controlled oscillator circuit and a feedback circuit for generating a control signal from a partial output of the voltage controlled oscillator circuit and feeding back the control signal as a control voltage of the voltage controlled oscillator circuit. In the oscillator provided, the feedback circuit, a frequency measuring instrument that measures a predetermined frequency proportional to the oscillation frequency from the output signal of the voltage controlled oscillator circuit by a digital value, and a digital measurement value measured by the frequency measuring instrument. D / for converting to an analog signal and generating the control signal
A converter.

[0008]

According to the present invention, a predetermined frequency proportional to the oscillation frequency is digitally measured from the oscillation output of the voltage controlled oscillation circuit by the frequency measuring device, and this digital measurement value is D
The / A converter converts the signal into an analog signal to generate a control signal for the voltage controlled oscillator circuit. Therefore, the oscillator has the tuning characteristics of the voltage controlled oscillator circuit (characteristics of the oscillation frequency with respect to the control signal) and the output characteristics of the D / A converter (the conversion characteristics of the digital measured value into the analog signal).
Stable oscillation is performed at the frequency determined at the intersection of and.

[0009]

1 is a block diagram of an oscillator according to the present invention. The oscillator 1 is composed of a VCO 2, a divider 3, a frequency divider 4, a frequency counter 5, a D / A converter 6 and a clock generation circuit 7. A feedback circuit is configured.

The output signal Ss of the VCO 2 is divided into two by the divider 3, part of which is fed back to the feedback circuit, and the rest is output. The fed back output signal Ss is input to the frequency divider 4, and the frequency divider 4 generates a divided signal Sx having a frequency fx (= fs / n) obtained by dividing the oscillation frequency fs by n. The frequency fx of the divided signal Sx is
It is counted by the frequency counter 5, and the count value is output as an N-bit digital signal. The frequency counter 5 controls the gate time of the frequency count by the clock signal Sc input from the clock generation circuit 7, and when the frequency count ends, the count value is reset at a predetermined timing. There is.
After the frequency count is completed, the output data of the frequency divider 4 is held at the count value until the count value is reset.

The N-bit digital signal output from the frequency counter 5 is converted into an analog signal of a predetermined level by the D / A converter 6 and fed back to the VCO 2 as a control signal Vc.

FIG. 2 is a circuit diagram of an embodiment of the oscillator according to the present invention. In the figure, VCO2 is SAW
(Surface Acoustic Wave) It is composed of a collector grounded Colpitts oscillator circuit using a resonator. R _A , R _B
Is a bias resistance of a transistor Tr that constitutes an amplifier. Further, C3 is a bypass capacitor of the bias circuit, C4 is a coupling capacitor for extracting the oscillation output, and L2 is an RFC (Radio Frequency Choke) coil for flowing the emitter current of the transistor Tr.

The series circuit of the SAW resonator 21, the capacitor C0 and the varactor diode VD provided between the base of the transistor Tr and the ground is an inductive feedback circuit (L property). A resonance circuit is configured by a series circuit (C characteristic) of capacitors C1 and C2 provided between the base and the emitter and between the emitter and the ground. The capacitor C0 blocks the flow of the control current into the SAW resonator 21, and connects the SAW resonator 21 and the varactor diode VD in series in an alternating current. The inductance of the resonant circuit is equivalent. Can be regarded as the inductance in the series circuit of the SAW resonator 21 and the varactor diode VD.

A control signal (DC voltage) Vc for controlling the oscillation frequency is applied to the cathode of the varactor diode VD via the RFC coil L1, and the control signal Vc is applied.
Is changed, the capacitance of the varactor diode VD is changed, whereby the inductance of the inductive feedback circuit is changed and the oscillation frequency fs of the VCO 2 is changed.

The frequency counter 5 is composed of a 4-bit binary counter in which four JK-flip-flops (hereinafter referred to as FF) 52 to 55 are connected in series. The FFs 52 to 55 are connected in series so that the output terminal Q of the previous stage is connected to the clock input terminal CK of the next stage. Further, the input stage has a gate circuit 51 composed of a NAND circuit, and the output end of the gate circuit 51 has the FF.
52 to FF55 are connected to respective preset terminals PR. Further, the output terminals Q1 to FF52 to FF55
Q4 is connected to the terminals d1 to d4 of the hold circuit 56, and the hold circuit 56 holds the outputs Q1 to Q4 of the FFs 52 to FF 55 at the end of counting.

The hold circuit 56 outputs the F signal at the end of counting.
The outputs Q1 to Q4 of the F52 to FF55 are output to the output terminals D1 to D4, respectively, and the output state is maintained until the next counting ends. In the count value consisting of 4 bits D1 to D4, D1 corresponds to the least significant bit,
4 corresponds to the most significant bit.

The gate circuit 51 has a frequency fx (= fs / n) obtained by dividing the oscillation frequency fs of the VCO 2 by a division ratio n.
The frequency-divided signal Sx and the clock signal Sc generated from the clock generation circuit 7 are input. Therefore, the divided signal Sx is output from the gate circuit 51 during the ON period of the clock signal Sc, and the output signal Sx is used as the count signal by the FF.
52 to FF55 are input to the preset terminals PR.

For example, the oscillation frequency of VCO2 is 300 MHz.
z, frequency division ratio n = 20, frequency fc of clock signal Sc is 1
When set to 00 Hz, the gate circuit 51 opens the gate for 0.01 seconds every 0.01 seconds, and the frequency fx = 15 MHz.
The divided signal Sx is input to the FFs 52 to FF55 to count the frequency fx of the divided signal Sx.

Although not shown, the gate circuit 5
When the gate of 1 is closed and the count period ends, this end information is input to the FFs 52 to FF 55 as a reset signal, the states of the FFs 52 to FF 55 are cleared, and then the gate of the gate circuit 51 is opened. The divided frequency fx of the divided signal Sx is again counted by the FFs 52 to FF 55.

The D / A converter 6 is a current addition type D / A conversion circuit composed of a load resistance, and has a power supply terminal Vcc and an output terminal V.
_A resistor R0 is connected between _OUT, and resistors R1 to R4 having loads satisfying the following relationships are connected in parallel between the output terminal V _OUT and the terminals d1 to d4 corresponding to each bit.

R1 / 2 ¹ = R2 / 2 ² = R3 / 2 ³ = R4 / 2 ⁴ = r (constant) ∴R1 = 2r, R2 = 4r, R3 = 8r, R4 = 16
r Then, by setting the loaded resistors R1 to R4 corresponding to the bits D1 to D4 as described above, the output terminal V
_As shown in FIG. 3, a voltage that linearly decreases in proportion to the oscillation frequency fs is output from OUT.

In the present embodiment, the D / A converter 6 combined with the 4-bit binary counter has been described as an example. However, when the frequency counter 5 is an N-bit binary counter, the output terminal is The D / A converter 6 can be configured by connecting N resistors R1 to RN in parallel between V _OUT and the terminals d1 to dN corresponding to each bit. In this case, the output characteristic of the D / A converter 6 is proportional to the oscillation frequency fs by configuring the resistance RK corresponding to 2 ^ K (2 to the Kth power) bits with 2 ^ K · r (r; constant). The characteristic can be linearly reduced.

The frequency counter 5 and the D / A converter 6
Is a commercially available general-purpose monolithic IC (Integrated C
ircuit) can be easily configured, but D /
Since the A converter 6 is a resistance circuit, the ACO 6 may be configured on the same substrate as the VCO 2 by printing a thick film resistor on the component substrate of the VCO 2. Further, the feedback circuit of the frequency divider 4, the frequency counter 5, and the D / A converter 6 may be configured by a one-chip IC for general purpose. In this way, one type of general-purpose one-chip I
The oscillator 1 having an arbitrary oscillation frequency can be easily configured by combining C with the VCO 2 having different tuning characteristics.

Next, stabilization of the oscillation frequency of the oscillator will be described with reference to FIG. FIG. 4 is a diagram showing the tuning characteristics of the VCO 2 and the output characteristics of the D / A converter 6. In the figure, the vertical axis represents the oscillation frequency f of VCO2.
c represents the control voltage of the VCO 2 (D / A converter 6).
Of the output voltage Vc). Further, indicates the tuning characteristic of the VCO 2, and indicates the output characteristic of the D / A converter 6.

Since the output voltage Vc of the D / A converter 6 is fed back to the control terminal of the VCO 2 as a control voltage, it is V
CO2 has a frequency fs corresponding to an intersection point P1 between the tuning characteristic of the VCO2 and the output characteristic of the D / A converter 6.
It oscillates at 1.

Now, suppose that while the VCO 2 is oscillating at the frequency fs1, the tuning characteristic of the VCO 2 is changed to the'indicated by the dotted line in the figure due to temperature change or the like. D / A
At the present time, the converter 6 has a voltage Vc corresponding to the intersection P1.
Since 1 is output, the oscillation frequency of VCO2 is VC
The frequency fs1 'corresponding to the intersection P2 between the O2 tuning characteristic' and the output characteristic of the D / A converter 6 changes.

When the oscillating frequency of the VCO 2 changes, the output voltage Vc of the D / A converter 6 changes accordingly, and D / A
The A converter 6 has a voltage Vc corresponding to the frequency fs1 '.
1'is output. That is, the D / A converter 6 outputs the voltage Vc1 'corresponding to the intersection P3 between the line parallel to the horizontal axis passing through the intersection P2 and the output characteristic of the D / A converter 6.
On the other hand, this output voltage Vc1 'is VCO2 as a control voltage.
Is fed back to the control voltage Vc, the oscillation frequency of the VCO 2 further changes. That is, V
CO2 is a line parallel to the vertical axis passing through the intersection P3 and the VCO
It oscillates at a frequency fs1 "corresponding to the intersection P4 with the second tuning characteristic '.

Then, the oscillation frequency fs of the VCO 2 will be described below.
The output voltage Vc of the D / A converter 6 changes according to the change of the output voltage Vc, and the output voltage Vc after the change changes as the control voltage VCO.
As shown in FIG. 4, the oscillation frequency fs of the VCO 2 is fed back to the tuning characteristic '.
The tuning characteristics of the VCO 2'and D while sequentially changing to the frequencies corresponding to the points P6, P8, ..., P (2K).
It converges on the intersection point Pn with the output characteristic of the / A converter 6 and stabilizes at the frequency fs2 corresponding to the intersection point Pn.

That is, the oscillation frequency fs of the VCO 2 is
An intersection point P between the changed tuned characteristic and the output characteristic of the D / A converter 6 according to the change of the tuned characteristic of the VCO 2.
It changes to the frequency fs corresponding to n and stabilizes at that frequency fs. Then, as can be seen from FIG. 4, the D / A converter 6
As the slope of the output characteristic of the D / A converter 6 becomes gentle, the rate of change of the oscillation frequency fs of the VCO 2 with respect to the output voltage Vc of the D / A converter 6 becomes small. By setting to, it is possible to configure an oscillator that is stable against environmental changes.

The output characteristic of the D / A converter 6 is preferably made steeper than the inclination of the central portion as shown in FIG. By doing this, VC
Even if the tuning characteristics of O2 deviate greatly from the standard tuning characteristics, the D / A converter 6 causes the VCO
The control voltage within the controllable range of 2 is output, the runaway phenomenon that the oscillation frequency fs of the VCO 2 does not converge is prevented, and the stability of the VCO 2 is further improved.

[0031]

As described above, according to the present invention,
An oscillator provided with a voltage controlled oscillator circuit and a feedback circuit for generating a control signal from a partial output of the voltage controlled oscillator circuit and feeding back the control signal as a control voltage of the voltage controlled oscillator circuit, wherein the feedback circuit comprises: A frequency measuring device for measuring a predetermined frequency proportional to the oscillation frequency with a digital value and a D / A converter for converting the digital measured value into an analog signal, and after generating a control signal by digital processing, Since the control signal is converted into an analog signal and fed back to the voltage controlled oscillator circuit, the response of the feedback circuit can be suitably controlled by controlling the gate time of the frequency measuring instrument.

Further, the above frequency measuring device is a monolithic I
The use of C enables downsizing, general-purpose use, and cost reduction of the oscillator. By forming the D / A converter on the same substrate as the voltage controlled oscillation circuit, downsizing of the oscillator can be achieved.
It is possible to easily make series of oscillators having different oscillation frequencies.

[Brief description of drawings]

FIG. 1 is a block diagram of an oscillator according to the present invention.

FIG. 2 is a circuit configuration diagram of an embodiment of an oscillator according to the invention.

FIG. 3 is a diagram showing output characteristics of a D / A converter.

FIG. 4 is a diagram showing a tuning characteristic of a VCO and an output characteristic of a D / A converter.

FIG. 5 is a block diagram of a conventional oscillator.

[Explanation of symbols]

 1 Oscillator 2 VCO 21 SAW oscillator 3 Divider 4 Frequency divider 5 Frequency counter 51 Gate circuit 52-55 Flip-flop 56 Hold circuit 6 D / A converter 7 Clock generation circuit R0-R4 Resistance VD Varactor diode

Claims (1)

[Claims] 1. An oscillator comprising a voltage controlled oscillator circuit and a feedback circuit for generating a control signal from a partial output of the voltage controlled oscillator circuit and feeding back the control signal as a control voltage of the voltage controlled oscillator circuit. Is a frequency measuring instrument that measures a predetermined frequency proportional to the oscillation frequency from the output signal of the voltage controlled oscillation circuit with a digital value, and the digital measuring value measured by the frequency measuring instrument is converted into an analog signal to control the frequency. An oscillator comprising: a D / A converter that generates a signal.