JPH0786516B2 - Period detection circuit - Google Patents

Description

The present invention relates to a cycle detection circuit, and more particularly to a cycle detection circuit for detecting the cycle of an input signal for driving a cross coil meter used in a speedometer, a tachometer, etc. of an automobile. Regarding

[Prior Art] Conventionally, a cross coil meter for instructing a predetermined angular direction by flowing a current according to an input amount in two exciting coils which are orthogonal to each other has been known, and a speedometer of an automobile or It is widely used in tachometers.

2 and 3 show schematic configuration diagrams of this cross coil meter. The two exciting coils L _{S and} L _C arranged so as to be orthogonal to each other generate a magnetic field in a predetermined angular direction when a pulse current corresponding to an input amount such as speed is supplied.

The rotatably supported permanent magnet M receives torque due to the magnetic fields generated by the two exciting coils L _S and L _C. Then, the indicator needle fixed to the permanent magnet M is
As shown in FIG. 3, the physical quantity (3rd
In the figure, the meter is rotated by θ from the reference position to show the predetermined position of the meter indicating plate on which the speed is displayed, and the indicated value corresponding to the input amount is shown.

An apparatus for driving these cross coil meters used in a speedometer, a tachometer, etc. of an automobile generally has the following configuration. That is, for example, a signal from a speed sensor or a rotation speed sensor that generates a pulse signal having a frequency according to speed or rotation speed is input, while a reference clock signal having a predetermined frequency is input from a reference clock generator. The counter detects one cycle of the input pulse signal by counting the number of pulses of the reference clock signal. Then, the frequency that is the reciprocal of the cycle is calculated, and the current corresponding to the calculated frequency is pulse width modulated (PWM) by the pulse width modulator, and the two exciting coils L _S and L _C orthogonal to each other are energized. Then, the meter is instructed according to the input amount.

[Problems to be Solved by the Invention] As described above, when driving the cross coil meter, the period of the input pulse signal from the speed sensor or the rotation speed sensor is set to a reference clock signal having a predetermined reference frequency (for example, 2 MHz). It is detected by counting the number of pulses of and the two exciting coils are energized based on the detected period.
Generally, the maximum frequency of the input signal to be detected, that is, the minimum cycle, differs depending on the model of the vehicle equipped with the speedometer or tachometer, so the number of bits of the counter that counts the number of pulses of the reference clock signal increases. There was a problem that it would end up.

Now, the maximum frequency of the input pulse signal that should be detected in the cycle is 250 Hz, 50
Consider the case where it is different from 0Hz, 1KHz and 2KHz. When the counter counts the cycle of the input pulse signal by the reference clock signal, the detection error of the cycle of the input pulse signal due to the quantization error at the time of counting is less than a predetermined value
1000 or less), it becomes necessary to include the number of reference clock pulses of 1000 or more. Therefore, when the maximum input frequency is f max, the reference clock frequency is 1000
Must be greater than or equal to ax and f as in the previous case
When max = 2KHz, it becomes 2MHz or more.

Therefore, if the frequency of the reference clock signal is 2 MHz, the counter that counts the number of pulses of this reference clock signal has an input frequency of 0H when the resolution of the meter display is 1/1000.
It is necessary to judge whether it is z or 2Hz, and if the judgment line is set to 1Hz, the number of counts obtained will be 2,000,000 and a 21-bit counter will be required.

However, when counting the period of the input pulse signal with the reference clock signal having a certain frequency of 2 MHz as described above, the maximum frequency of the input signal is 2 KHz.
A bit counter is sufficient, but for an input pulse signal with a maximum frequency of 1 KHz, the cycle is twice that of a 2 KHz signal.
A 22-bit counter is required. Furthermore, the highest frequency
4 times for the input pulse signal of 500Hz, that is, 23
When a bit is required and an input pulse signal whose maximum frequency is 250 Hz is reached, a counter of 8 times, that is, 24 bits is required.

Of course, if the number of bits is increased in this way, the accuracy is improved, but even if the accuracy is unnecessarily increased, the angular azimuth indicated by the relationship with the resolution of the meter is hardly affected. It is not practical to increase the accuracy.

The present invention has been made in view of the above conventional problems, and an object thereof is a cycle in which the cycle of an input pulse signal having various maximum frequencies can be detected by one circuit without increasing the number of bits of a counter. It is to provide a detection circuit.

[Means for Solving the Problems] In order to achieve the above object, the cycle detection circuit of the present invention detects a cycle of an input signal having a different maximum frequency by counting the number of pulses of a reference clock signal. The storage means for storing the frequency division ratio corresponding to each of the different maximum frequencies, the control means for reading out the frequency division ratio corresponding to the maximum frequency of the input signal from the storage means, and the read-out division A frequency divider for dividing the frequency of the reference clock signal by a frequency ratio, and detecting the period of the input signal by the frequency-divided reference clock signal.

[Operation] As described above, the cycle detection circuit of the present invention does not count the cycle of the input signal with the reference clock signal having a predetermined frequency as in the prior art, but the minimum cycle of the input signal, that is, the maximum cycle, which differs depending on the meter. The frequency of the reference clock signal is appropriately divided according to the frequency, and the divided reference clock signal counts the cycle of the input signal.

That is, when the minimum cycle of the input signal is T _min , that is, when the frequency of the reference clock signal used when counting the cycle of the input signal whose maximum frequency is f _max is f _ref , the minimum cycle is 2T _min , that is, the maximum frequency is When counting the period of the input signal of f _max / 2, the reference clock signal is divided and its frequency is set to f _ref / 2.

In this way, by dividing the frequency of the reference clock signal in proportion to the maximum frequency of the input signal, the same count number can be obtained when counting input signals with different maximum frequencies. It is possible to detect the cycle with the same accuracy without increasing.

[Embodiment] An embodiment will be described below with reference to the drawings, in which an embodiment of the cycle detection circuit of the present invention is applied to a drive device for driving a cross coil meter used in an automobile speedometer.

FIG. 1 is a configuration block diagram of this embodiment. The speed sensor 10 is attached to a transmission case of an automobile or the like, and outputs a pulse according to the rotation speed of the driven gear. As the speed sensor 10, a magnetic sensor using a magnetoresistive element (MRE) that utilizes a so-called magnetoresistive effect, which is a change in electric resistance caused by applying a magnetic field to a conductor or a semiconductor through which a current is flowing, is widely used. Cage,
A pulse signal corresponding to the rotational speed of the driven gear, that is, the vehicle speed is output by the change in the direction of the magnetic field generated by the magnet ring that rotates together with the driven gear. Then, the pulse signal from the speed sensor 10 is a cycle detection circuit.
Entered in 14.

On the other hand, the reference clock generator 16 generates a reference clock signal having a frequency of 2 MHz, which is characteristic in this embodiment is that the reference clock signal from the reference clock generator 16 is input from the speed sensor 10. A configuration is provided in which a frequency divider 20 that divides at a frequency division ratio according to the highest frequency of the pulse signal is provided, and the period detection circuit 14 counts the period T by the divided reference clock signal sent from the frequency divider 20. There is that. In this embodiment, the maximum frequency f _max of the input pulse signal from the speed sensor 10 depends on the vehicle type.
The frequency division ratio of the frequency divider 20 is 1, 1/2, 1/2 ² = 1/4, 1/2 ³ to correspond to the case different from 2KHz, 1KHz, 500Hz and 250Hz.
It can be set in 4 steps of 1/8. The data of the four division ratios can be electrically erased and written to E ²
When the maximum frequency of the input pulse signal is 2KHz, the frequency division ratio is 1, that is, when the frequency of the reference clock signal is 2MHz or 1KHz. Divide ratio 1 /
2, the frequency of the reference clock signal is 1MHz, the division ratio is 1/4 when 500Hz, that is, the frequency of the reference clock signal is 500KHz, and the division ratio is 1/8 when 250Hz,
That is, the frequency of the reference clock signal can be set to 250 KHz. Then, the reference clock signal thus appropriately divided is input to the cycle detection circuit 14.

The cycle detection circuit 14 has a 21-bit latch counter therein, and the counter detects the cycle T of the input pulse signal by counting the number of pulses of the reference clock signal.

Now, in the present embodiment, since the reference clock signal is divided by the maximum frequency f _max of the input pulse signal as described above, the specification that the quantization error is 1/1000 or less is satisfied, and the counter bit It is possible to reduce the number to 21 bits. That is, when counting the cycle of the input pulse signal with the highest frequency of 2KHz, the reference clock frequency is 2MHz (division ratio 1), and 1Hz required to satisfy the resolution of the meter display 1/1000 is counted. The number of counts to be made is 2,000,000, and it is possible to count with 21 bits. And the maximum input frequency is 1KHz
Since the frequency of the reference clock signal is 1/2 even when counting the cycle of the input pulse signal of, that is, 1MHz, the count that counts the input frequency necessary to satisfy the resolution 1/1000 of the meter display. The number can be as high as 2,000,000 with a maximum input frequency of 2KHz, so it can be counted in 21 bits. Maximum input frequency is 500Hz, 250
Similarly, in the case of Hz, the reference clock frequency is 500 KHz, 25
Since it is 0 KHz, it is understood that 21 bits can be counted without increasing the number of bits.

The period T of the input pulse signal counted by the counter of the period detection circuit 14 is sent to the arithmetic processing block 18 which performs various arithmetic processes. The calculation processing block 18 calculates the reciprocal of the cycle T sent from the cycle detection circuit 14 to calculate the frequency. And for control according to the calculated frequency
The deflection angle θ of the meter is calculated using the parameters supplied from the CPU. Further, sin cos calculation of the calculated deflection angle θ is performed and output to the driving means 24.

The driving means 24 is two pulse width modulation circuits 24 for sin and cos for pulse width modulating the output signal from the arithmetic processing block 18.
a, a quadrant determiner 24b and an output driver 24c that directly drives the cross coils L _S and L _C , the same number as the number of cross coils to be driven is provided, and the modulated pulse current is applied to the cross coils L _S , By energizing L _C , it is excited to drive the meter, and the meter is instructed according to the input amount.

As described above, the present invention does not count the period T of the input pulse signal with the reference clock signal having a predetermined frequency, but an appropriate pulse count number according to the maximum frequency of the input pulse signal which differs depending on the vehicle type to be mounted. In order to obtain, the frequency of the reference clock signal is divided and counted, without increasing the number of bits of the counter,
The period T of the input pulse signal can be detected with sufficient accuracy.

In addition, in the present embodiment, the case where it is applied to the device for driving the cross coil meter used in the speedometer of the automobile is shown, but the present invention is not limited to this, and any digital signal can be used. It goes without saying that it can be used in a device that detects the cycle T of and uses it.

[Effects of the Invention] As described above, according to the cycle detection circuit of the present invention, it is possible to deal with input pulse signals of a wide range of frequencies without increasing the number of bits of the counter. There is an effect that the bus line width of the hardware can be reduced and the circuit scale can be reduced while having general versatility to cope with the input pulse signal.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an embodiment of a cycle detection circuit according to the present invention, and FIGS. 2 and 3 are operation explanatory views for explaining the operation of a cross coil meter. 10 …… Speed sensor 12 …… Control CPU 14 …… Cycle detection circuit 16 …… Reference clock generation path 18 …… Arithmetic processing block 20 …… Divider 22 …… E ² PROM 24 …… Driving means

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masakazu Kobayashi 2-1910 Nisshin-cho, Omiya-shi, Saitama Kanto Seiki Co., Ltd. (72) Masanori Narita 2-1910 Nisshin-cho, Omiya-shi, Saitama Kanto Seiki Within the corporation

Claims (1)

[Claims] 1. A cycle detection circuit for detecting a cycle of an input signal having a different maximum frequency by counting the number of pulses of a reference clock signal, wherein a frequency division ratio corresponding to each of the different maximum frequencies is stored. Storage means, control means for reading out a frequency division ratio corresponding to the maximum frequency of the input signal from the storage means, and a frequency divider for dividing the frequency of the reference clock signal by the read frequency division ratio. Then, the cycle detection circuit detects the cycle of the input signal by the frequency-divided reference clock signal.