JPH0786482A - Lead terminal structure of surface mount component - Google Patents

Lead terminal structure of surface mount component

Info

Publication number
JPH0786482A
JPH0786482A JP5232717A JP23271793A JPH0786482A JP H0786482 A JPH0786482 A JP H0786482A JP 5232717 A JP5232717 A JP 5232717A JP 23271793 A JP23271793 A JP 23271793A JP H0786482 A JPH0786482 A JP H0786482A
Authority
JP
Japan
Prior art keywords
lead terminal
surface mount
solder
solder paste
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5232717A
Other languages
Japanese (ja)
Inventor
Hiromoto Uchida
浩基 内田
Seiki Sakuyama
誠樹 作山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5232717A priority Critical patent/JPH0786482A/en
Publication of JPH0786482A publication Critical patent/JPH0786482A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3405Edge mounted components, e.g. terminals
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To eliminate the occurrence of defective soldering at the time of soldering surface mount components. CONSTITUTION:A pattern is formed in advance on a wiring board and lead terminals are soldered to a plurality of pads composed of metallic thin films by positioning the lead terminals by making them abutting on the pads after printing paste on the pads and passing the wiring board through a reflow furnace. In such a lead frame structure for surface mount components, the front ends of the lead terminals are folded up in parallel with gaps for generating capillary phenomena in between.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明ははんだ付け不良を抑制し
たリード端子構造に関する。現在、情報処理装置や通信
機器においては電子部品の表面実装が一般的に行なわれ
ている。すなわち、プリント配線基板やセラミック配線
基板上にパターン形成してあるボンディングパッド位置
にスクリーン印刷などの方法ではんだペーストを塗布し
ておき、この位置にフラットパッケージ・タイプのIC
やチップ・タイプのコンデンサや抵抗器などの端子を位
置決めし、はんだの融点に対応して加熱温度が設定して
ある電気炉中を通すリフローソルダリングによりはんだ
付けが行なわれて電子回路が形成されている。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead terminal structure which suppresses defective soldering. At present, surface mounting of electronic components is generally performed in information processing devices and communication devices. That is, a solder paste is applied to a bonding pad position formed on a printed wiring board or a ceramic wiring board by a method such as screen printing, and a flat package type IC is applied to this position.
The terminals such as chip type capacitors and resistors are positioned and soldered by reflow soldering through an electric furnace in which the heating temperature is set according to the melting point of the solder to form an electronic circuit. ing.

【0002】[0002]

【従来の技術】表面実装技術(Surface Mounting Techn
ology 略称SMT)は情報処理装置の主体を構成するL
SIやVLSIなどの半導体集積回路を基板上に高密度
に装着する実装方法であるが、これを装着する基板には
夥しい数の配線パターンの形成が必要となる。
[Prior Art] Surface Mounting Techn
ology abbreviation SMT) is an L that constitutes the main body of the information processing device.
This is a mounting method in which semiconductor integrated circuits such as SI and VLSI are mounted on a substrate with high density, but it is necessary to form a large number of wiring patterns on the substrate on which this is mounted.

【0003】すなわち、ICやLSIなど、半導体集積
回路の形成には少なくとも信号線,電源線,グランド線
などの配線形成が必要であるが、集積度が向上するに従
ってこれらの配線数は増加し、また、基板上には半導体
集積回路を密に搭載することから、これを搭載する回路
基板は必然的に多層構造となり、最上層には薄膜形成技
術と写真蝕刻技術(フォトリソグラフィ)を用いて微細
なボンディングパッドを多数形成し、このボンディング
パッドを用いて電子部品の表面実装が行なわれている。
That is, at least wirings such as signal lines, power supply lines, and ground lines are required to form semiconductor integrated circuits such as ICs and LSIs. The number of these wirings increases as the degree of integration increases. Further, since the semiconductor integrated circuits are densely mounted on the substrate, the circuit board on which the semiconductor integrated circuits are mounted inevitably has a multilayer structure, and the uppermost layer is formed by a thin film forming technique and photolithography technique (photolithography). A large number of different bonding pads are formed, and the electronic components are surface-mounted using the bonding pads.

【0004】然し、基板上に形成されているボンディン
グパッドの数は夥しく多く、一方、この寸法は非常に小
さい。いま、一例を挙げると、横32 mm , 縦28 mm , 高
さ4.4 mm のフラットパッケージを構成するリード端子
の数は104 本であり、また、横44 mm , 縦40 mm , 高さ
4.4 mm のフラットパッケージを構成するリード端子の
数は168 本であり、リード端子は厚さが0.2 〜0.3 mm
の銅合金を用いで形成されているが、これが0.8 mm 程
度の端子ピッチで配列して形成されている。
However, the number of bonding pads formed on the substrate is extremely large, while the size thereof is very small. Now, as an example, the number of lead terminals that make up a flat package of 32 mm in width, 28 mm in height, and 4.4 mm in height is 104, and 44 mm in width, 40 mm in height, and 40 mm in height.
The number of lead terminals that make up a 4.4 mm flat package is 168, and the thickness of the lead terminals is 0.2 to 0.3 mm.
Of copper alloy, which are arranged with a terminal pitch of about 0.8 mm.

【0005】また、更に集積度を増したLSIを搭載す
るフラットパッケージについては、格段にリード端子の
数が増しており、端子ピッチは0.3 mm 程度まで縮小し
てきている。そのため、ボンディングパッドはリード端
子のピッチに対応して基板上にパターン形成されてい
る。
Further, in a flat package mounting an LSI having a higher degree of integration, the number of lead terminals has been remarkably increased, and the terminal pitch has been reduced to about 0.3 mm. Therefore, the bonding pads are patterned on the substrate corresponding to the pitch of the lead terminals.

【0006】こゝで、基板上に装着される表面実装部品
は一種類に限らず、数多く存在しており、また、ボンデ
ィングパッドの大きさとピッチはそれぞれの電子部品に
特有なものであって、それぞれ、基板上にパターン形成
されている。
Here, the number of surface mount components mounted on the substrate is not limited to one type, and there are many types, and the size and pitch of the bonding pads are peculiar to each electronic component. Each pattern is formed on the substrate.

【0007】基板上には、このように大きさとピッチの
異なるボンディングパッドが多数パターン形成されてお
り、表面実装に当たっては、先ず、メタルマスクを用い
てはんだペーストをボンディングパッド上に印刷し、次
に、表面実装部品のリード端子をボンディングパッドに
当接して位置合わせし、この状態ではんだの融点に合わ
せて温度設定してあるリフロー炉を通すことにより、は
んだ付けが行なわれている。
A large number of bonding pads having different sizes and pitches are formed on the substrate in this way. For surface mounting, first, a solder paste is printed on the bonding pads using a metal mask, and then the bonding pads are printed. The lead terminals of the surface mount components are brought into contact with the bonding pads to be aligned with each other, and in this state, a reflow furnace whose temperature is set according to the melting point of the solder is passed through to perform soldering.

【0008】然し、ボンディングパッド上に印刷してあ
るはんだペーストが過多である場合は、ボンディングパ
ッドよりはんだが溢れて隣接するボンディングパッドに
接触して所謂るはんだブリッジを生じてショート状態と
なり、また、過少である場合は接続不良を生じて断線状
態となり信頼性を低下させている。
However, when the amount of the solder paste printed on the bonding pad is excessive, the solder overflows from the bonding pad and comes into contact with an adjacent bonding pad to form a so-called solder bridge, resulting in a short circuit state. If it is too small, a connection failure will occur and a wire breakage will result, reducing reliability.

【0009】[0009]

【発明が解決しようとする課題】表面実装を行なう多層
回路基板上には微少なピッチで小面積のボンディングパ
ッドがパターン形成されているが、リフローソルダーリ
ング後の段階ではんだブリッジや断線などのはんだ付け
不良が発生し易い。そこで、この解決が課題である。
Although a bonding pad having a small area is patterned at a fine pitch on a multi-layered circuit board for surface mounting, solder bridges, disconnections, or other solder may occur after reflow soldering. Poor attachment is likely to occur. Therefore, this solution is an issue.

【0010】[0010]

【課題を解決するための手段】上記の課題は配線基板上
にパターン形成してあり、金属薄膜よりなる複数のパッ
ド上に、予めはんだペーストを印刷した後、このパッド
に電子部品のリード端子を当接して位置決めを行い、リ
フロー炉を通すことにより、はんだ付けを行なう電子部
品のリード端子において、リード端子の先端が毛管現象
を生ずる間隙を隔てゝ平行に折り畳んであることを特徴
として表面実装部品のリード端子構造を構成することに
より解決することができる。
Means for Solving the Problems The above-mentioned problem is that a pattern is formed on a wiring board, and after solder paste is printed in advance on a plurality of pads made of a metal thin film, the lead terminals of electronic parts are attached to the pads. In the lead terminal of the electronic component to be soldered by contacting and positioning and passing through the reflow oven, the tip of the lead terminal is folded in parallel with a gap that causes a capillary phenomenon. This can be solved by configuring the lead terminal structure of.

【0011】[0011]

【作用】表面実装のリフローソルダリング工程におい
て、ショートや断線が生じるのは各ボンディングパッド
へのはんだペーストの塗布量が適正でないためである。
こゝで、はんだペーストははんだ粉末とフラックスビヒ
クル (Flux-vehicle) とを重量比で9:1程度に混合物
したものであり、はんだの構成金属,粉末の粒度と形
状,フラックスビヒクルの構成材料などにより各種のは
んだペーストが実用化されているが、最も一般的なはん
だ構成金属は錫(Sn)63 重量%- 鉛(Pb)37重量%よりな
る共晶はんだで融点は183 ℃である。一方、フラックス
ビヒクルはロジン(松脂 Rosin),増粘剤, 溶剤, 活性剤
などを主成分として構成されており、これらの種類と濃
度を変えることにより多種多用な性質をもつフラックス
ビヒクルが作られている。
In the surface mount reflow soldering process, short circuits and disconnections occur because the amount of solder paste applied to each bonding pad is not appropriate.
Here, the solder paste is a mixture of solder powder and flux vehicle in a weight ratio of about 9: 1. The constituent metal of the solder, the particle size and shape of the powder, the constituent material of the flux vehicle, etc. Although various solder pastes have been put into practical use, the most common solder constituent metal is a eutectic solder consisting of 63 wt% tin (Sn) -37 wt% lead (Pb) and has a melting point of 183 ° C. On the other hand, the flux vehicle is composed mainly of rosin (pine resin Rosin), a thickener, a solvent, an activator, etc. By changing the types and concentrations of these, flux vehicles with various versatile properties are made. There is.

【0012】さて、配線基板にパターン形成してあるボ
ンディングパッドへのはんだペーストの塗布はメタルマ
スクを用いて行なわれているが、はんだペーストの塗布
厚はメタルマスクの厚さにより自ずから決まっており、
適当な塗布厚は経験と実績から発明者等はボンディング
パッドのピッチが0.8 mm のものについては、はんだペ
ーストの厚さは200 μm ,0.5 mm ピッチのものには150
μm ,0.3 mm ピッチのものには100 μm の厚さを採用し
ている。
The solder paste is applied to the bonding pads formed on the wiring board by using a metal mask. However, the applied thickness of the solder paste is naturally determined by the thickness of the metal mask.
Appropriate application thicknesses are based on experience and achievements.The inventors have found that solder paste thicknesses of 200 μm and 0.5 mm pitch are 150 mm for bonding pad pitches of 0.8 mm.
The thickness of 100 μm is adopted for the one with μm and 0.3 mm pitch.

【0013】然し、実際の配線基板には大きさとピッチ
の異なる多種類のボンディングパッドがパターン形成さ
てあることから、発明者等は代表的なはんだペースト厚
として200 μm を採用しているが、この場合にはこれよ
りピッチの狭いリード端子を備えたパッケージでは短絡
障害が生じ易く、一方、これよりピッチの広いリード端
子を備えたパッケージや部品でははんだペーストの量が
不足することになるが、接触不良を生じない限り、はん
だペーストの不足は致命的ではない。
However, since many kinds of bonding pads having different sizes and pitches are patterned on an actual wiring board, the inventors have adopted a typical solder paste thickness of 200 μm. In this case, a package with lead terminals with a narrower pitch is more likely to cause a short-circuit fault, while a package or component with a lead terminal with a wider pitch will lack the amount of solder paste. A lack of solder paste is not fatal, unless it causes defects.

【0014】そこで、本発明はボンディングパッドの上
に必要以上に塗布されているはんだペーストを吸収し、
はんだブリッジの発生を防ぐ方法としてリード端子の先
端を折り曲げ、毛細管現象を生じさせて余分のはんだペ
ーストを吸収するものである。すなわち、図2は従来の
フラットパッケージのリード端子構造を示すものであ
り、リード端子1の先端はフォーミング加工により折り
曲げてあり、先端部2をボンディングパッドに当接して
はんだ付けしているが、本発明は図1の(A),(B)
に示すように先端部3,4を上向き或いは下向きに重ね
合わせるように折り曲げるものである。
Therefore, the present invention absorbs the solder paste excessively applied on the bonding pad,
As a method of preventing the generation of solder bridges, the tip of the lead terminal is bent to cause a capillary phenomenon to absorb excess solder paste. That is, FIG. 2 shows a conventional lead terminal structure of a flat package. The tip of the lead terminal 1 is bent by a forming process, and the tip portion 2 is brought into contact with a bonding pad for soldering. The invention is shown in FIGS. 1A and 1B.
As shown in FIG. 3, the tip portions 3 and 4 are bent so that they are superposed upward or downward.

【0015】こゝで、毛細管現象は液体中に毛細管を立
てると液面が上がるか、または下がる現象であって、液
体の管に対する濡れ性が大きい(付着力が大きい) 場合
は液面は上昇し、一方、濡れ性が小さいときは降下する
現象であるが、はんだペーストのリード端子に対する濡
れ性は極めて良い。
Here, the capillarity phenomenon is a phenomenon that the liquid level rises or falls when a capillary is erected in the liquid, and the liquid level rises when the wettability of the liquid to the pipe is large (adhesiveness is large). On the other hand, when the wettability is small, it is a phenomenon of dropping, but the wettability of the solder paste to the lead terminals is extremely good.

【0016】すなわち、はんだペーストは、リフロー工
程において、はんだペーストの温度上昇と共に溶剤が蒸
発して粘度が上昇し、ロジンの被覆により外気を遮断
し、活性剤により金属表面を活性化した状態で溶融した
はんだが金属に濡れることにより、はんだ付けが行なわ
れるよう構成されているが、加熱により溶剤が蒸発する
段階で濡れ性が向上し、良好なはんだ付けが行なわれて
いる。本発明はリフローソルダーリングの際の濡れ性の
向上を利用し、余分のはんだペーストを毛細管現象を利
用して吸い取るものである。
That is, in the reflow process, the solder paste melts in a state where the solvent evaporates and the viscosity rises as the temperature of the solder paste rises, the rosin coating blocks the outside air, and the activator activates the metal surface. Although the soldering is carried out by wetting the solder with the metal, the wettability is improved at the stage where the solvent is evaporated by heating and good soldering is carried out. The present invention utilizes the improvement of wettability at the time of reflow soldering, and absorbs excess solder paste by utilizing a capillary phenomenon.

【0017】[0017]

【実施例】はんだペーストを構成するはんだは、融点が
183 ℃でSn 63 重量%- Pb 37 重量%よりなる共晶はん
だ(粒径20〜45μm )で融点は183 ℃である。一方、フ
ラックスビヒクルはロジン(松脂 Rosin),増粘剤, 溶
剤, 活性剤などを主成分として構成されており、はんだ
ペーストの粘度は300,00 cp である。
Example: The melting point of the solder that constitutes the solder paste is
It is a eutectic solder (grain size 20-45 μm) consisting of Sn 63 wt% -Pb 37 wt% at 183 ° C and its melting point is 183 ° C. On the other hand, the flux vehicle is composed mainly of rosin (pine resin Rosin), a thickener, a solvent, an activator, etc., and the viscosity of the solder paste is 300,00 cp.

【0018】また、配線基板上にはピッチが900 μm と
150 μm の二種類のフラットパッケージ搭載用のボンデ
ィングパッドをパターン形成した。すなわち、一方は幅
500μm で長さが2.41 mm のボンディングパッドが900
μm のピッチで100 個配列しており、他方は150 μm ピ
ッチで300 個配列してパターン形成されている。
On the wiring board, the pitch is 900 μm.
Bonding pads for mounting two types of flat packages of 150 μm were patterned. Ie one is width
900 bond pads with 500 μm and 2.41 mm length
The pattern is formed by arranging 100 pieces at a pitch of μm and the other 300 pieces at a pitch of 150 μm.

【0019】この配線基板に対して厚さが400 μm のメ
タルマスクを用い、はんだペーストを印刷して後、各フ
ラットパッケージのリード端子を当接した。こゝで、ピ
ッチ900 μm のフラットパッケージのリード端子( 幅30
0 μm , 厚さ170 μm)に対してはペーストの厚さ400 μ
m は適正であるため、リード端子の先端は折り曲げず従
来の形状のものを用いたが、ピッチ150 μm のフラット
パッケージのリード端子( 幅100 μm , 厚さ170 μm)は
図1(A)に示すように折り曲げ加工を施して当接し
た、また、従来のように折り曲げないフラットパッケー
ジも比較のために搭載した。そして、最高温度が250 ℃
に設定してあるリフロー炉を通してはんだ付けを行なっ
た。
A solder mask was printed on this wiring board using a metal mask having a thickness of 400 μm, and then lead terminals of each flat package were brought into contact with each other. This is a flat package lead terminal with a pitch of 900 μm (width 30
0 μm, thickness 170 μm), paste thickness 400 μm
Since m is appropriate, the tip of the lead terminal was not bent and the conventional shape was used, but the lead terminal (width 100 µm, thickness 170 µm) of the flat package with a pitch of 150 µm is shown in Fig. 1 (A). For comparison, a flat package which is bent and abutted as shown, and which is not bent as in the conventional case is also mounted. And the maximum temperature is 250 ℃
Soldering was performed through the reflow furnace set to.

【0020】その結果、900 μm ピッチのパッケージ
と、リード端子を折り曲げ加工した150 μm ピッチのパ
ッケージについてははんだ付け不良は認められなかった
ものゝ、曲げ加工を施さない150 μm ピッチのパッケー
ジについてははんだブリッジの発生率は23%であった。
As a result, no soldering failure was found in the package of 900 μm pitch and the package of 150 μm pitch in which the lead terminals were bent, and in the package of 150 μm pitch without bending, soldering was performed. The incidence of bridges was 23%.

【0021】[0021]

【発明の効果】毛細管現象を利用して余分のはんだペー
ストを吸収する本発明の実施によりはんだブリッジの発
生を防ぐことができ、これによりピッチの異なる各種の
ボンディングパッドが配列している場合でも歩留りよく
ボンディングを行なうことができる。
EFFECTS OF THE INVENTION By implementing the present invention in which excess solder paste is absorbed by utilizing the capillary phenomenon, it is possible to prevent the occurrence of solder bridges, and thus the yield is improved even when various bonding pads with different pitches are arranged. Good bonding can be performed.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明を実施したフラットパッケージのリー
ド端子構造である。
FIG. 1 is a lead terminal structure of a flat package embodying the present invention.

【図2】 従来のフラットパッケージのリード端子構造
である。
FIG. 2 is a lead terminal structure of a conventional flat package.

【符号の説明】[Explanation of symbols]

1 リード端子 2,3,4 先端部 1 Lead terminal 2, 3, 4 Tip

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 配線基板上にパターン形成してあるボン
ディングパッド上に、予めはんだペーストを印刷した
後、該パッドにリード端子を当接して位置決めを行い、
リフロー炉を通すことにより、はんだ付けを行なう表面
実装部品のリード端子において、 該リード端子の先端が毛管現象を生ずる間隙を隔てゝ平
行に折り畳んで設けてあることを特徴とする表面実装部
品のリード端子構造。
1. A solder paste is printed in advance on a bonding pad which is patterned on a wiring board, and a lead terminal is brought into contact with the pad for positioning.
In a lead terminal of a surface mount component to be soldered by passing through a reflow oven, the lead of the surface mount component is characterized in that the tip of the lead terminal is folded in parallel with a gap that causes a capillary phenomenon. Terminal structure.
JP5232717A 1993-09-20 1993-09-20 Lead terminal structure of surface mount component Withdrawn JPH0786482A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5232717A JPH0786482A (en) 1993-09-20 1993-09-20 Lead terminal structure of surface mount component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5232717A JPH0786482A (en) 1993-09-20 1993-09-20 Lead terminal structure of surface mount component

Publications (1)

Publication Number Publication Date
JPH0786482A true JPH0786482A (en) 1995-03-31

Family

ID=16943686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5232717A Withdrawn JPH0786482A (en) 1993-09-20 1993-09-20 Lead terminal structure of surface mount component

Country Status (1)

Country Link
JP (1) JPH0786482A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081238A (en) * 2005-09-15 2007-03-29 Teikoku Tsushin Kogyo Co Ltd Surface mount type electronic component and its carrier tape

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081238A (en) * 2005-09-15 2007-03-29 Teikoku Tsushin Kogyo Co Ltd Surface mount type electronic component and its carrier tape

Similar Documents

Publication Publication Date Title
US7145236B2 (en) Semiconductor device having solder bumps reliably reflow solderable
US5118029A (en) Method of forming a solder layer on pads of a circuit board and method of mounting an electronic part on a circuit board
US5133495A (en) Method of bonding flexible circuit to circuitized substrate to provide electrical connection therebetween
EP0769346A1 (en) Composite solder paste for flip chip bumping
KR100317717B1 (en) Improved Solder Paste Mixture
JPH08227613A (en) Conductive material and usage thereof
US20070007323A1 (en) Standoff structures for surface mount components
EP0947125B1 (en) Method of making a printed circuit board having a tin/lead coating
JP3143441B2 (en) Solder bump input / output pads for surface mount circuit devices
US5641995A (en) Attachment of ceramic chip carriers to printed circuit boards
JPH0786482A (en) Lead terminal structure of surface mount component
JP2002076605A (en) Semiconductor module and circuit board for connecting semiconductor device
JP2646688B2 (en) Electronic component soldering method
US5962151A (en) Method for controlling solderability of a conductor and conductor formed thereby
KR101005505B1 (en) Method of mounting electronic parts on wiring board
JPH02234447A (en) Method of connection semiconductor integrated circuit element
US6391678B1 (en) Method for controlling solderability of a conductor and conductor formed thereby
JP2795535B2 (en) Electronic component mounting method on circuit board
US20060049238A1 (en) Solderable structures and methods for soldering
JP2003249746A (en) Printed wiring board
Hsu et al. Tombstoning Investigation of Ultra-small Chip Passive Components on eMMC Products
JP3516983B2 (en) Method of manufacturing printed circuit board and method of mounting surface mount component
JPH0780682A (en) Solder paste
JPH0330492A (en) Mounting of electronic component
JPS598391A (en) Solder plate for mounting planarly

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20001128