JPH0786421A - Complementary type mos transistor and its manufacture - Google Patents

Abstract

PURPOSE:To prevent mutual diffusion of impurities in a silicon layer, by isolating and forming a silicon layer above a P/N junction part composed of a silicon layer in which P-type impurities are introduced and a silicon layer in which N-type impurities are introduced. CONSTITUTION:An amorphous silicon layer 6 is formed by using a CVD method. P-type impurities like B are selectively ion-implanted in the amorphous silicon layer 6 of the P-channel transistor forming region. N-type impurities like P are selectively ion-implanted in the amorphous silicon layer 6 of the N-channel transistor forming region. A tungsten silicide layer 7 is formed on the amorphous silicon layer 6 by using a CVD method. From the part above a P/N junction part composed of the respective amorphous silicon layers 6 in which the P-type impurities or the N-type imprities are introduced, the tungsten silicide layer 7 is eliminated and an aperture 8 is formed for isolation. Thereby the P-type impurities and the N-type impurities which are introduced in the silicon layer 6 can be prevented from mutually diffusing via the silicide layer 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary MOS transistor and its manufacturing method.

[0002]

2. Description of the Related Art A cross sectional view of a conventional complementary MOS transistor is shown in FIG. In the figure, 1 is a P-type silicon substrate, 2 is a field insulating film, 3 is an N-type well, 4 is a P-type well, 5 is a gate insulating film, and 6 is a polycrystalline silicon layer. Therefore, a P-type impurity is introduced into the P-channel transistor region, and an N-type impurity is introduced into the N-channel transistor region. A silicide layer 7 constitutes a gate electrode together with the polycrystalline silicon layer 6. Reference numeral 12 is an insulating film, and 14 is an aluminum electrode.

Both the P-channel transistor and the N-channel transistor have N-type impurities introduced into the gate electrode of the initial complementary MOS transistor, and the P-channel transistor has a P region in the channel region for controlling the threshold voltage. A buried channel type transistor in which a type impurity is introduced at a low concentration has been used. However, as miniaturization progresses and the gate length becomes shorter, in the case of a buried channel type transistor, problems such as a decrease in threshold voltage due to a short channel effect and a decrease in withstand voltage between source and drain have come to occur. .

In order to solve this problem, therefore, a surface channel type transistor which does not introduce impurities into the channel region has been adopted in place of the buried channel type transistor. By the way, in order to control the threshold voltage of the P-type surface channel transistor, it is necessary to change the conductivity type of the gate electrode from the conventional N-type to the P-type in view of the work function.

On the other hand, in order to reduce the resistance of the gate electrode,
A laminated film of a polycrystalline silicon layer and a metal silicide layer is widely used for the gate electrode.

As described above, the common gate electrode of the complementary MOS transistor has a laminated film of a polycrystalline silicon layer having two conductivity type regions of P type and N type and a silicide layer,
That is, a dual polycide gate structure is used.

[0007]

However, the impurity diffusion coefficient in silicide is 20 to 20 compared with that in polycrystalline silicon.
Since it is as large as about 50 times, the impurity in the polycrystalline silicon layer 6 diffuses through the silicide layer 7 and the impurity concentration in the polycrystalline silicon layer 6 decreases. When the impurity concentration at the interface between the silicide layer 7 and the polycrystalline silicon layer 6 decreases, the contact resistance between the silicide layer 7 and the polycrystalline silicon layer 6 increases, which causes an increase in resistance parasitic on the gate electrode. When the impurity concentration in the polycrystalline silicon layer 6 is lowered, the Fermi level is changed and the threshold voltage is changed.

As a means for preventing such diffusion of impurities, as shown in FIG. 12, P / of the polycrystalline silicon layer 6 is used.
There is a structure in which the silicide layer 7 is separated at the upper portion of the N junction portion, but when the silicide layer 7 is separated, a gate current will flow through the P / N junction of the polycrystalline silicon layer 6, thereby increasing resistance and increasing the internal potential difference. Will cause a voltage drop due to.

An object of the present invention is to eliminate these drawbacks. The gate electrode is made of a laminated film of a silicon layer and a silicide layer, and the silicon layer forming the gate electrode of the P-channel transistor contains P-type impurities. N is introduced into the silicon layer that is introduced and forms the gate electrode of the N-channel transistor.
In a complementary MOS transistor having a type impurity introduced thereinto, mutual diffusion of P-type and N-type impurities introduced into a silicon layer is prevented, and a current is prevented from flowing to a P / N junction portion of the silicon layer. And an increase in the parasitic resistance of the gate electrode and a voltage drop due to an internal potential difference are prevented, and the variation of the threshold voltage is improved to be small.
It is to provide an OS transistor and a manufacturing method thereof.

[0010]

Of the above objects, the first
The purpose (complementary MOS transistor) is to have field effect transistors having different conductivity type channels (3, 4) on the single semiconductor substrate (1) and having different conductivity type channels in each region. In the complementary MOS transistor having, the gate electrode (9) is made of a laminated film of a silicon layer (6) and a silicide layer (7), and a P-type impurity is contained in the silicon layer (6) in the P-channel transistor formation region. The N-type impurity is introduced into the silicon layer (6) in the N-channel transistor formation region, and the silicide layer (7) corresponds to the P-type impurity introduction region of the silicon layer (6). The opening (8) is formed by removing the upper portion of the P / N junction with the N-type impurity introduction region,
The opening (8) of the silicide layer (7) is formed on the entire surface.
An insulating film (12) having an opening (13) formed thereon,
This is achieved by a complementary MOS transistor having a metal electrode (14) in this opening (13).

The silicide layer (7) in the P-channel transistor forming region is covered with a second silicon layer (15) into which a P-type impurity is introduced, and the silicide layer (7) in the N-channel transistor forming region is formed. ) May be covered with a second silicon layer (15) doped with N-type impurities.

Of the above objects, the second object (complementary M
A method of manufacturing an OS transistor) is such that an N-type well (3) and a P-type well (4) are adjacent to each other on a semiconductor substrate (1).
Are formed, a gate insulating film (5) is formed, a silicon layer (6) is formed, and then P is formed on the N-type well (3).
Type impurities are introduced, N type impurities are introduced on the P type well (4) to form a silicide layer (7), and the P type impurity introduced silicon layer (6) and the above The silicide layer (7) is removed from the vicinity of the junction with the silicon layer (6) introduced with the N-type impurity to form an opening (8), and the N-type well (3) and the P-type well ( The above-mentioned N-type well is formed by removing the silicide layer (7), the silicon layer (6) and the gate insulating film (5) while leaving the strip-shaped region connecting with (4). A P-type impurity is introduced into (3) to form a source / drain (10) of a P-channel transistor, and an N-type is formed in the P-type well (4).
Source of N-channel transistor
A drain (11) is formed and an interlayer insulating film (12) is formed on the entire surface.
And forming the opening (13) by removing the interlayer insulating film (12) from above the opening (8) and forming a gate electrode (14) in the opening (13). This is achieved by the method of manufacturing a complementary MOS transistor.

After forming the opening (8), a second silicon layer (15) is formed, P-type impurities are introduced into the N-type well (3), and the P-type impurity is introduced. A step of introducing an N-type impurity may be added to the well (4).

[0014]

Since the silicide layer 7 is separated at the upper portion of the P / N junction between the silicon layer 6 into which the P-type impurity is introduced and the silicon layer 6 into which the N-type impurity is introduced, the silicide layer 7 is introduced into the silicon layer 6. The P-type and N-type impurities are prevented from diffusing each other through the silicide layer 7 to reduce the impurity concentration in the silicon layer 6. In addition, P of the silicon layer 6
Since the silicide layers 7 separated in the upper part of the / N junction are connected to each other via the metal electrode 14, the gate current flows through the electrode 14 and the P / N junction of the silicon layer 6 is formed. Flow through is suppressed. As a result, it is possible to prevent an increase in the parasitic resistance of the gate electrode and a voltage drop due to the internal potential difference, and it is possible to reduce the fluctuation of the threshold voltage.

When the silicide layer 7 is covered with the second silicon layer 15, it is effective in preventing the separation of the silicide layer 7, and the contact resistance between the metal electrode and the silicon layer is the contact resistance between the metal electrode and the silicide layer. Is smaller than
It is effective in reducing the gate resistance.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a complementary MOS transistor according to five embodiments of the present invention will be described below with reference to the drawings.

First Example Refer to FIG. 2. A field insulating film 2 is formed in a region of a P-type silicon substrate 1 excluding regions where P-channel transistors and N-channel transistors are formed, and the P-type silicon substrate 1 in the P-channel transistor formation region is formed. By introducing N-type impurities such as phosphorus, N
A type well 3 is formed, and a P type impurity such as boron is introduced into the P type silicon substrate 1 in the N channel transistor forming region to form a P type well 4.

Referring to FIG. 3, after the entire surface is oxidized to form the gate insulating film 5, the amorphous silicon layer 6 is formed by the CVD method, and the amorphous silicon layer 6 in the P channel transistor forming region is formed.
Is selectively ion-implanted with P-type impurities such as boron, and N-type impurities such as phosphorus are selectively ion-implanted into the amorphous silicon layer 6 in the N-channel transistor formation region. Then, the tungsten silicide layer 7 is formed on the amorphous silicon layer 6 by using the CVD method.

See FIG. 4. An amorphous silicon layer 6 into which P-type impurities are introduced and N
P with the amorphous silicon layer 6 into which the type impurities are introduced
The opening 8 is formed by removing the tungsten silicide layer 7 from the upper portion of the / N junction.

Referring to FIG. 5, the tungsten silicide layer 7, the amorphous silicon layer 6 and the gate insulating film 5 are sequentially patterned to form a gate electrode 9 made of tungsten polycide as shown in the plan view of FIG. The P-type silicon substrate in the region excluding the gate electrode formation region is exposed. Then P
P-type impurities such as boron are selectively ion-implanted into the N-type well 3 in the channel transistor formation region with the gate electrode 9 interposed therebetween to form P-type source / drain 10. N-type impurities such as phosphorus are selectively ion-implanted with the gate electrode 9 sandwiched between
The mold source / drain 11 is formed.

Referring to FIG. 1, an interlayer insulating film 12 is formed on the entire surface, the interlayer insulating film 12 is removed from above the opening 8 of the tungsten silicide layer 7, an opening 13 is formed in the interlayer insulating film 12, and the opening 13 is filled. Then, an aluminum film is formed on the entire surface, and this is patterned to form an electrode 14 in the opening 13.

A polycrystalline silicon layer may be formed instead of the amorphous silicon layer 6.

Second Example See FIG. 6 After performing the same steps as those shown in FIGS. 2, 3, and 4 carried out in the first example, the opening 8 is formed by using the CVD method.
A second amorphous silicon layer 15 is formed on the tungsten silicide layer 7 by filling the inside thereof, a P-type impurity such as boron is added to the second amorphous silicon layer 15 on the P-channel transistor formation region, and an N-channel transistor is formed. N-type impurities such as phosphorus are selectively ion-implanted into the second amorphous silicon layer 15 on the formation region. According to the first example, the second amorphous silicon layer 1
5, the tungsten silicide layer 7, the amorphous silicon layer 6, and the gate insulating film 5 are sequentially patterned to form a gate electrode made of tungsten polycide, and the P-type silicon substrate in the region excluding the gate electrode formation region is exposed.

7A and 7B, after forming the source / drain in the same manner as in the first example, the interlayer insulating film 12 is formed, and the second amorphous silicon layer 15 into which the P-type impurity is introduced and the N-type impurity are formed. An opening is formed in the upper part of the P / N junction with the introduced second amorphous silicon layer 15, and the aluminum electrode 14 is formed in this opening.

Third Example See FIG. 8 Prior to the step of forming the second amorphous silicon layer 15 in the second example, P / A of the amorphous silicon layer 6 was used.
Tungsten silicide layer 7 formed on the N-junction
The side wall 16 made of silicon dioxide is formed on the side wall of the opening 8 and the other steps are the same as those in the second example.

Fourth Example See FIG. 9 In the second example, when the tungsten silicide layer 7 above the P / N junction of the amorphous silicon layer 6 is removed to form the opening 8, the lower amorphous silicon layer 6 is formed.
Is also removed at the same time to form an opening reaching the field insulating film 2, and the other steps are the same as in the second example.

Fifth Example See FIG. 10 In the fourth example, prior to forming the second amorphous silicon layer 15, the side walls of the openings formed in the tungsten silicide layer 7 and the amorphous silicon layer 6 are made of silicon dioxide. The sidewall 16 is formed, and the other steps are the same as in the fourth example.

[0028]

As described above, in the complementary MOS transistor according to the present invention, the laminated film of the silicon layer and the silicide layer is used for the gate electrode, and the P-type impurity is added to the silicon layer in the P-channel transistor formation region. And an N-type impurity is introduced into the silicon layer in the N-channel transistor formation region, the silicide layer is separated above the P / N junction of the silicon layer, and an electrode is formed in this separated region. Therefore, the impurities introduced into the silicon layer are prevented from mutually diffusing through the silicide layer, and the gate current is suppressed from flowing through the P / N junction portion of the silicon layer. As a result, an increase in parasitic resistance of the gate electrode and a voltage drop due to an internal potential difference are prevented, and fluctuations in the threshold voltage are also reduced to form a high quality complementary MOS transistor.

[Brief description of drawings]

FIG. 1 is a sectional view of a complementary MOS transistor according to a first embodiment of the present invention.

FIG. 2 is a process drawing of the complementary MOS transistor according to the first embodiment of the present invention.

FIG. 3 is a process drawing of the complementary MOS transistor according to the first embodiment of the present invention.

FIG. 4 is a process drawing of the complementary MOS transistor according to the first embodiment of the present invention.

FIG. 5 is a process drawing of the complementary MOS transistor according to the first embodiment of the present invention.

FIG. 6 is a process drawing of a complementary MOS transistor according to a second embodiment of the present invention.

FIG. 7 is a sectional view of a complementary MOS transistor according to a second embodiment of the present invention.

FIG. 8 is a sectional view of a complementary MOS transistor according to a third embodiment of the present invention.

FIG. 9 is a sectional view of a complementary MOS transistor according to a fourth embodiment of the present invention.

FIG. 10 is a sectional view of a complementary MOS transistor according to a fifth embodiment of the present invention.

FIG. 11 is a cross-sectional view of a complementary MOS transistor according to a conventional technique.

FIG. 12 is a cross-sectional view of a complementary MOS transistor according to a conventional technique.

[Explanation of symbols]

 1 silicon substrate 2 field insulating film 3 N well 4 P well 5 gate insulating film 6 silicon layer 7 silicide layer 8 opening 9 gate electrode 10 P-type source / drain 11 N-type source / drain 12 insulating film 13 opening 14 electrode 15 second Silicon layer 16 Sidewall

Claims (4)

[Claims] 1. A complementary MOS transistor having different conductivity type regions (3, 4) on a single semiconductor substrate (1), and field effect transistors having different conductivity type channels in each region. In, the gate electrode (9) is composed of a laminated film of a silicon layer (6) and a silicide layer (7), P-type impurities are introduced into the silicon layer (6) in the P-channel transistor forming region, and an N-channel transistor is formed. An N-type impurity is introduced into the silicon layer (6) in the formation region, and the silicide layer (7) is formed of P of the silicon layer (6).
An opening (8) is formed by removing the P / N junction between the N-type impurity introduction region and the N-type impurity introduction region, and an opening is formed on the entire surface over the opening (8) of the silicide layer (7). A complementary MOS transistor characterized in that an insulating film (12) having (13) is formed and a metal electrode (14) is formed so as to fill the opening (13). 2. The complementary MOS transistor according to claim 1, wherein the silicide layer (7) in the P channel transistor formation region is a second silicon layer (1) into which a P type impurity is introduced.
5) The complementary MOS transistor characterized in that the silicide layer (7) in the N channel transistor forming region is covered with a second silicon layer (15) into which an N type impurity is introduced. 3. An N-type well (3) and a P-type well (4) are formed adjacent to each other on a semiconductor substrate (1), a gate insulating film (5) is formed, and a silicon layer (6) is formed. And then forming the N-type well (3)
A P-type impurity is introduced above, an N-type impurity is introduced onto the P-type well (4), a silicide layer (7) is formed, and a silicon layer (6) into which the P-type impurity is introduced is formed. The N
The silicide layer (7) is removed from the vicinity of the junction with the silicon layer (6) introduced with the type impurities to form an opening (8), and the N-type well (3) and the P-type well (4) are formed. The N-type well (3) is formed by removing the silicide layer (7), the silicon layer (6), and the gate insulating film (5) while leaving a strip-shaped region connecting the two. By introducing P-type impurities into the source / drain (10) of the P-channel transistor,
An N-type impurity is introduced into the P-type well (4) to form a source / drain (11) of the N-channel transistor, an interlayer insulating film (12) is formed on the entire surface, and the interlayer insulating film (12) is formed over the opening (8). A method of manufacturing a complementary MOS transistor, comprising the steps of removing an insulating film (12) to form an opening (13) and forming a gate electrode (14) in the opening (13). 4. After forming the opening (8), a second silicon layer (15) is formed, P-type impurities are introduced on the N-type well (3), and the P-type well (4) is formed. 4. A method of manufacturing a complementary MOS transistor according to claim 3, further comprising the step of introducing an N-type impurity on the above.