JPH0782487B2 - Moving least squares function regression device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to an apparatus for analyzing various time-series signals including abnormal signal values, in a signal of an analysis section having a constant time width with respect to a certain time of the time-series signal. In order to calculate the moving least squares function regression using the value, the multiplication result of the signal indicating whether or not the analysis is permitted and each signal such as the time signal, the time series signal, etc. is integrated and each time is calculated. Are stored in a pair of memories, the first and second memories are read with the time data of the start point and the end point representing the analysis section from the analysis section calculation circuit as addresses, and the first and second memory outputs The regression result is obtained in real time by obtaining the difference in the data of and calculating the difference.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moving least square function regression device in a device that analyzes various time series signals.

An ultrasonic diagnostic apparatus is an example of a time series signal analysis apparatus. The ultrasonic diagnostic apparatus transmits an ultrasonic pulse to a heterogeneous medium such as a living body, receives a reflected wave (echo), analyzes the received signal, measures the acoustic characteristic value of the medium, and visualizes it.

As one of such devices, there is an invention previously filed by the present applicant under the name of "ultrasonic medium characteristic value measuring device" (Japanese Patent Application No. 61-252887).

The specification of this earlier application describes a method of processing the induction amount obtained from the echo signal to obtain the attenuation coefficient gradient β and measuring the acoustic characteristic value of the medium, in which case a specific n-th order function is used. Calculations are performed in which f (t) is regressed on the induction amount using the least squares method with w (t) as a weight of the squared error within a time window of width T to obtain the coefficient of the function f (t).

The present invention relates to a moving least square function regression device useful in such a time series signal measuring device.

[Prior Art] As an apparatus for analyzing various time-series signals, when unnecessary noise is included in a signal to be analyzed, it is desired to perform analysis without using the data of the time when the noise is included. The demand is increasing.

As a response to this request, a binary analysis permission signal (weighting function) is taken as an original time when a time including noise takes a value of 0 and a time not including noise takes a value of 1. There is a method of obtaining the analysis result that is not affected by noise from the analysis permission signal and the original time-series signal, by obtaining from the series signal by preprocessing.

In that case, if the analysis permission signal is 0 and the signal is not used, and the analysis is performed with a fixed analysis interval length, the number of valid data is insufficient and the regression output with sufficient accuracy cannot be obtained. .

Therefore, without using the signal at the time when the analysis permission signal is 0, and so that the number of data used for regression is constant,
Regression has come to be performed by making the analysis interval length variable.

The calculation will be described with reference to FIG. 4. Only the value of the time-series signal y (t) in (a) during the period in which the analysis permission signal (weighting function) w (t) in (b) is 1 is to be calculated. To
An intermittent signal like the waveform in (c) is created.

Then, for each time t, the average value of the section before and after T / 2 hours is obtained, but for that purpose, the period in which the analysis permission signal is 0 cannot be included in the time of T / 2.
This is because if the period is included, the number of data varies and the calculation result varies unnaturally greatly depending on the time position.

As a result, when performing the calculation within the time window T for the time t, the time t ₁ before T / 2 hours is the starting point of the calculation, and in the signal waveform between T / 2 hours later, t / 4 hours after t ( the t ₃₎ becomes the value of 0, then signal rises time (t ₄₎ further T / 4 from
The number of data becomes constant by calculating the signal data up to t ₂ after time.

There is no known known conventional example of a dedicated calculation device for calculating the moving least squares function regression of a time series signal using such an analysis permission signal (weighting function), and the time of the start point and the end point of the analysis section is known. Third as a conventional example of a structure for obtaining data
The configurations shown in FIG. 3A and FIG. 3B can be considered.

In FIGS. 3 (a) and 3 (b), 30 is a counting circuit, 31 is a memory, and 32 is an MPU (microprocessor unit). First, the counting circuit 30 shown in FIG. 3 (a) counts the clock signal CLK, and provides the address input of the memory 31 with the data corresponding to each time as its output. Therefore, the state of 1,0 at each time point of the analysis permission signal shown in FIG. 3B is sequentially stored in the memory 31 at each address (time position).

Next, as shown in FIG. 3B, the start time t ₁ and the end time t ₂ of the analysis section corresponding to the output time t are obtained using the MPU 32. In that case, the analysis permission signal is examined from the time t toward the positive time direction and the negative time direction, and the time when the sum of the times when the value of the analysis permission signal is 1 is T / 2 is searched for. Then, the moving least square function regression for the above time series signal is calculated.

[Problems to be solved by the invention]

As described above, the conventional method requires at least 2T times of memory access and addition processing to determine the analysis interval for each output time. Therefore, if the data length is N, at least 2N × T times of memory are required. Access and addition are required. Furthermore, after the analysis interval is calculated, the moving least square function regression is performed on the time-series signal when the analysis permission signal is 1, but the time required for these processes is great and real-time processing is difficult. There was a problem.

[Means for solving problems]

The present invention, in order to perform a moving least squares function regression calculation of a time series signal including an abnormal signal value, a weighting function signal indicating whether or not analysis is permitted, and each signal such as a time signal or a time series signal. A first point representing an analysis section from a separately provided analysis section calculation circuit is provided for each output by providing a first memory and a second memory for integrating each of a plurality of multiplication results with and storing each output at each time. And the end point time data are used as addresses to read the first and second memories, find the difference between the data output from the first and second memories, and perform an operation on the result to perform regression in real time. The result is obtained.

The basic configuration of the present invention is shown in FIG. 1 (a), and the basic configuration of the analysis section calculation circuit therein is shown in FIG. 1 (c), and FIG. 1 (a) and FIG. An operation explanatory view is shown in FIG. 1 (b) and FIG. 1 (d).

In FIG. 1 (a), 100 is an analysis interval calculation circuit, and 110.
.... 140 is a multiplication / integration circuit for multiplying two input signals and integrating each, and 111, 112 ... 141, 142 are circuits 110 to 1 respectively
Represents a pair of memories 4 to 11 storing 40 outputs, 113
... 143 is an adder circuit for obtaining the difference between the memory outputs of each pair, and 150 is an arithmetic circuit for performing an operation on the outputs x1 to x4 of each adder circuit to obtain a regression result.

Further, in FIG. 1 (c), 10 is a counting circuit for receiving and counting a clock signal only when the value of the binary weighting function signal (analysis permission signal) w (t) is 1, and 11 to 13 are memories 1 ~
Memories 3 and 14 are counting circuits for counting clock signals, 15 is a code conversion circuit, 16 and 17 are addition circuits, and 18 to 21 are switching circuits.

[Operation] In FIG. 1 (a), the memories 4 and 5 use the weighting function signal w.
The integrated value of the result of multiplying (t) by the time signal t is a switching circuit.
With the time signal t as an address, the write control signal is applied to the terminal W / R and the same contents are written and stored in the state where 101 and 102 are in the positions shown.

Similarly, the memories 6 and 7 store the integrated value of the multiplication result of the weighting function signal w (t) and the square of the time signal t, and the memories 8 and 9 store the weighting function signal w (t) and the time series signal y (t. ) And t, and stores the integrated value of the result, and the memories 10 and 11 store the integrated value of the result of multiplying the weighting function signal w (t) and the time-series signal y (t) in the memories 4 and 5. Write to the same address as and memorize.

This operation will be described using a typical example shown in FIG. 1 (b). The time series signal y (t) in (a) and the weighting function signal w (t) in (b) are input to the circuit 140. Then, both signals are multiplied to obtain (C). This integrated output is written into the memories 10 and 11 at each time using the time signal t as an address and stored as shown in (d).

In FIG. 1 (a), after this storing operation, the switching circuit 10
1 and 102 are set at positions opposite to the positions shown in the drawings, and the time signal t ₁ and t ₂ at the start point and the end point representing the analysis section of the time width T for each time t are stored in the memories 5, 7, 9, 11 and memories 4, 6, 8 and 10 are simultaneously supplied, the integrated values from time 0 to t ₁ and the integrated values from time 0 to t ₂ are read out and output from the respective memory groups.

The read state in the memories 10 and 11 is shown in FIG. 1 (b).
(D), the respective read data a and b are output.

These outputs are added to the adder circuit 113 ...
When subtraction-143, the sum of the integral value of the respective time within the width T of the analysis zones from these circuits (from t ₁ to t ₂₎ x1 to x4 are obtained.

Of these, x4 is the section as shown in (e) of Fig. 1 (b).
The difference between the integrated values from t ₁ to t ₂ is represented, and the value corresponds to the sum of the shaded portions A to C of the waveform (e).

The outputs x1 to x4 are input to the arithmetic circuit 150, and calculation is performed by a calculation logic circuit preset therein to obtain the result of regression calculation.

Next, the operation of the analysis section calculation circuit shown in FIG. 1 (c) will be described with reference to FIG. 1 (d).

First, the time-related data storage operation will be described by setting the switching circuits 18 to 21 in the illustrated state.

When the weighting function signal w (t) is input to the counting circuit 10, the counting circuit 10 receives the signal of the waveform shown in FIG. 1 (d) at the ENABLE terminal and counts (integrates) the clock signal only when the value is 1.
Then, the counting circuit 14 sequentially counts the clock signals and generates t as its output.

The memories 1 to 3 are written (W) driven by a control signal at each clock, the memory 1 writes the output (time integrated value) data of the counting circuit 10 using the output of the counting circuit 14 as an address, and the memories 2 and 3 are Writing is sequentially performed with the output of the counting circuit 14 as data and the output of the counting circuit 10 as an address, and the situation is as shown in FIG. 1 (d).

Next, the operation of generating the analysis interval signals t ₁ and t ₂ of the time width T with respect to the time t will be described. The switching circuits 18 to 21 are set to positions opposite to the illustrated state, and the switching circuit 18 to T / 2 is set. The data corresponding to the time is input, and the memories 1 to 3 are read (R) driven for each clock signal.

As a result, the weighting function signal w (t) from the memory 1 is 1
The time integral value for each time t is read out,
The adder circuit 17 adds T / 2 to that value, and the adder circuit 16 subtracts T / 2 from that value (since it is negatively encoded by the code conversion circuit 15) and supplies it to the memories 3 and 2 as an address, respectively. Read out. As a result, the memory 2 outputs the time t ₁ representing the start point of the analysis section, and the memory 3 outputs the time t ₂ representing the start point.

This state is shown in FIG. 1 (d), and the weighting function signal w
It can be seen that the time when (t) is 0 is not included in the clock calculation of the analysis section, and the number of data is constant and the analysis section length is variable.

[Embodiment] FIG. 2 shows the configuration of an embodiment of the present invention.

In the figure, 20a to 20d are multiplication circuits, 21a to 21d are integration circuits, 22a to 22d are registers, and 23a to 23d are memories 4, 6, 8, and 10,
24a to 24d are memories 5, 7, 9, 11, 25a to 25d are adder circuits, 25,
26 is a counting circuit, 27 to 29 are memories 1 to 3, 3 is a code conversion circuit, 41 is a timing control circuit, 43, 44, 53 and 54 are addition circuits, 45 to 49 are switching circuits, and 50 and 52 are squares. A circuit, 51 is a multiplication circuit, and 55 is a division circuit.

In the configuration of FIG. 2, the multiplication circuit 20a, the integration circuit 21a and the register 22a correspond to the multiplication / integration circuit 110 of FIG. 1 (a), and the memories 4 and 5 of 23a and 24a are shown in FIG. 1 (a). The same applies to the other multiplication / integration circuits and memories corresponding to the memories 4 and 5 of 111 and 112, and 52 to 55 in FIG. 2 correspond to the arithmetic circuit 150 in FIG.

The multiplication / integration operation in the multiplication circuit 20, the integration circuit 21, and the register 22, the writing to the memories 23 and 24, and the read operation by the address from the analysis section calculation circuit are performed as described with reference to FIG. As I did.

The counting circuits 25 and 26 and memories 1 to 3 in FIG. 2 correspond to the counting circuits 14 and 10 and memories 1 to 3 in FIG. 1C, and the calculation output operation of the analysis section is also shown in FIG. The same operation is performed according to the principle described for c).

The moving least squares calculation of the present invention uses the time width T before and after the time t.
In the section of, the specific function f (t) is set to the time series signal y.
It is to meet (t). That is, the weighting function w
(T) and the time-series signal y (t) are input, and the specific function f (t) = a _n t ⁿ + a _n-1 t ^n-1 + ... + a ₁ t + a ₀ coefficients a _n , a
Outputs _n-1 , ..., a ₁ , a ₀ .

Considering the case where the specific function is a linear function for simplification, it is f (t) = a ₁ t + a ₀ , and it is clear from the formula that the coefficients a ₁ and a ₀ when regressing this are as follows. Is.

The regression calculation shown in FIG. 2 is for obtaining the above a ₁ . That is, from the adder circuit 25a to TΣw (t) t from the adder circuit 25b to TΣw (t) t _{2 from the} adder circuit 25c to TΣw (t) y (t) t from the adder circuit 25d to TΣw (t) y (t) , The above-mentioned coefficient a ₁ is output from the division circuit 55 at the final stage by performing the respective calculations in the respective arithmetic circuits shown by 52 to 55 in FIG. 2, and the value corresponds to each time. And then sequentially obtained in real time.

With respect to the coefficient a, the regression calculation can be performed with the same configuration by giving an input corresponding to the above equation.

The regression calculation can be easily performed by switching the switching circuits 45 to 49 so that analyzable data (data when the weighting function signal is 1) is read so as to occur at consecutive times.

This regression calculation has the same configuration and has an arbitrary n-th order function (n ≧
The coefficient of 1) can be calculated, and in that case, it can be obtained by applying it to the multiplying circuits 20a ... In accordance with the equations of the respective coefficients and performing the corresponding operation in the arithmetic circuit with the output of each adder circuit 25a. Needless to say.

EFFECTS OF THE INVENTION According to the present invention, it is possible to perform a moving least squares function regression calculation in which the analysis interval length is variable in substantially real time.

[Brief description of drawings]

FIG. 1 (a) and FIG. 1 (c) are principle configuration diagrams of the present invention,
FIG. 1 (b) and FIG. 1 (d) are respectively FIG. 1 (a) and FIG.
2 (c) is an operation explanatory diagram, FIG. 2 is a configuration diagram of an embodiment of the present invention, FIG. 3 is a configuration diagram of a conventional example, and FIG. 4 is an explanatory diagram of a calculation principle of a time series signal. 1 (a) and 1 (c) 100: Analysis section calculation path 110-140: Multiplication / integration circuit 111-142: Memory 4-11 113-143: Adder circuit 150: Arithmetic circuit 10: Counting circuit 11 to 13: Memory 1 to memory 3 14: Clock signal counting circuit 15: Code conversion circuit 16, 17: Addition circuit 18 to 21: Switching circuit

Claims (1)

[Claims] 1. A time-series signal (y (t)) including a time section in which analysis is prohibited is used in an arbitrary order by using signal function values in a predetermined time section (T) before and after each analysis target time. In a device that regresses to a time function by the method of least squares, a binary analysis permission signal (w (t)) obtained from the time series signal (y (t)) and a time signal from a time counting means (14) (T) or a plurality of means (110 to 140) for multiplying and integrating the signal (t ² , y (t) · t) related to the time-series signal (y (t)), and the multiplication / integration described above. A plurality of first memories (111 to 14) each storing the output data of the means using the time signal as an address.
1) and a second memory (112 to 142), means (100) for calculating time data of the start point and the end point of the analysis section corresponding to each time, and the first and second memories (112 to 142). ) Is read as the address of the start point and end point time data of the analysis section calculation means (100), and the difference between the outputs of the first and second memories (112 to 142) is input to perform mutual calculation. A moving least squares function regression device comprising a circuit (150).