JPH0782069B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit.

[Conventional technology]

The conventional semiconductor integrated circuit does not have a circuit for detecting whether or not the output terminal is grounded.

[Problems to be solved by the invention]

It is difficult to find out the cause of the above-described conventional semiconductor integrated circuit, even if it malfunctions after being incorporated in a device such as a computer. In particular, since the output terminal is grounded due to erroneous wiring on the side of a device such as a computer, it is difficult to determine the grounding state of the output terminal even if a malfunction occurs.

An object of the present invention is to provide a semiconductor integrated circuit which can easily detect whether or not an output terminal is grounded and can easily determine the cause of the malfunction when the output terminal is grounded and malfunctions due to incorrect wiring. To do.

[Means for solving problems]

A semiconductor integrated circuit of the present invention includes a first current switching type output circuit which inputs an input signal from an internal circuit and a reference voltage and outputs the reference voltage, and a second current switching type output circuit which inputs the input signal and the signal of the output terminal. It is configured to include a current switching type output circuit and a flip-flop that receives an output signal of the second current switching type output circuit.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the present invention. A logic signal generated from the internal circuit of the semiconductor integrated circuit enters the input 1 of the output block A ₁ on the same semiconductor integrated circuit. The input 1 enters the base of the transistor Q ₁ and becomes the input of the first emitter follower circuit composed of the resistor R ₁ . Output 2 of this emitter follower circuit is in the bases of transistors Q ₂ and Q ₅ . Transistor Q ₂ has a reference voltage at its base
The transistor Q ₃ to which V _R is applied, the resistor R _2, and the constant current source C ₁ constitute a first current switching (hereinafter referred to as CML) output circuit. The connection point between the resistor R ₂ and the collector of the transistor Q ₃ is the output of this CML output circuit, and the output terminal 3
Then, it becomes an external signal of the semiconductor integrated circuit. The output terminal 3 is connected to the base of the transistor Q _4, the input of the second emitter full Oro word circuit configured with transistors Q ₄ a resistor R ₃ and R _4. Also, the connection point 5 between the resistors R ₃ and R ₄ is the output of this second emitter follower circuit, and is connected to the base of the transistor Q ₆ . Further, here, the transistor Q ₆ is the second CML together with the transistor Q ₅ and the constant current source C ₂ .
It constitutes a detection circuit. It is the output of this CML detection circuit. Block A ₁ ... A _n and the resistor R ₅ collector along with other of the plurality of output blocks of the transistor Q _6, the diode D ₁
Are commonly connected at the connection point 6. Furthermore, this connection point 6
Enters the inverter G ₁ , becomes the inverted logic output 7, and enters the flip-flop B ₁ . The flip-flop B ₁ here is a flip-flop having a reset and a set input, the terminal 8 is a reset terminal, and the inverted logic output 7 is a set input. Further, the output of the flip-flop B ₁ is connected to the terminal 9.

As a result, the internal logic signal of the semiconductor integrated circuit appears at the output terminal 3 through the first emitter follower circuit in the output block and further through the CML output circuit. On the other hand, the signal of the output terminal 3 passes through the second emitter follower circuit, and together with the output signal of the first emitter follower circuit, a CML detection circuit which is a circuit for detecting grounding or non-grounding of the output terminal 3. to go into. Further, this CLM detection circuit is commonly connected with other output blocks and becomes an input of the flip-flop circuit through the inbeta. Therefore, the ground detection result of the output terminal can be indicated by the logic state of the flip-flop. Next, the operation of the semiconductor integrated circuit shown in FIG. 1 will be described with reference to FIGS. 2 and 3.

FIG. 2 is a waveform diagram showing the operation when the output terminal 3 is not grounded, that is, in the normal use state. When a signal having a high level (hereinafter, referred to as H level) of O ^V and a low level (hereinafter, referred to as L level) of V _l is input to the input terminal 1, the terminal 2 is a transistor with respect to the level of the terminal 1. Q ₁ Base-emitter forward voltage V _Fl H level lowered by V _Fl
In- phase signals with _Fl and L levels of V _Fl + V _l appear. In addition, the CML output circuit that receives the signal from terminal 2 is a transistor Q.
_The reference voltage V _R entering the base of ₃ is almost Since it is set to, an output signal of the same phase as the terminal 2 whose H level is O ^V and L level is V ₂ is generated at the output terminal 3. Furthermore, the signal output terminal 3 and the second emitter full Oro word circuit output 5 an emitter current I ₄ and the resistance R ₃ of the base and the emitter forward voltage of the transistor Q ₄ to the output terminal 3 V _F4 and the transistor Q ₄ An in-phase signal is generated in which the H level is V _F4 + I ₃ × R ₃ and the L level is V _F4 + I ₃ × R ₃ + V ₂ . Where V ₁ = V ₂ , V _F1 = V _F4 , Then, the input of the terminal 2 entering the CML detection circuit is always higher than the input of the terminal 5 by V _1/2 . Therefore, the current I ₂ of the constant current source C ₂ flows through the transistor Q ₅ . If the output terminals of all output blocks L ₁ ... A _m from the it is not grounded, O ^V next to the common ground point 6 always H level, the output 7 of the inverter G _l also becomes L level. Therefore, the flip-flop _Bl is in a reset state at the terminal 8 as shown in FIG. 2, and the output 9 thereof always holds the H level, indicating that the output terminal is not grounded.

Next, the operation when the output terminal 3 is grounded to the ground level will be described with reference to FIG. The operations of the input terminals 1 and 2 are the same as those in FIG. However, when the output terminal 3 is grounded to the ground level due to an external factor, the output terminal 3 is always fixed to the H level O ^V. Therefore, the output 5 of the second emitter follower circuit always remains fixed at the level of V _F4 + I ₃ × R ₃ . As described in FIG. 2, the forward voltages V _F1 and V _F4 between the emitters and the bases of the transistors Q ₁ and Q ₄ are equal, and the level of I ₃ × R ₃ is
Assuming V _1/2, the current I ₂ of the CML detection circuit flows through the transistor Q ₅ when the terminal 2 is at the H level because the level of the terminal 2 is higher than that of the terminal _5, and conversely when the terminal 2 is at the L level. 5
Flows through transistor Q ₆ due to its high level. Therefore, at the common connection point 6, when the terminal 2 is at the L level, a level that is made up of the current I ₂ and the resistance R ₅ is generated. Further, the signal at the connection point 6 becomes an inverted signal at the terminal 7 by the inverter G ₁ . Assuming that the flip-flop B ₁ is previously reset by the reset terminal 8 as described in the explanation of FIG. 2, the output signal 9 of the flip-flop changes from H level in the reset state to L in the set state by the terminal 7. It will change to a level.

Further, as can be seen from FIG. 1, since the outputs of the CML detection circuits of A ₁ ... A _n of a plurality of output blocks are commonly connected to the common connection point 6, it is possible to select one or more of each output block. When the output terminal is installed, that state is detected and the output 9 of the flip-flop is set to L level to indicate the grounding result.

〔The invention's effect〕

As described above, the present invention is provided with the first current switching type output circuit which inputs the input signal and outputs it to the output terminal and the second current switching type output circuit which inputs the input signal and the signal of the output terminal. As a result, it is possible to detect that the output terminal is grounded and take out the detection result as an external signal.

Therefore, when the device incorporating the semiconductor integrated circuit malfunctions, it can be easily determined whether or not the cause is that the output terminal of the semiconductor integrated circuit is in the grounded state due to incorrect wiring or the like.

[Brief description of drawings]

1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of each point of the embodiment shown in FIG. 1 when the output terminal is not grounded, and FIG. FIG. 7 is a waveform diagram showing the operation of each point of the embodiment shown in FIG. 1 in the grounded state. A ₁ …… A _n …… Output block, G _l …… Inverter, B _l …… Set and reset type flip-flop, Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q
₆ …… Transistor, R ₁ , R ₂ , R ₃ , R ₄ , R ₅ …… Resistor, diode …… D ₁ , 1,2,4,5,7 …… Terminal, 3 …… Output terminal, 6…
… Common connection point, 8 …… Reset terminal, 9 …… Flip-flop output terminal, C ₁ , C ₂ …… Constant current source, I ₁ , I ₂ , I ₃ …… Current, V _R …… Reference voltage, V _EE: Power supply voltage.

Claims (2)

[Claims] 1. A first current switching type output circuit for inputting an input signal from an internal circuit and a reference voltage and outputting to an output terminal, and a second current switching type inputting the input signal and a signal of the output terminal. A semiconductor integrated circuit comprising an output circuit and a flip-flop for receiving an output signal of the second current switching type output circuit. 2. A first current switching type output circuit for inputting an input signal and a reference voltage from an internal circuit and outputting to an output terminal, and a second current switching type input circuit for inputting the input signal and the signal of the output terminal. A semiconductor integrated circuit comprising: a plurality of output blocks each having an output circuit; and a flip-flop that receives an output signal of the second current switching output circuit of each of the plurality of output blocks.