JPH0779266A - Clock synchronizing method and its circuit - Google Patents

Abstract

PURPOSE:To suppress the influence of a band limitation that a reception signal receives and to obtain an excellent clock synchronization with high response speed by obtaining the clock synchronization only when the difference of two phases is in a prescribed relation. CONSTITUTION:The output phase difference of a subtracter 13 is delivered to deciding devices 14 and 15 and a comparator 21. When the output of the deciding device 14 becomes a reproduction bit X and becomes a reproduction bit X' by being delayed by one symbol in a delay device 22. In the same way, reproduction bits Y and Y' are obtained from the output of deciding device 15. Each reproduction bit is supplied to a state decision circuit 24, and when a state is the one where the influence by a band limitation on a reception signal is little, the output is delivered to an AND circuit 25. The output of the comparator 21 is delivered to a delay device 26, the comparison result is delayed by a prescribed symbol which is below one-symbol length and the result is delivered to an edge detector 27. An edge detection signal is transmitted to the circuit 25. The output of the delay device 26 is delivered to a symbol counter 17, a count value is corrected according to the signal from the circuit 25 and a clock synchronization is performed.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a π / 4 shift QPSK.
The present invention relates to a clock synchronization method and circuit used in a signal receiving device.

[0002]

2. Description of the Related Art A PHP (Personal Handy Pho) considered as a next-generation cordless telephone.
(ne: Personal Handy Phone) system,
In the receiving device that receives the π / 4 shift QPSK (four-valued phase modulation) signal, the received signal is demodulated and the clock synchronizing circuit having the structure shown in FIG. 5 is used.

In the figure, the received signal is first inputted to the phase detector 11, where the phase component θ in the signal is taken out and sent to the delay device 12 and the subtractor 13. The delay unit 12 delays the input phase component θ by one symbol to form a delayed phase component θd, and sends it to the subtractor 13.

The subtractor 13 subtracts "θ-θd" from the phase component θ directly input from the phase detector 11 and the delayed phase component θd delayed through the delay device 12, and the phase difference Δθ is obtained. Distributes and outputs to the judgment devices 14 and 15.

The discriminator 14 outputs a signal 0 when the phase difference Δθ is 0 (zero) or more, and outputs a signal 1 when the phase difference Δθ is smaller than 0 (negative), and the output of the discriminator 14 is reproduced. It becomes a bit X and is sent to the edge detector 16.

Further, the determiner 15 determines the absolute value of the phase difference Δθ
If Δθ | is larger than π / 2, the signal 1 is output, and if it is within π / 2, the signal 0 is output, and the output of the determiner 15 becomes the reproduction bit Y.

The edge detector 16 detects the edge position when the signal from the determiner 14 changes from 0 to 1 or from 1 to 0, thereby detecting the timing at which the phase difference Δθ crosses 0. The detection signal is sent to the symbol counter 17.

In the symbol counter 17, the edge detector 16
When a detection signal from the counter is received, the clock value is synchronized by correcting the count value (correction of lead / lag) or resetting the predetermined count value. The clock synchronization signal output from the symbol counter 17 is the reproduction bit X. , Y to the processing circuit of the next stage.

In the above structure, the edge detector
16 detects the timing at which the phase difference Δθ crosses 0 as described above, but as the received signal is band limited, it is clear from the eye pattern of the π / 4 shift QPSK signal shown in FIG. The detection timing is ±
It has a temporal spread (error) of about 0.2 symbols. Therefore, in order to obtain good clock synchronization, it is necessary to average this clock synchronization processing for a long time, which causes a problem that the response speed of the receiving circuit cannot be increased.

[0010]

As described above, in the conventional general clock synchronization circuit, the response speed of the reception circuit cannot be increased due to the band limitation of the reception signal. Was there.

The present invention has been made in view of the above circumstances, and an object of the present invention is to suppress the influence of band limitation on a received signal and obtain good clock synchronization at a high response speed. A clock synchronization method and circuit capable of

[0012]

That is, according to the present invention, when the phase difference between the reception signal subjected to band limitation and the reception signal one symbol before the reception signal crosses a predetermined value, the timing is sandwiched. Two phase differences separated by one symbol,
Typically, clock synchronization is achieved only when the phase difference before 1/2 symbol and the phase difference after 1/2 symbol have a predetermined relationship.

[0013]

With the above structure, the influence of band limitation is reduced, and good clock synchronization can be obtained at a high response speed.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A .pi. / 4 shift QPSK signal receiving clock synchronizing circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the circuit configuration thereof, which is basically the same as that shown in FIG. 2 described above. Therefore, the same parts are designated by the same reference numerals and the description thereof will be omitted.

However, the phase difference Δθ output from the subtractor 13
Is output not only to the decision units 14 and 15 but also to the comparator 21.

The output of the decision unit 14 is used as it is as the reproduction bit X, and is delayed by one symbol by the delay unit 22 to be the delayed reproduction bit X '. Similarly, the output of the decision unit 15 is used as it is as the reproduction bit Y, and the delay unit 23 outputs 1
It is delayed by the number of symbols to be a delayed reproduction bit Y '.

The reproduced bit X and the delayed reproduced bit X'are output to the processing circuit (not shown) in the next stage and also input to the state determination circuit 24. Similarly, the reproduced bit Y and the delayed reproduced bit Y ′ are output to the processing circuit of the next stage and also input to the state determination circuit 24.

The state determination circuit 24 is for determining this when a preset state in which the influence of band limitation is considered to be small on the received signal is reached.
The output of 24 is sent to the AND circuit 25.

The comparator 21 has a phase difference Δ from the subtractor 13.
θ is compared with a preset value, and the comparison result is output to the delay device 26. The delay device 26 delays the comparison result of the comparator 21 by a predetermined symbol of one symbol length or less and sends it to the edge detector 27.

The edge detector 27 detects the edge position when the delayed signal level of the comparison result changes from 0 to 1 or from 1 to 0, and sends the detection signal to the AND circuit 25.

The output of the delay device 26 is sent to the symbol counter 17, and the symbol counter 17 corrects or resets the count value in accordance with the signal from the AND circuit 25 to perform clock synchronization. Then, the obtained clock synchronization signal is output to the processing circuit of the next stage.

The π / 4 shift QPSK is a symbol (X,
-3π / 4 shift when Y) is (1,1), (0,1)
Is a 3π / 4 shift, (0,0) is a π / 4 shift, and (1,0) is a −π / 4 shift, and the received signal is as shown in FIG. For example, at a timing when the phase difference Δθ crosses 60 ° or −60 °, the phase difference Δ before and after the 1/2 symbol is Δ.
When the region in which θ is present has the following specific combination, the error due to the effect of band limitation in the received signal is very small (about 0.1 symbol). That is, the phase difference Δ
At the timing when θ crosses 60 °, (X, X ′,
When the combination of (Y, Y ') is (1, 0, 1, 0) or (0, 1, 0, 1), and the phase difference Δθ is -60 °.
(0, 1, 1, 0) (1,
When it is 0, 0, 1), the error due to the influence of the band limitation is very small.

Therefore, for example, if 60 ° is given as the comparison set value of the comparator 21, the decision circuit 24 has exclusive OR circuits 24a and 24b and an exclusive NOR circuit 24c as shown in FIG.
And the AND circuit 24d, and the delay amount of the delay device 26 may be set to 1/2 symbol. Set value of comparator 21 is 60 °
And the phase difference Δθ from the subtracter 13 are compared with each other, and the comparison signal is delayed by 1/2 symbol via the delay device 26 and sent to the edge detector 27.

As a result, at the time when the edge detector 27 detects an edge, the reproduced bits X and Y have a state after ½ symbol of the edge and the delayed reproduced bit X′Y ′ has a state before ½ symbol. The signal of the state determination circuit 24 at that time is "1", that is, the combination of (X, X ', Y, Y') is (1,2) as described above. The gate of the AND circuit 25 is controlled to be in the open state only when it is set to (1, 0, 0) or (0, 0, 1, 1), and its output signal becomes "1", and the symbol counter 17
Are synchronized.

In the above embodiment, the exclusive NOR circuit 24c is provided in the determination circuit 24. However, when viewed from the eye pattern of FIG. 6, the phase difference 40 ° is crossed (X,
Since there is no case where the combination of (X ', Y, Y') becomes (0, 1, 1, 0) or (1, 0, 0, 1), the exclusive NOR circuit 24c can be deleted. is there.

When the exclusive NOR circuit 24c is removed from the judgment circuit 24, that is, the judgment circuit 24 is replaced by the exclusive OR circuit 24.
2a and 24b and an AND circuit 24d, the configuration shown in FIG.
, The phase difference Δθ from the subtractor 13 is set to −6
A comparator 28 for comparing with 0 °, a 1/2 symbol delay device 29 and an edge detector 30 are provided, and the output of this edge detector 30 and the output of the edge detector 27 are connected via an OR circuit 31 to an AND circuit 25. The clock synchronization can be achieved with all of the above four combinations.

In the above-described embodiment, the delay device 26 (29) connected before the edge detector 27 (30) is
Since the timing at which the edge detection signal is output is only delayed by 1/2 symbol, it may be provided before the comparator 21 (28) or after the edge detector 27 (30).
In particular, in the case where the edge detection is performed by the two systems as in the second embodiment, with this configuration, one delay device can be shared by both systems. Figure 3 shows the edge detector 2
A common delay device 33 is provided after 7 and 30. Each output of the edge detectors 27 and 30 is supplied to the delay device 33 via the OR circuit 32, and the delay device 33 delays by 1/2 symbol. And is supplied to the AND circuit 25.

FIG. 4 shows a further embodiment of the present invention. In the structure for detecting the 60 ° cross of the phase difference Δθ shown in FIG. 1, the phase difference Δθ of − is similar to this structure. 60
° A configuration to detect cross is added. Therefore, the decision circuit 24 includes an exclusive OR circuit 24e and an AND circuit.
24f is added, and the output of the AND circuit 24f is supplied to the AND circuit 34 to gate-control the output of the edge detector 30 on the -60 ° cross detection side. AND circuit 25
The output of the edge detector 30 to which is added is supplied to the symbol counter 17 via the OR circuit 35.

[0030]

As described above, according to the present invention, there is provided a clock synchronization method and a circuit in which the influence of band limitation on a received signal is reduced and good clock synchronization can be obtained at a high response speed. Can be provided.

[Brief description of drawings]

FIG. 1 is a π / 4 shift QPSK according to an embodiment of the present invention.
The block diagram which shows the structure of the clock synchronization circuit for signal reception.

FIG. 2 is a π / 4 shift QPSK according to an embodiment of the present invention.
The block diagram which shows the other structural example of the clock synchronization circuit for signal reception.

FIG. 3 is a π / 4 shift QPSK according to an embodiment of the present invention.
The block diagram which shows the other structural example of the clock synchronization circuit for signal reception.

FIG. 4 is a π / 4 shift QPSK according to an embodiment of the present invention.
The block diagram which shows the other structural example of the clock synchronization circuit for signal reception.

FIG. 5 is a block diagram showing a configuration of a conventional general π / 4 shift QPSK signal receiving clock synchronization circuit.

FIG. 6 is a diagram showing an eye pattern of a π / 4 shift QPSK signal.

[Explanation of symbols]

11 ... Phase detector, 12, 22, 23 ... (1 symbol) delay device,
13 ... Subtractor, 14, 15 ... Judgment device, 16 ... Edge detector, 17 ...
Symbol counter, 21 ... Comparator, 24 ... State determination circuit, 25
… And circuit, 26… (1/2 symbol) delay device.

Claims (3)

[Claims] 1. When a phase difference between a reception signal subjected to band limitation and a reception signal one symbol before the reception signal crosses a predetermined value, two positions separated by one symbol with the timing sandwiched therebetween. A clock synchronization method characterized in that clock synchronization is performed only when the phase difference has a predetermined relationship. 2. When the phase difference between the reception signal subjected to band limitation and the reception signal of one symbol before the reception signal crosses a predetermined value, the phase difference of 1/2 symbol before and the 1/2 symbol A clock synchronization method characterized in that clock synchronization is established only when a phase difference after a minute has a predetermined relationship. 3. A phase difference detecting means for detecting a phase difference between a reception signal subjected to band limitation and a reception signal one symbol before the reception signal, and a phase difference detecting means for separating by one symbol. And a comparing means for comparing the phase difference obtained by the phase difference detecting means with a predetermined set value, and a state judging means for judging this when the combined state of the two phase differences becomes a preset state. And an edge detection means for detecting a change point of the comparison result obtained by the comparison means and outputting an edge detection signal, and an output timing of the edge detection signal which is provided before or after the edge detection means and has a 1/2 symbol Delay means for delaying by a minute, gate control means for controlling passage of the edge detection signal delayed by 1/2 symbol based on the determination result of the state determination means, and passage through the gate control means And a counting unit that is synchronized by the edge detection signal.