JPH0779135B2 - Method for manufacturing semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a contact portion and a manufacturing method thereof.

2. Description of the Related Art In the manufacturing process of a MOS type semiconductor device, in order to prevent disconnection of aluminum wiring and prevent aluminum residue in a step portion when wiring is processed using anisotropic dry etching,
Smoothing is performed by phosphorus glass flow treatment so that the unevenness of the gate electrode, wiring, etc. is not reflected on the surface of the PSG protective film above it. This state is shown in FIG.
A sectional view of the semiconductor device is shown in FIG. In the figure, 3 is a gate oxide film, 4 is poly Si, 5 and 10 are titanium silicide,
6 is a side wall, and the surface of PSG11 is smooth. Conventionally, in order to connect an aluminum wiring with an element such as a transistor, as shown in FIG. 4b, the PSG11 on the region of the source / drain diffusion layer 14 and the gate wiring provided on the Si substrate is formed.
At the same time, the contact windows 17 and 18 were simultaneously opened.

Problems to be Solved by the Invention However, when the PSG film flows due to the glass flow process and the gate electrode / wiring distance is narrow like VLSI, the film thickness of the PSG11 becomes large in the source / drain diffusion region 14 between the electrode wiring. , Because it is thin on the electrode wiring, a fine contact window is opened in PSG11.Therefore, if anisotropic dry etching is performed with a gas such as CHF ₃ , C ₃ F ₈ or the like, contact window 17 will be contacted during complete etching. 18 was in an over-etched state, and there was a problem that the underlying titanium silicide TiSi _X was also etched to some extent as shown in FIG. 4B. Therefore, it is difficult to open both contact windows with good controllability.

The present invention has been made in view of the above points, and a MOS
An object of the present invention is to provide a structure of a contact portion and a manufacturing process thereof in which the problem of dry etching for opening a contact window does not occur in a semiconductor device.

Means for Solving the Problems In order to solve the above problems, the present invention provides a pedestal having a thickness similar to that of a gate electrode / wiring in the vicinity of a region of a diffusion layer of a semiconductor substrate where a contact is to be formed. The electrode is drawn out onto the pedestal to form a contact structure in which a contact window is opened on the pedestal.

Action According to the present invention, the pedestal is higher than the diffusion layer of the semiconductor substrate and has the same height as the gate electrode / wiring by the above-described forming method. It has almost the same thickness as the film. Therefore, the contact windows on the gate electrode / wiring and the pedestal can be opened in substantially the same etching time, and one of the windows is not overetched.

EXAMPLE FIG. 1 is a process sectional view for manufacturing a contact structure of the present invention, showing a part of a MOS type semiconductor integrated circuit device. The process shown in FIG. 1a is performed by forming a 100 nm-thick poly Si film 4 and a 200 nm-thickness on the entire surface of the gate oxide film 3 having a thickness of 10 nm and the SiO ₂ film 2 having a thickness of about 1 μm on the surface of the P-type Si substrate 1. Titanium silicide (TiSi _x ) film 5 of 2 is sequentially removed by selective removal of M
This is a stage where the polycide gate electrode a, the contact pedestal b, and the gate wiring c of the OS type transistor are simultaneously formed in the same structure. Reference numeral 6 is a sidewall made of SiO ₂ provided after forming these a, b and c. Next, Ti7, which is one of the refractory metals, is vacuum-deposited and sputtered on the entire surface to a thickness of 50 nm by a CVD method or the like, and an amorphous Si film 8 is vacuum-deposited and sputtered on 7 and plasma CV.
It is deposited to a thickness of 50 nm using the D method or the like (step of FIG. 1b). The amorphous Si film 8 can be dry-etched by using a fluorocarbon gas such as CF ₄ with almost no etching of the underlying Ti film 7. In this way, the film 8 is selectively removed, leaving only the portion extending from the source / drain region of the transistor to the pedestal b for forming a contact. Then, Si ⁺ ions and As ⁺ ions 9 that will later form the source / drain diffusion layer are added to KeV × 10 ¹⁵ / cm ² , K respectively.
Inject under the condition of eV × 10 ¹⁵ / cm ² . Both Si ⁺ ion and As ⁺ ion implantation are performed with the Ti film 7 and the Si substrate interface, with the amorphous Si film 8.
It also serves to form a Ti—Si mixed layer at the interface of the Ti film 7 (step of FIG. 1c). After ion implantation, when heat treatment is performed at 500 ° C. to 700 ° C. for several tens of seconds to 30 minutes in N ₂ or Ar or vacuum, TiSi _X is present in the contact portion between the Si substrate 1 and the Ti film 7 and the portion where the amorphous Si 8 exists. , But the other parts remain as Ti film. Residual Ti can be removed with H ₂ O ₂ + NH ₄ OH solution, and only TiSi _X 10 in the source / drain region and the electrode TiSi _X 10 ′ extracted from 10 to pedestal b remain 10 and 10 ′ electrically. Is connected (step in FIG. 1d). Then PSG film 11
Is formed to a thickness of about 700 nm and a phosphorus glass flow is performed, the As implanted in step c diffuses into the Si substrate 1 to form an n ⁺ layer 14, and the PSG film 11 has a source and drain region of about 900 nm.
nm, pedestal b, and gate wiring c are about 400 nm.
When the source / drain signal extraction contact film 12 is opened on the pedestal b, the PSG film 11 has almost the same thickness b and c.
It can be opened under the same etching conditions as 13 (first
Step of FIG. E). Finally, the aluminum alloy wiring 15 is formed so as to cover the contact windows 12 and 13 (step of FIG. 1F).

FIG. 2 is a sectional view of a semiconductor device showing a second embodiment of the present invention. In this case, the contact forming pedestal b is Si
Since it is provided on the substrate 1 and is formed at the same time as the gate electrode a, the gate oxide film 3, poly Si 4, and TiSi _x are formed in the same manner as a.
It has a structure of 5.

FIG. 3 shows a third embodiment of the present invention. In this case, the pedestal TiSi is the same as the gate electrode a and the gate wiring c.
_This is a case where an insulating film 16 made of SiO ₂ , PSG, Si ₃ N ₄ or the like is further provided on the _X film 5. In the case of such a contact structure as well, the source / drain regions 14 and the TiSi _X 10 ′ extraction electrodes can maintain electrical connection, so that the characteristics of the first and second embodiments are completely the same. The insulating film 16 protects the gate electrode structure together with the sidewalls 6 from external pollution in an oxidizing atmosphere, and prevents the implanted ions into the source / drain regions from entering the gate electrode as shown in step c in FIG. It is used when it is necessary to prevent it.

Although the lead electrode is TiSi _{X in the} above-mentioned embodiments, other refractory metals such as Mo, W, Ta, Hf and Zr shown in FIG. 1 may be used, and the lead electrode may be silicide thereof.

EFFECTS OF THE INVENTION As described above, the present invention intends to make contact with a semiconductor substrate on a pedestal having the same height as the contact surface on the gate electrode / wiring. In this case, the pedestal is used. Since the film thickness of PSG etc. after glass flow is almost the same on the top and on the gate / electrode / wiring, PSG
At the time of opening a contact to a film or the like, overetching that has been conventionally seen does not occur. In addition, since the PSG film thickness is thin on the pedestal, the depth of the contact window opening is shallow, and there is an additional effect that the step coverage at the contact opening portion of the aluminum film for wiring is also improved. It is effective.

[Brief description of drawings]

1A to 1F are process sectional views showing a manufacturing method in a first embodiment of a semiconductor device of the present invention, FIG. 2 is a sectional view for explaining the method of the second embodiment, and FIG. 3 is a cross-sectional view for explaining the method of the third embodiment, and FIGS. 4A and 4B are process cross-sectional views for explaining the conventional method for manufacturing a semiconductor device. 1 ... Silicon substrate, 2 ... Thick SiO ₂ film, 3 ... Gate oxide film, 4 ... Poly Si, 5,10,10 '... Titanium silicide, 6 ... Side wall, 7 ... Ti, 8 …… Amorphous Si, 9 …… Injected ions, 11 …… PSG, 12,13 …… Contact window, 14 …… Source / drain diffusion layer, 15 …… Aluminum alloy wiring, 16 …… Insulating film.

Claims (1)

[Claims] 1. A step of forming a pedestal having substantially the same height as the wiring on a semiconductor substrate having wiring formed thereon, and a refractory metal film and a semiconductor film covering the exposed portion of the pedestal and the surface of the semiconductor substrate. And a step of forming a pattern connected to at least a part of the pedestal from the exposed portion of the semiconductor substrate by selectively removing the semiconductor film, and then performing a heat treatment. Forming a compound film conductive layer by reaction with the melting point metal film, removing the unreacted refractory metal film, and forming an insulating film so as to cover the compound film and the wiring, A method of manufacturing a semiconductor device, comprising: forming a compound film on the pedestal and an opening reaching the wiring in the insulating film by etching.