JPH0778056A - Semiconductor disk device - Google Patents

Abstract

PURPOSE:To vary the storage capacity of the semiconductor disk device without exerting any influence upon data in a flash EEPROM which relates to neither chip replacement nor extension. CONSTITUTION:When a drive number #0 is specified from a host system, a 1st memory block 1 is selected and when a drive number #1 is specified, a 2nd memory block 2 is selected. Consequently, the 1st and 2nd memory blocks 1 and 2 are different disk drives when viewed from the host system, and data written in flash EEPROMs 11-1 to 11-3 of the 1st memory block 1 and data written in flash EEPROMs 11-4 to 11-6 of the 2nd memory block 2 are individually managed. Therefore, even if chip replacement or extension is performed in the 2nd memory block 2, files written in the flash EEPROMs 11-1 to 11-3 of the 1st memory block 1 are not affected at all.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor disk device provided with a flash EEPROM which is a non-volatile memory capable of electrically batch erasing, and in particular, a host device which designates a disk device to be accessed by a drive number. Flash EE in response to disk access request
The present invention relates to a semiconductor disk device that accesses a PROM.

[0002]

2. Description of the Related Art Many conventional information processing apparatuses such as workstations and personal computers use magnetic disk devices as storage devices. The magnetic disk device has advantages such as high recording reliability and a low bit unit price, but has drawbacks such as a large device size and weak physical shock.

The magnetic disk device has an operating principle of magnetically writing data on a rotating disk or reading them by running a magnetic head on the disk surface. Mechanically movable parts such as the rotating disk and the magnetic head may naturally malfunction or fail due to physical impact on the device. Further, the need for such a mechanically movable portion is an obstacle to reducing the size of the entire device.

For this reason, the magnetic disk device does not hinder the use of a desktop type computer which is fixedly mounted on a desk, but these disadvantages exist in a portable and small laptop computer or notebook computer. Is a big problem.

Therefore, in recent years, attention has been focused on a semiconductor disk device which is small in size and resistant to physical shock. The semiconductor disk device uses a flash EEPROM, which is a non-volatile memory that can be electrically collectively erased, as a secondary storage device such as a personal computer like a conventional magnetic disk device. Since this semiconductor disk device does not have a mechanically movable part like a magnetic disk device, malfunctions and failures due to physical shocks are unlikely to occur. Further, there is an advantage that the size of the device is reduced.

Further, the semiconductor disk device has an advantage that it is possible to easily change the physical storage capacity, which is difficult with the magnetic disk device. That is, since the storage medium of the semiconductor disk device is a flash EEPROM, the storage capacity can be changed relatively easily by replacing or adding the chip.

For example, if a part of a plurality of flash EEPROMs provided in a semiconductor disk device is partially replaced with another chip having a large storage capacity or a new chip is added, the memory of the semiconductor disk device is stored. The capacity can be increased.

However, even if the physical storage capacity of the semiconductor disk device is changed by such chip replacement or extension, even if the physical storage capacity of the semiconductor disk device is changed, a plurality of flash EEPs are generated.
Even if some of the ROMs are partially replaced or only some chips are added, the data stored in the semiconductor disk device cannot be used as it is.

This is because file management by the host system is performed in drive number units, so in a semiconductor disk device specified by a certain drive number, one file stores a plurality of flash EEPROMs in the semiconductor disk device. This is because it is often distributed and stored in. In this case, even if the chip replacement is partial, if the data stored on that chip is part of a file stored on another chip, the contents of the file itself are guaranteed. The problem of disappearing occurs.

Further, even when the number of chips is increased,
In order to effectively use the storage area increased by the addition, it is necessary to rearrange files and the like, so it is practically difficult to directly use the data on the flash EEPROM which is not related to the chip addition.

[0011]

Conventionally, when the physical storage capacity of a semiconductor disk device is changed by chip replacement or expansion, even if the physical storage capacity of the semiconductor disk device is changed, a plurality of flash E
Even if some of the EPROMs are partially replaced or only some chips are added, there is a drawback that the data stored in the semiconductor disk device cannot be used as it is.

The present invention has been made in view of the above points, and a flash EE not related to chip replacement or extension.
An object of the present invention is to provide a semiconductor disk device which can easily change the storage capacity without affecting the data on the PROM.

[0013]

Means and Actions for Solving the Problems
Disk access from a host device including a plurality of flash EEPROMs and including a drive number for specifying a disk drive to be accessed and a logical address for addressing a disk recording medium included in the disk drive to be accessed A semiconductor disk device for accessing the flash EEPROM in response to a request, wherein first and second drive numbers that can be designated by the disk access request are respectively assigned, and first and second drives each having a flash EEPROM. A memory block, address conversion means for converting the logical address into a physical address for accessing the flash EEPROM of the first or second memory block according to address conversion information, and designated by the host device In response to said drive No. 1
And one of the second memory blocks is selected,
Flash EEPROM of the selected memory block
Memory access means for performing read / write access according to the physical address translated by the address translation means, the first and second memory blocks, the address translation means, and a circuit board provided with the memory access means. It is characterized by doing.

In this semiconductor disk device, the first
First and second drive numbers are respectively assigned to the first and second memory blocks, and the first and second different drive numbers are responsive to the first and second drive numbers designated by the host device, respectively. A memory block is selected for access. Therefore, when viewed from the host device, the first and second memory blocks serve as different disk drives, and the data written in the flash EEPROM of the first memory block and the flash EEPROM of the second memory block.
The data written in M will be managed separately. Therefore, one file is the first and second
Therefore, even if the flash EEPROM chip is replaced or added in the second memory block, it is not written in the first memory block.
The file stored in the memory block of is not affected at all. Therefore, it is possible to easily change the storage capacity of the semiconductor disk device without affecting the data on the flash EEPROM which is not related to chip replacement or expansion.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a semiconductor disk device according to an embodiment of the present invention. The semiconductor disk device 10 is connected to a host system 1 such as a personal computer and used as an alternative to a hard disk device, and is a flash EEPROM 11-1.
11-6, IC sockets 11A and 11B, a host interface 12, and a controller 20. The flash EEPROMs 11-1 to 11-6 are used as the recording medium of the semiconductor disk device 10 and correspond to the magnetic recording medium of the hard disk device. The IC sockets 11A and 11B are slots for adding flash EEPROMs as needed.

These flash EEPROMs 11-1 to 11-1
11-6 and the IC sockets 11A and 11B are connected to the controller 20 via a common I / O bus and a read / write control signal line. Further, the controller 20 and the flash EEPROMs 11-1 to 11-6
And chip select signal (CS1 to CS8) lines between the IC sockets 11A and 11B, and Ready.
/ Busy signal line is provided independently for each chip.

These flash EEPROMs 11-1 to 11-1
In 11-6, the minimum unit is set for the amount of data handled when writing or erasing, and the data for that unit is handled collectively. Here, as an example, it is assumed that the flash EEPROMs 11-1 to 11-6 can write data in 256-byte page units and the data erasing unit is a 4 Kbyte block unit. In this case, these flash EEPROMs have NA
It is preferable to use an ND type flash EEPROM.

Flash EEPROM 11-1 to 11-
Reference numeral 6 denotes a first memory block composed of the flash EEPROMs 11-1 to 11-3, and the flash EEPROM.
It is divided into a second memory block composed of OMs 11-4 to 11-6. Drive numbers # 0 and # 1 are assigned to the first and second memory blocks, respectively, and are treated by the host system 1 as a master drive and a slave drive, respectively.

The IC sockets 11A and 11B have flash EEP in the first memory block or the second memory block.
This is for adding ROM, and a flash EEPROM is mounted if necessary.

The semiconductor disk device 10 also includes a host interface 12 and a controller 20. The host interface 12 has a pin arrangement of 40 pins conforming to the IDE interface that can be connected to the system bus of the host system 1.

The controller 20 is realized by one LSI, and an interface controller circuit 13, an access control circuit 14, and a data buffer 15 as shown in the figure are integrated and formed on the LSI chip.

The interface controller 13 communicates with the host system 1 via the host interface 12. This interface controller 13
Is provided with an interface register group including a sector number register 131, a sector count register 132, a data register 133, a cylinder register 134, a drive / head register 135, a command register 136, a status register 137, and the like. These registers can be read / written by the host system 1.

The sector number of the access start position is written in the sector number register 131 by the host system 1. The host system 1 writes the number of read / write target sectors to the sector count register 132. In the data register 133, write data input from the host system 1 or read data output to the host system 1 is set. The cylinder number of the read / write target is written in the cylinder register 134 by the host system 1. The drive / head register 135 is written by the host system 1 with the read / write target drive number and the head number. A read command, a write command, and the like are written in the command register 136 by the host system 1. The status register 137 contains the semiconductor disk device 1 for notifying the host system 1.
Various statuses of 0 are set.

The access controller 14 includes an MPU,
The flash EEPROM 11- includes a local memory in which a firmware program for controlling the operation of the MPU is stored, and which responds to a disk access request supplied from the host system 1 via the host interface 12 and the interface controller 13.
Access control is performed on 1 to 11-6.

That is, M of the access controller 14
The PU reads various commands and parameters set in the register group of the interface controller 13,
Depending on the contents, flash EEPROM 11-1 to 1
Access control 1-6.

Further, the access controller 14 is provided with an address conversion table 141. The address conversion table 141 includes logical addresses from the host system 1 and the flash EEPROMs 11-1 to 11-6.
The address translation information indicating the correspondence with the physical address for accessing is defined. Here, the logical address is an address for disk access and is determined by the cylinder number, head number, sector number, and drive number. Physical address is Flash E
This is an address for selectively accessing the EPROMs 11-1 to 11-6, and is determined by the chip number and the memory address. This address conversion table 1
41 can be stored in any of the flash EEPROMs 11-1 to 11-6.

When the drive number is # 0, the flash EEPROMs 11-1 to 11-of the chip numbers # 1 to # 3
3 is selected as the access target and the drive number is # 1
In case of, flash EEPR of chip numbers # 4 to # 6
OMs 11-4 to 11-6 are selected as access targets.

The access control circuit 14 performs selection of the flash EEPROMs 11-1 to 11-6 and read / write control of data for the selected flash EEPROM according to the conversion result of the address conversion table 141. In this case, the access controller 14 uses the flash EEP corresponding to the memory chip number output from the address conversion table 141.
To select ROM, first, flash EEPROM
Chip selection signals CS1 to CS6 are provided to M11-1 to 11-6.
To selectively supply.

For example, when the drive number designated by the host system 1 is # 0, the flash EEPROM
Chip selection signal CS1 corresponding to M11-1 to 11-3
~ CS3 is selectively generated. On the other hand, when the drive number designated by the host system 1 is # 1, the chip selection signals CS3 to CS6 corresponding to the flash EEPROMs 11-3 to 11-6 are selectively generated.

After this, the access control circuit 14
Generates a memory address output from the address conversion table 141 as a start address, and sequentially reads the start address so that the read / write operation of data for the number of sectors sent from the host system 1 is executed. Count up.

In this case, access to the flash EEPROM is performed by a command method in which the operation mode of the flash EEPROM is designated by a command. That is, the access control circuit 14 first specifies the operation mode (write mode, read mode, erase mode, verify mode, etc.) of the flash EEPROM, and then the address indicating the access position (address and write data in the write mode). ) Flash EEP
Supply to ROM. The flash EEPROM is provided with an input / output register of 256 bytes, for example. Therefore, in the write mode, for example, after the write data is transferred to the register, the flash EEPR
Since the write operation is executed inside the OM, the access control circuit 14 is released from the control of the write access.

Furthermore, the access controller 14 manages the number of times of rewriting of each of the flash EEPROMs 11-1 to 11-6 by using the write count information provided in each of the chips. This write count information is incremented by +1 when the rewriting is executed a predetermined number of times (hundreds to thousands). In addition, the access controller 14
Configuration information such as the number of chips currently mounted and the storage capacity of the entire semiconductor disk device 10 is stored in the flash E.
It is managed using the CONFIG table stored in any of the EPROMs 11-1 to 11-6.

The data buffer 15 is the host system 1
Write data and flash memory 11 sent from
The read data from -1 to 11-6 is held. In this semiconductor device 10, the flash EEPROM 1
The first memory block composed of 1-1 to 11-3 is selected by the first drive number # 0, and the flash E
The second memory block composed of the EPROMs 11-4 to 11-6 is selected by the second drive number # 1. Therefore, from the perspective of the host system 1, those first
And the second memory block become different disk drives, and the flash E of the first memory block
Data written to the EPROMs 11-1 to 11-3 and the flash EEPROM 1 of the second memory block
The data written in 1-4 to 11-6 will be managed separately. This state is conceptually shown in FIG.

As shown in FIG. 2, the semiconductor disk device 10 is treated as two drives by the FAT file system of the host system 1, and the flash EEPROM 11 corresponding to the drive of drive number # 0.
The file management of -1 to 11-3 is performed using the first file management information (FAT1), and the flash EEPROM 11-3 corresponding to the drive of the drive number # 1.
The file management of 11-6 is the second file management information (F
AT2) is used.

In this case, all files managed by FAT1 are flash EEPROMs 11-1 to 11-11.
-3 and all files managed by FAT2 are stored in flash EEPROMs 11-4 to 11-6.

Therefore, since one file is not written in a distributed manner in the first and second memory blocks, for example, in any of the flash EEPROMs 11-3 to 11-4 in the second memory block. Even if a new flash EEPROM is added to the second memory block by exchanging the flash memory or using the IC slots 11A and 11B, the flash EEP of the first memory block
The files stored in the ROMs 11-1 to 11-3 are not affected at all.

Therefore, the flash EEPROM 11
It is possible to easily change the storage capacity of the semiconductor disk device 10 without affecting the contents of -1 to 11-3.

Next, referring to FIG. 3, the semiconductor disk 1
An example of an actual implementation of 0 will be described. In FIG. 3, the first
Memory block flash EEPROMs 11-1 to 11-1
Only the portions corresponding to 1-3 are shown as a representative.

That is, all the constituent units of the semiconductor disk device 10 shown in FIG. 1, that is, the controller 2
0, Flasher EEPROM 11-1 to 11-6, IC
Although the sockets 11A and 11B are mounted on the printed circuit board 30, the flash EEPROMs 11-1 to 11
-6 is not directly on the printed circuit board 30,
Each is mounted via the corresponding IC socket.

For example, the flash EEPROMs 11-1 to 11-3 of the first memory block are mounted on the printed circuit board 30 via the corresponding IC sockets 21A to 21C, respectively. These sockets 21A
21C are to mount the flash EEPROM on the printed circuit board 30 in the same manner as the IC sockets 11A and 11B described above.

In the semiconductor disk device 10 thus configured, the flash EEPROMs 11-1 to 11-3 mounted in the three sockets 21A to 21C can be easily replaced with other chips as needed. it can.

In the same manner, the flash EEPRO
Since M11-4 to 11-6 are also mounted on the printed circuit board 30 via the corresponding IC sockets,
Tips can be easily replaced.

Here, the address conversion table 1
The address conversion information of 41 is divided into two for the drive number # 0 and the dry number # 1, but two types of address conversion tables are prepared in advance for the first memory block and the second memory block, and these address conversion tables are prepared. It is also possible to select by the drive number specified by the host system 1.

Further, the translation information of the address translation table 141 can be defined as shown in FIG. That is, in the address conversion table 141 of FIG.
The drive number is not defined, instead the first
Memory block flash EEPROMs 11-1 to 11-1
Flash EEPROM of 1-3 and second memory block
Sequential sector numbers are assigned to 11-4 to 11-6.

Since the host system 1 manages the sector number independently for each drive, originally, the sector numbers assigned to the flash EEPROMs 11-1 to 11-3 of the first memory block and the second memory block are assigned. The sector numbers assigned to the flash EEPROMs 11-4 to 11-6 all start from "0".

However, here, the values obtained by adding the offsets of n + 1 to the original sector numbers "0" to "m" assigned to the flash EEPROMs 11-4 to 11-6 of the second memory block are generated. It is registered in the address conversion table 141.

Hereinafter, with reference to the flowchart of FIG.
The operation of the entire semiconductor disk device 10 including the address conversion operation using the address conversion table 141 of FIG. 4 will be described.

First, the host system 1 writes a read / write command in the command register 136 (step S11). Next, the hardware of the interface controller 13 sets the busy flag (BSY) in the status register 137 (step S12). When the firmware of the access controller 14 detects that a command has been written in the command register 136, the following command processing is started accordingly (steps S13 and S1).
4).

That is, the firmware first reads a command from the command register 136, interprets the code of the command, and determines the command content (step S16). In this command determination processing, the command processing firmware corresponding to the command code is called and activated.

The activated firmware generates a sector address for searching the address conversion table 141 based on the drive number (Drive #) and the sector number designated by the host system 1. This sector address is: sector address = sector number + offset × (0
It is obtained by the operation of OR 1).

The offset value is n + 1 as described above, and when the drive number is # 0, the sector number designated by the host system 1 is as it is in the address conversion table 1.
It becomes the sector address for searching 41. On the other hand, when the drive number is # 1, the offset value (n + 1) is added to the sector number designated by the host system 1, and the addition result becomes the sector address for searching the address conversion table 141.

Next, the firmware executes the command, and according to the chip number and the memory address obtained by searching the address conversion table 141, the flash EEPROMs 11-1 to 11-3, or the flash E.
Access control is performed on the EPROMs 11-4 to 11-6 (steps S18 and S19).

As described above, in the semiconductor disk device 10 of this embodiment, when viewed from the host system 1,
The first and second memory blocks serve as different disk drives, and the data written in the flash EEPROMs 11-1 to 11-3 of the first memory block and the flash EEPROM of the second memory block.
The data written in 11-4 to 11-6 are managed separately by the FAT file system of the host system 1. For this reason, one file is not written in a distributed manner in the first and second memory blocks. For example, even if the flash EEPROM chips are replaced or added in the second memory block, The files stored in the memory block are not affected at all. Therefore, the semiconductor disk device 10 is not affected without affecting the data on the flash EEPROM which is not related to chip replacement or expansion.
It is possible to easily change the storage capacity of the.

Next, the management operation for the flash EEPROM newly mounted by chip replacement / expansion will be described. FIG. 6 shows a flash EEPROM in which the number of times of rewriting has reached a certain value or more and becomes exchange symmetric.
With a new flash EEPR
A series of processes in the case of being replaced by the OM is shown.

As described above, the access controller 14
Indicates the number of times of rewriting the flash EEPROM 11-1 to
11-6 manages using the write counter stored in each, and when the number of times of rewriting of a certain flash EEPROM reaches a certain value or more, the chip number is notified to the host system 1. Host system 1
Responds to the inquiry from the user and displays a message indicating the chip number that needs to be replaced on the display monitor and presents it to the user.

Upon recognizing the necessity of chip replacement, the user first installs a new flash EEPROM in an empty slot which is not used at that time, for example, the slot 11A, and specializes in making the new flash EEPROM usable. The utility program is loaded from the HDD or FD of the host system 1 into the main memory of the system 1 and executed (steps S21, S22). At this time, the chip number to be replaced is specified by the user.

Next, a command is transferred from the host system 1 to the semiconductor disk device 10, and a program relating to chip replacement is executed by the MPU of the access controller 14 of the semiconductor disk device 10.

The MPU of the access controller 14 first reads all the information stored in the replacement source chip,
The chip is newly copied to the slot 11A (step S23). For example, when the flash EEPROM 11-1 with the chip number # 1 is the replacement source chip, all the contents of the flash EEPROM 11-1 are newly installed in the slot 11A.
Copied to ROM.

Here, the slot number in which the new chip is mounted can be detected by referring to the Ready / Busy signal line. That is, when the flash EEPROM is mounted in the slot 11A, the Ready / Busy signal line corresponding to the slot 11A, which has been fixed to the indefinite level or the GND level until then, is set to the Ready state (H level) by the flash EEPROM. Therefore, the Ready / Bu
It is possible to detect in which slot the chip is mounted by the potential change of the sy signal line.

In the copy process, flash EEP
The value of the write counter of the ROM 11-1 is also copied to the new flash EEPROM. Therefore, MP
U is the newly installed flash E after the copy process
The value of the write counter of the EPROM is rewritten to the initial value "0" (step S24).

Next, the MPU rewrites the address conversion table 141 to replace the flash EEPROM 1 of the replacement source.
The logical address assigned to 1-1 is mapped to the newly mounted flash EEPROM (step S25). For example, the newly installed flash E
When the chip number of the EPROM is # 7, the address conversion table 141 of FIG. 1 shows that all entries in which the chip number # 1 is registered include the chip number # 1 to the chip number #.
Changed to 7.

After that, when the MPU issues a command end status to the host system 1, a message indicating the command end is displayed on the display monitor of the host system 1 and presented to the user (step S26). The user removes the flash EEPROM of the replacement source (step S27). After that, by using the newly installed flash EEPROM, drive # 0
The disk access of can be performed as before.

In this case, the flash EE having the same memory size as the flash EEPROM which has been exchanged symmetrically.
Although the case where the PROM is mounted has been described as an example, the replacement source chip and the replacement destination chip do not necessarily have to have the same memory size, and for example, another type of chip having a larger capacity than the replacement source chip is newly mounted. You can also

Hereinafter, with reference to FIG. 7, a flash EEPROM (chip type 1) which is exchange symmetrical will be described.
A series of processes for replacing with a new flash EEPROM (chip type 2) having a double storage capacity will be described.

When the user knows that the chip needs to be replaced,
First, an empty slot not used at that time, for example, slot 1
1A is equipped with a new flash EEPROM, and a dedicated utility program for enabling the new flash EEPROM is loaded from the HDD or FD of the host system 1 into the main memory of the system 1 and executed. (Steps S31, S32). At this time, the chip number to be replaced is specified by the user.

Next, a command is transferred from the host system 1 to the semiconductor disk device 10, and a program relating to chip replacement is executed by the MPU of the access controller 14 of the semiconductor disk device 10.

The MPU of the access controller 14 first determines the flash EEPRO installed in the slot 11A.
Detect M chip type. The chip type detection process can be performed depending on whether the ID (B0B0) stored in advance at the start address of the second chip area of the flash EEPROM can be normally read.

That is, the MPU makes a read access to the start address of the second chip area of the flash EEPROM mounted in the slot 11A, and determines the chip type depending on whether the read data matches a predetermined ID. (Steps S33, S34). In this case, if the read data and the ID match, chip type 2,
If they do not match, chip type 1 is determined.

Flash E mounted in slot 11A
When the EPROM is the chip type 2, the MPU determines the first chip area of the flash EEPROM as a substitute chip area and the second chip area as an additional chip area (step S35).

Then, the MPU copies all the information stored in the replacement source chip to the alternative chip area (step S36). For example, when the flash EEPROM 11-1 with the chip number # 1 is the replacement source chip, all the contents of the flash EEPROM 11-1 are newly installed in the slot 11A.
Copied to the alternate chip area of the PROM. in this case,
Since the value of the write counter of the flash EEPROM 11-1 is also copied, the MPU returns the value of the write counter of the alternative chip area to the initial value "0" (step S37).

Next, the MPU rewrites the address conversion table 141 to replace the flash EEPROM 1 of the replacement source.
The logical address assigned to 1-1 is mapped to the alternative chip area, and a new logical address space continuous to the logical address space of drive # 0 is mapped to the expanded chip area (step S38).

For example, if the chip number of the flash EEPROM newly installed in the slot 11A is # 7, the address conversion table 141 of FIG. 1 shows that all entries registered with the chip number # 1 are chip numbers # 1.
To chip number # 7. Further, an entry of the address conversion table 141 is added, and a new logical address space corresponding to the capacity of the additional chip is assigned there. In this case, the chip number of the additional chip is # 7 as in the alternative chip, but its head memory address starts from the value next to the final address of the alternative chip.

After that, when the MPU issues a command end status to the host system 1, a message indicating the command end is displayed on the display monitor of the host system 1 and presented to the user (step S39). The user removes the flash EEPROM of the replacement source (step S40).

Next, with reference to FIG. 8, a procedure for simply adding chips without replacing the chips will be described. Here, in the state where only the flash EEPROMs 11-1 to 11-3 with the drive number # 0 exist in the semiconductor disk device 10, the newly added flash EE
The case where the PROM is handled as the memory block having the drive number # 1 will be described as an example.

The user first creates a new flash EEP in an unused slot that is not used at that time, for example, the slot 11A.
After mounting the ROM, the host system 1 is powered on (step S51). In response to this power-on, the MPU of the access controller 14 detects the number of chips existing in the semiconductor disk device 10 (step S52). The number of chips is the Ready / Bus that is independently supplied from each chip to the access controller 14.
It can be detected by referring to the y signal line. That is, the flash EE immediately after power-on
Since the Ready / Busy signal line of the PROM is maintained in the Ready state (H level), the Read / Busy signal line of H level is read.
The number of chips can be detected by the number of y / Busy signal lines.

Next, in the MPU, the detected chip number is registered in the Config table (here, the chip number is the flash EEPROM 11-1).
When the number of chips is larger than the above, the additional chips are recognized, and the expanded chips are assigned to the drive # 1 (step S53). The MPU adds an entry corresponding to the logical address space of the drive # 1 to the address conversion table 141, and maps the logical address space of the drive # 1 to the added chip (step S54). After this, MPU is Config
The contents of the g table are rewritten to values including the additional chips (step S55).

As a result, thereafter, this semiconductor disk device is handled by the host system 1 as two disk devices corresponding to the drive numbers # 0 and # 1. Not only the number of drives but also the storage capacity of drive # 0 or drive # 1 can be increased by adding chips. For example, when the capacity of the drive # 1 is increased, a new logical address space continuous to the logical address space of the drive # 1 may be mapped to the added chip.

As described above, this semiconductor disk device 1
In 0, it is possible to easily replace / increase the recording medium inside the drive unit, which is impossible with the conventional HDD, by a method such as chip replacement / chip expansion and independently for each drive number.

[0079]

As described in detail above, according to the present invention, since one semiconductor disk device can be treated as two drives, one of the drives can be treated without affecting the data of the other drive. It becomes possible to replace or add chips to the drive.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor disk device according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing how drive numbers are assigned to the semiconductor disk device of the embodiment.

FIG. 3 is a perspective view showing an example of a mounting form of the semiconductor disk device of the embodiment.

FIG. 4 is a diagram showing a configuration example of an address conversion table provided in the semiconductor disk device of the same embodiment.

5 is a flow chart for explaining an address conversion operation using the address conversion table of FIG.

FIG. 6 shows a flash E of the semiconductor disk device of the same embodiment.
The flowchart for demonstrating a series of processing procedures at the time of exchanging EPROM.

FIG. 7 shows a flash E in the semiconductor disk device of the embodiment.
6 is a flowchart for explaining a series of processing procedures when replacing an EPROM with a chip having a larger storage capacity.

FIG. 8 shows a flash E in the semiconductor disk device of the same embodiment.
The flowchart for demonstrating a series of processing procedures at the time of adding EPROM.

[Explanation of symbols]

1 ... Host system, 10 ... Semiconductor disk device, 11
-1 to 11-6 ... Flash EEPROM, 12 ... Host interface, 13 ... Interface controller, 14 ... Access controller, 15 ... Data buffer.

Claims (5)

[Claims] 1. A host including a plurality of flash EEPROMs, including a drive number for designating an access target disk drive and a logical address for addressing a disk recording medium included in the access target disk drive. A semiconductor disk device for accessing the flash EEPROM in response to a disk access request from a device, wherein first and second drive numbers that can be designated by the disk access request are respectively assigned, and each has a flash EEPROM. First and second memory blocks, and the first and second logical blocks according to the address conversion information.
Or flash EEPROM of the second memory block
Address conversion means for converting a physical address for accessing the memory device, and selecting either one of the first and second memory blocks according to the drive number specified by the host device, and selecting the selected memory block. Flash E
A memory access unit for performing read / write access to the EPROM according to the physical address converted by the address conversion unit; and a circuit board provided with the first and second memory blocks, the address conversion unit, and the memory access unit. A semiconductor disk device comprising: 2. The semiconductor disk device according to claim 1, wherein at least one of the flash EEPROMs is mounted on the circuit board via a socket for detachably mounting the flash EEPROM. . 3. The semiconductor disk device according to claim 1, wherein a spare socket for adding a flash EEPROM is further provided on the circuit board. 4. A host containing a plurality of flash EEPROMs, including a drive number for designating an access target disk drive and a logical address for addressing a disk recording medium included in the access target disk drive. A semiconductor disk device for accessing the flash EEPROM in response to a disk access request from a device, wherein first and second drive numbers that can be designated by the disk access request are respectively assigned, and each has a flash EEPROM. 1 and 2 memory blocks and at least 1 for adding flash EEPROM
Spare sockets and flash EE of said first and second memory blocks
A control unit for controlling the PROM; and a circuit board on which the first and second memory blocks, the spare socket, and the control unit are provided, wherein the control unit sets the logical address according to address conversion information. First
Or flash EEPROM of the second memory block
Address conversion means for converting a physical address for accessing the memory device, and one of the first and second memory blocks is selected according to the drive number specified by the host device, and the selected memory block Flash E
A memory access unit that performs read / write access to the EPROM according to the physical address converted by the address conversion unit, and manages the number of times of rewriting of each flash EEPROM of each of the first and second memory blocks. Flash EEPR has reached a certain number of times
Means for determining the OM as a chip to be replaced, means for copying the information stored in the chip to be replaced to the flash EEPROM of the spare socket when a new flash EEPROM is mounted in the spare socket, A semiconductor disk device comprising means for updating the address conversion information and allocating a logical address corresponding to the chip to be replaced to the flash EEPROM of the spare socket. 5. A host having a plurality of flash EEPROMs and including a drive number for designating an access target disk drive and a logical address for addressing a disk recording medium included in the access target disk drive. A semiconductor disk device for accessing the flash EEPROM in response to a disk access request from a device, wherein first and second drive numbers that can be designated by the disk access request are respectively assigned, and each has a flash EEPROM. 1 and 2 memory blocks and at least 1 for adding flash EEPROM
Spare sockets and flash EE of said first and second memory blocks
A control unit for controlling the PROM; and a circuit board on which the first and second memory blocks, the spare socket, and the control unit are provided, wherein the control unit sets the logical address according to address conversion information. First
Or flash EEPROM of the second memory block
Address conversion means for converting a physical address for accessing the memory device, and one of the first and second memory blocks is selected according to the drive number specified by the host device, and the selected memory block Flash E
A memory access unit for performing read / write access to the EPROM in accordance with the physical address converted by the address conversion unit; Means for allocating an extended logical address space subsequent to the logical address space of the first or second memory block to the memory address space of the EEPROM.