JPH0775406B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a solid-state image pickup device equipped with a CCD solid-state image pickup device and equipped with electronic exposure control means.

(B) Conventional technology In an image pickup device such as a television camera using a CCD solid-state image pickup device, it is considered to electronically perform automatic exposure control by utilizing the operation principle of CCD.

For example, in JP-A-63-24764, in the frame transfer type CCD solid-state imaging device, the photoelectric transfer period in the middle of the photoelectric conversion period for each vertical scanning period is defined as the reading and transferring direction of the photoelectric charges accumulated in the light receiving unit until then. An exposure control unit is shown which transfers and discharges in the opposite direction and accumulates photocharges only during the remaining photoelectric conversion period. According to such an exposure control means, the reverse transfer timing of the photocharge is variably set according to the subject brightness,
The optimal exposure state can be obtained by controlling the expansion and contraction of the photoelectric conversion period.

However, in the above-described exposure control means, the amount of change in the reverse transfer timing in one step is uniform, and the expansion and contraction of the photoelectric conversion period is performed in fixed period units. Then the rate of change will be different. For example, if the photoelectric conversion period is shortened by 8H (H is one horizontal scanning period), the photoelectric conversion period is shortened by 10% when it is 80H, but is reduced by 50% when it is 16H. Become. Therefore, the rate of change in the level of the image signal obtained from the solid-state image sensor becomes uneven,
The playback screen becomes difficult to see.

Therefore, the applicant of the present application has proposed a solid-state imaging device which controls the exposure by expanding and contracting the photoelectric conversion period at a constant rate.
I am proposing to the issue. The structure is shown in FIG.

In the figure, a frame transfer type CCD solid-state image pickup device (10) comprises an image pickup section (11), a storage section (12) and a horizontal transfer section (13). The image charges obtained by photoelectric conversion are temporarily transferred and stored in the storage unit (12) in units of one screen, and the image signal Y (t) is transferred in units of one scanning line in each horizontal scanning period via the horizontal transfer unit (13). Is output as. Then, the image signal Y (t) that is continuous for each screen is sampled and held by the signal processing circuit (1),
It is output to the outside after being subjected to processing such as gamma correction.

The drive circuit (20) pulse-drives the CCD (10), and the image pickup section (11) has a read clock φ for reading charges.
_F or a discharge clock φ _B for discharging charges is supplied from the read clock generation circuit (21) or the discharge clock generation circuit (22), respectively. Further, the storage clock φ _S is supplied from the storage clock generation circuit (23) to the storage section (12), and the output clock generation circuit (24) is supplied to the horizontal transfer section (13).
From the output clock φ _H. Each of these clock generation circuits (21) (22) (23) (24) is created based on a basic clock from the same oscillation source, and the horizontal scanning signal HD and the vertical scanning signal VD are also generated based on this basic clock. can get.

Then, a read timing signal FT having a read pulse at a specific timing of the blanking period of the vertical scanning signal VD is input to the read clock generation circuit (21), and a CCD (10) is supplied to the discharge clock generation circuit (22). Ejection timing signal BT in which the ejection pulse is set at the timing according to the exposure amount of
Is entered.

Subsequently, a circuit configuration for producing the discharge timing signal BT will be described.

The image signal Y (t) obtained from the CCD (10) is integrated in the vertical scanning period unit by the integrating circuit (2) and input to the determination circuit (30) as the exposure amount signal L, and the first and second comparators are provided. (31) and (32) are compared with the reference values Lmax and Lmin, respectively. These reference values Lmax, Lmin correspond to the upper and lower limits of the proper exposure amount range of the CCD (10), and these reference values Lmax, Lmin
When there is an exposure amount signal L between them, the proper exposure state is obtained. The comparison results of the comparators (31) (32) are stored in the flip-flops (33) (34) at the read drive timing corresponding to the vertical scanning period. Therefore, the output of both flip-flops (33) (34) becomes 2-bit data,
Indicates one of "0,0", "1,0" and "1,1". Ie 2
In the bit data, "0,0" represents L≥Lmax "1,0" represents Lmax> L≥Lmin "1,1" represents Lmin≥L. Then, the decoder (35) converts each data “0,0”, “1,0” and “1,1” into an “exposure suppression signal”,
Decode as "exposure fixed signal" and "exposure promotion signal",
For the data "0,0", the expansion signal OPEN during the photoelectric conversion period
Is output, and the shortened signal CLOSE is output for the data “1,1”.

The discharge timing generation circuit (40) counts up according to the expansion signal OPEN and counts down according to the shortening signal CLOSE. The output of the up / down counter (41) is converted into predetermined binary data. Decoder (42) to decode, clock CK with a constant cycle
The step counter (43), which comprises a step counter (43) for counting the number of times, a decoder (42) and a comparison circuit (44) for detecting the coincidence of outputs of the step counter (43).
The discharge timing signal BT having the discharge pulse is output at the timing when the output of the output coincides with the output of the decoder (42). Therefore, in the case of a 4-bit configuration, the up / down counter (4
1) stores the step numbers S _{0 to} S ₁₅ when the vertical scanning line period is divided into 16 steps, and the decoder stores 4-bit binary data corresponding to the step numbers S _{0 to} S ₁₅ . The binary data will be described later in detail. On the other hand, the step counter (43) is reset at each read timing and counted up by the clock CK having 16 pulses per vertical scanning period. And
When the output of the two-step counter (43) matches the output of the decoder (42), the comparison circuit (44) generates a discharge pulse. According to the above configuration, the up / down counter (41)
The photoelectric conversion period is extended at a constant rate each time is counted up, and the photoelectric conversion period is extended at a constant rate each time is counted down.

Table 1 shows the output of the up / down counter (41) and the output of the decoder (42) corresponding to each step number when the rate of change in the photoelectric conversion period is set to 3/4 (in the case of shortening).

In this table, the photoelectric conversion period E is shown in percentage with reference to the time of step S ₀ . The 4-bit binary data output from the decoder (42) has 16 vertical scanning periods.
Divided, the difference in each step are selected data as a minimum, when the photoelectric conversion period is shortened, the output of the decoder as in step S ₉ to S ₁₂ variation becomes small (42) There are cases where it does not change. For this, the number of bits of the step counter (43) is increased and the decoder (42) is increased.
A constant rate of change can be obtained at each step by increasing the number of output bits of.

(C) Problems to be Solved by the Invention However, in order to make the rate of change in the photoelectric conversion period more uniform, increasing the number of bits of the step counter (43) increases the number of gates of the decoder (42). As a result, the circuit scale increases.

Further, since the discharge timing is determined based on the data set in the decoder (42) in advance, it is necessary to change the setting of the decoder (42) in order to change the change rate once set.
Complicated operation is required.

Therefore, an object of the present invention is to provide a solid-state imaging device in which the discharge timing generation circuit (40) can be simplified and the change rate of the photoelectric conversion period can be easily changed.

(D) Means for Solving the Problems The present invention has been made to solve the above-mentioned problems.
The features are that a solid-state image sensor for photoelectrically converting a received image to obtain image information, a drive circuit for discharging and driving the photoelectrically converted charges of the solid-state image sensor, and a read drive for the image information. A determination circuit for determining whether or not it is within the proper exposure range of the solid-state image pickup device, and based on the comparison result of this determination circuit, the charge discharge drive timing and the charge read drive timing of the drive circuit are set to set the timing between the two timings. A solid-state imaging device comprising: a timing control circuit for controlling expansion / contraction of an effective photoelectric conversion period, wherein the timing control circuit has an effective photoelectric conversion period of 1 / n (n is an integer) of the effective photoelectric conversion period in one step. The purpose is to extend or shorten the period.

(E) Operation According to the present invention, the data designating the charge discharge driving timing is calculated for each step, and the photoelectric conversion period is extended or shortened at a constant rate for each step. Of the photoelectric conversion period is variably set according to the setting of, and more specifically, the setting of the division value for dividing the data.

(F) Example An example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the solid-state imaging device of the present invention. In this figure, the CCD (10), the drive circuit (20) and the decision circuit (30) have the same construction as in FIG. 4, and the same parts are designated by the same reference numerals.

A feature of the present invention is that when the exposure amount of the image signal Y _(t) obtained from the CCD (10) is larger than the upper limit of the proper exposure range of the CCD (10), the effective photoelectric conversion period is 1 / of that period.
n (n is an integer) is shortened as one step, and conversely, when it is smaller than the lower limit of the proper exposure range, the effective photoelectric conversion period is extended by 1 / n of that period as one step.
That is, the timing control circuit (50) uses the step data S _X that specifies the timing of charge discharge drive by the horizontal scanning line number.
(X is a positive integer) A data hold circuit (5
1), a division circuit that calculates 1 / n of step data S _X (5
2), an arithmetic circuit (53) for calculating the sum or difference of the division result S _X / n of the division circuit (52) and the step data S _X , a step counter (54) and operation for counting down by the horizontal scanning signal HD. It is composed of a comparison circuit (55) which detects the coincidence of the outputs of the circuit (53) and the step counter (54) and generates an ejection pulse. When the expansion signal OPEN of the photoelectric conversion period is input from the decoder (35), the arithmetic circuit (53) adds both data and sets the next step data S _{X + 1} as S _X + S _X.
/ n is output, and when the shortened signal CLOSE is input, the division data S _X / n is subtracted from the step data S _X to obtain the next step data.
Outputs S _X −S _X / n as S _{X + 1.} Operation circuit (53)
Is compared with the output of the step counter (54) by the comparison circuit (55) and is stored again in the data hold circuit (51). When neither the expansion signal OPEN nor the shortening signal CLOSE is input from the decoder (35),
The arithmetic circuit (53) outputs the step data S _X as it is without performing addition and subtraction.

Therefore, the data compared with the output of the step counter (54) in the comparison circuit (53) changes 1 / n in 1 step in accordance with S _{X + 1} = S _X ± S _X / n. According to the data S _{X + 1, the} photoelectric conversion period changes in steps of 1 / n period.

For example, if n = 8 is set when the photoelectric conversion period is 64H (H is one horizontal scanning period), the photoelectric conversion period is extended or shortened to 72H or 56H in one step. Where 72H
When is shortened by 1/8 again, it becomes 63H, and it does not return to the previous 64H. Therefore, the photoelectric conversion period can be any length (1H unit).

As shown in FIG. 2, the division circuit (52) is composed of a shifter that shifts to the lower bit of the sample data S _X , and the division value n is determined according to the number of bits to be shifted. That is, the sample data S _X is shifted by m bits in the lower direction, and the upper bits except the lower m bits are taken out to obtain the division data S _X / 2 ^m (m is an integer). For example, to obtain 1/2 for 8-bit data "10110010", shift 1 bit downward to "01011001".
When 1/8 is obtained, 3 bits are shifted in the lower direction to “00010110”. However, the lower m bits after the shift are ignored as the remainder of the division.

Therefore, the sample data S _X is, for example, “10110010”,
If n = 8, the next sample data S _{X + 1} is “11001000”
(Extended photoelectric conversion period), "10011100" (shortened photoelectric conversion period), or "10110010" (fixed photoelectric conversion period).

In the above division circuit (52), when the step data S _X is smaller than the division value n, the division data becomes "0" and the timing control circuit (50) does not operate. The division circuit (52) is configured to output the lower bit as "1". For example, the division circuit (5
It is sufficient to replace the inversion of the logical sum of all output bits in 2) with the least significant bit.

FIG. 3 is a block diagram showing the configuration of the timing control circuit of another embodiment. In this figure, a data hold circuit (51), a comparison circuit (55) and a step counter (54)
Are the same as those in FIG. 1 and are designated by the same reference numerals. The division circuit (56) divides the step data S _X input from the data hold circuit (51) by the division n, inputs the division data S _X / n to the selection circuit (58), and also the inverting circuit (57). To enter. Inverting circuit (57) is intended to create a negative division data -S _X / n obtained by inverting the positive and negative with respect to the division data S _X / n, the lowest inverts each bit of the division data S _X / n It is configured to add "1" to the bit. For example, “11101010” is obtained for 8-bit data “00010110”. The selection circuit (58) selects the positive division data S _X / n or the negative division data -S _X / n according to the output of the decoder (35) and supplies it to the arithmetic circuit (59). The arithmetic circuit (59) adds the data S _X / n or -S _X / n selected by the selection circuit (58) and the step data S _X. Then, the addition result is input to the comparison circuit (55) and stored again in the data hold circuit (51). That is, the expansion signal of the photoelectric conversion period
When OPEN is input to the selection circuit (58), the positive division data S _X / n
Is selected and S _X + S _X / n is obtained as the next step data S _{X + 1. When} the shortened signal CLOSE is input, the negative division data −S
_X / n is selected and the next step data S _{X + 1} is S _X −S _X /
n is obtained. For example, the sample data S _X is "10110010"
If n = 8, the positive division data S _n / 8 becomes “0001011
0 ”, the negative division data −S _n / 8 is“ 11101010 ”, so the step data S _{X + 1} is“ 110010 ”with respect to the expansion signal OPEN.
00 ”, and the step data S for the shortened signal CLOSE
_{X + 1} becomes "10011100". Therefore, the arithmetic circuit (5
Match the output of 3).

On the other hand, the decoder (35) outputs the expansion signal OPEN and the shortening signal CLOS.
When neither E is output, the selection circuit (58) selects neither the positive division data S _X / n nor the negative division data −S _X / n. Output S _{X as} is.

In the arithmetic circuits (53) (58), the arithmetic result may be larger than the maximum output value. In such a case, the output is the maximum value, that is, all the output bits are "1". Is set to.

Although the 8-bit configuration is illustrated for the above embodiment, the 8-bit configuration can count only from 0 to 255, and the horizontal scanning line (26
2.5 bits) cannot be counted, so 9 bits are required. With such a configuration, the charge discharge driving timing can be limited to any timing during the vertical scanning period. Further, when the photoelectric conversion period is narrowed down from the maximum to the minimum, when n = 8, it reaches in about 30 steps (about 0.5 seconds).

(G) Effect of the Invention According to the present invention, the photoelectric conversion period can be always extended or shortened at a constant rate, and the rate can be easily changed, and smoother exposure control can be realized. . Further, since the data designating the timing of discharging the electric charges is obtained by the calculation, the decoder having a large number of gates is not required, and the increase in the circuit scale can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a solid-state image pickup device of the present invention, FIG. 2 is a diagram for explaining a divider circuit, FIG. 3 is a block diagram showing a configuration of a timing control circuit of another embodiment, and FIG.
The figure is a block diagram showing a conventional solid-state imaging device. (10) …… CCD solid-state image sensor, (11) …… Imaging unit, (1
2) ... storage section, (13) ... horizontal transfer section, (20) ... drive circuit, (21) ... read clock generation circuit, (22) ...
Discharge clock generation circuit, (23) …… Accumulated clock generation circuit, (24) …… Output clock generation circuit, (30) …… Judgment circuit, (31) (32) …… Comparator, (33) (34) ...... Flip-flops, (35) …… Decoders, (40) (50) ……
Timing control circuit, (41) …… up / down counter, (42) …… decoder, (43) (54) …… step counter, (44) (55) …… comparator circuit, (51) …… data hold circuit , (52) (56) …… Division circuit, (53) (5
9) …… Operation circuit, (57) …… Inversion circuit, (58) …… Selection circuit.

Claims (1)

[Claims] 1. A solid-state image sensor for photoelectrically converting a received image to obtain image information, a drive circuit for driving the photoelectric conversion charge of the solid-state image sensor to discharge and then reading out the solid-state image sensor. A judgment circuit for judging whether or not it is within the proper exposure range of the element, and based on the judgment result of this judgment circuit, the charge discharge driving timing and the charge reading driving timing of the driving circuit are set, and the effective photoelectric voltage between both timings is set. A solid-state imaging device, comprising: a timing control circuit for controlling expansion / contraction of a conversion period, wherein the timing control circuit stores a step data S _X (X is an integer) for determining a charge discharge driving timing, in response to determining times of determination results, adding or subtracting the division data S _X / n obtained by dividing the step data S _X by divisor n with respect to the step data S _X S in a new step data S _{X + 1} Rukoto _X + S _X / n or S _X -
An arithmetic circuit for calculating S _X / n, a counter circuit that is counted in a horizontal scanning period within a vertical scanning period, and a charge for the driving circuit by detecting a match between the output of the arithmetic circuit and the output of the counter circuit. A solid-state imaging device, comprising: a comparison circuit that gives an instruction for ejection driving.