JPH0775085A - Picture transmission control system - Google Patents

Abstract

PURPOSE:To provide a picture transmission control system in which the transmission of picture data such as animation data whose data amounts are large through a digital transmission line can be easily attained at a low cost. CONSTITUTION:In the picture transmission control system for controlling the transmission of the picture data through the digital transmission line, the reading processing of two-plane frame memories 114 and 115 for storing digital picture data and a writing processing in a digital transmission control part 121 in an interface part 4 of the digital transmission line are complementarily operated, the number of frames per unit time of the reading processing is made smaller than the number of frames per unit time of the writing processing, the data in the frames are divided into packet units of the maximum length which can be handled by the digital transmission control part 121, and the entire packets constituting one frame are DMA-transferred in one reading processing period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image transmission control system for controlling the transmission of image data through a digital transmission line such as a LAN (local area network).

[0002]

2. Description of the Related Art In image transmission of image data obtained by a CCD camera device or the like, the image data is transmitted through a digital transmission interface (hereinafter referred to as digital transmission interface).
A transmission system is known in which image data is transmitted through a digital transmission line such as a LAN (local area network) via the F.) and the digital transmission line is used. Since the amount of this image data is usually large, it is not possible to send the image data obtained by the camera device to a digital transmission line such as a LAN without changing the obtained data amount. It may be difficult in terms of. For example, when a moving image or a quasi-moving image is handled as image data, the amount of data becomes larger than that of a still image, which may hinder sufficient transmission of data required to express the moving image or the quasi-moving image. Therefore, conventionally, the amount of data to be transmitted has been reduced by compressing and encoding image data.

FIG. 12 is a block diagram of a conventional digital transmission I / F provided in a camera device. Note that FIG. 12 shows an example in which a LAN is used as a digital transmission line.

In FIG. 12, reference numeral 301 denotes a CCD solid-state image sensor, and analog image data output from the CCD solid-state image sensor 301 is CCD solid-state image sensor 301.
An NTSC system (National Television System) by a CCD control unit 302 for controlling the
The image signal is output as an em committee image signal and input to the A / D conversion unit 304. At this time, CC
The D control unit 302 is the CCD scan timing generation unit 3
It is driven in synchronism with the timing of the NTSC system supplied from 03.

A conventional digital transmission I / F has a compression encoder 305 for compressing and encoding image data, and an A / D converter 304 converts a video signal converted from an analog value to a digital value. , This compression encoder 305
Is compressed and encoded in the frame memory unit 30.
At 6, the data is stored for each frame. The image data of one frame stored in the frame memory unit 306 is
The data is transferred to the LAN control LSI 308 in synchronization with the control timing supplied from the frame memory control unit 307. The image data transferred to the LAN control LSI 308 is the LA stored in the LAN control LSI 308.
In accordance with N communication procedure (hereinafter referred to as protocol), L
Line control driver 30 for driving an AN line
9 and the LAN line connection terminal 311
Sent on N lines. Incidentally, 310 is an L for LAN control
It is a local MPU unit for controlling the SI 308.

[0006]

However, in the above-mentioned conventional image transmission control, since the capacity of the digital transmission line is limited, image data having a large data amount such as moving image data is transmitted through the digital transmission line. However, as a means for solving this problem and making the image data into a data amount suitable for the transmission capacity of the digital transmission line, the conventional digital transmission I /
A processing method of compressing and encoding image data in F is known, but the compression encoder of this conventional processing method has a complicated structure, which complicates the overall configuration of the apparatus for image transmission control, resulting in cost reduction. Also has the problem of rising.

Therefore, the present invention solves the above-mentioned problems of the conventional image transmission control, and in the image transmission control, transmission of image data having a large data amount such as moving image data through a digital transmission path is simple and low cost. It is an object of the present invention to provide an image transmission control method that can be realized by

[0008]

SUMMARY OF THE INVENTION The present invention relates to an image transmission control system for controlling transmission of image data by a digital transmission line, and a digital image capable of writing and reading operations on an interface section of the digital transmission line. Provided with a two-sided frame memory for data storage,
The above-mentioned object is achieved by performing the write operation and the read operation of the two-sided frame memory complementarily and making the number of write and read frames different per unit time, thereby converting the transfer rate of digital image data. To do.

Further, according to the present invention, in an image transmission control system for controlling transmission of image data by a digital transmission line, a reading process of a frame memory for storing digital image data in an interface section of the digital transmission line, and a digital processing By performing the write processing to the transmission control unit by the direct memory access transfer, and by performing the transfer size of the data in the direct memory access transfer in the unit of the maximum length packet which the digital transmission control unit can handle, the above-mentioned object is achieved. To achieve.

According to the present invention, in an image transmission control system for controlling the transmission of image data by a digital transmission line, a reading process of a two-sided frame memory for storing digital image data in an interface section of the digital transmission line. And the writing process to the digital transmission control unit is performed complementarily, the number of frames per unit time of the reading process is made smaller than the number of frames per unit time of the writing process, and the data included in the frame is set by the digital transmission control unit. The above object is achieved by dividing the packet into units of the maximum length that can be handled and transferring all the packets constituting one frame during direct read access.

In the present invention, the digital transmission line is a transmission line having a function of transmitting digital data, and for example, a local area network (LAN) can be adopted. Further, in the present invention, the interface section of the digital transmission line has a function of performing various data conversion processes for transmitting the image data through the digital transmission line, and the digital transmission control section follows the protocol defined by the digital transmission line. It has a function of controlling data transmission.

[0012]

According to the present invention, the interface section of the digital transmission line is provided with a two-sided frame memory for storing digital image data capable of writing and reading operations, and the two-sided frame memory writing operation. And the reading operation are performed complementarily, and the transfer rate of digital image data is converted by changing the number of frames per unit time of writing and reading in each writing operation and reading operation, and image data with a large amount of data is converted. Can be made to correspond to the transmission speed of the digital transmission line.

Further, according to the present invention, the reading process of the frame memory for storing digital image data in the interface unit of the digital transmission line and the writing process to the digital transmission control unit are performed by direct memory access transfer. At the same time, the transfer unit in the direct memory access transfer is set to the maximum length packet unit that can be handled by the digital transmission control unit, which enables efficient transfer even for image data having a large data amount. .

Further, the reading processing of the two-sided frame memories for storing digital image data in the interface section of the digital transmission path and the writing processing to the digital transmission control section are complementarily performed, and the reading processing per unit time is performed. The number of frames is made smaller than the number of frames per unit time in the writing process, the image data of the frame is divided into packet units of the maximum length that the digital transmission control unit can handle, and all packets constituting one frame are read during one reading process period. Direct memory access transfer is performed to enable image data having a large data amount to be handled by digital transmission.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings, but the present invention is not limited to the embodiments.

[Structure of Embodiment] First, the structure of an embodiment for carrying out the image transmission control method of the present invention will be described with reference to FIG.

In FIG. 1, the image data output from the CCD camera 101 is converted into a digital signal in the digital camera section 10 shown by the alternate long and short dash line in the figure, the data amount is reduced, and digital transmission such as LAN is performed. A process for riding on a road (hereinafter, LAN will be described as an example) is performed. The digital camera unit 10 receives the image data from the CCD camera 101 and outputs an analog signal of NTSC system, and the CCD input processing unit 1 and the input analog signal image data in digital units of one pixel. A / for converting to a signal
From the D conversion unit 2, the frame memory control unit 3 for reducing the image data to be transmitted, the circuit control unit 4 for sending the image data to the LAN, and the local MPU unit 5 for controlling the entire apparatus. Composed.

The detailed configuration of the digital camera section 10 will be described below.

(CCD input processing section 1): The CCD input processing section 1 is a section having a function of inputting image data from the CCD camera 101 and outputting an analog signal of NTSC system. CCD control board 102, CCD driver 103, CCD scan
Timing generation unit 104 and sample hold unit 105
And a low-pass filter (hereinafter referred to as LPF) 106
And a clock generator 110.

The CCD driver 103 supplies the CCD scan / timing generator 104 with the NTSC system timing to drive the CCD control board 102, and the CCD solid-state image sensor 101 synchronizes with the analog of each pixel in synchronization with the NTSC system timing. Output the value. This CCD control board 10
The analog signal corresponding to each pixel output from 2 is sampled and temporarily held by the sample hold unit 105, and then limited by the LPF 106 to a signal component only in the video band (for example, 4.5 MHz). Is supplied to. The CCD scan timing generation unit 104 supplies control timing to the entire CCD input processing unit 1 including the CCD driver 103 and the sample hold unit 105, and receives the reference clock from the clock generator 110.

(A / D converter 2): The A / D converter 2 is
The pedestal clamp unit 107 and the A / D conversion circuit 108 have a function of converting the image data of the input analog signal into a digital signal of a pixel unit.
And the timing correction unit 11.

In the pedestal clamp section 107,
The "0 level" of the analog signal of the image data that has passed through the LPF 106 is taken out and fixed, and this "0 level" is set as the pedestal level of the NTSC signal at the time of A / D conversion. NTS passed through the pedestal clamp 107
The C-system video signal is quantized into, for example, 8 bits in the A / D conversion circuit 108, and is converted into 8-bit digital B / W.
It is output as a signal. The sampling interval in this A / D conversion circuit 108 is the CCD of the CCD input processing unit 1.
It is set by the sampling clock supplied from the scan / timing generation unit 104 and corrected by the timing correction unit 11 to have a one-pixel width.

(Frame / memory control section 3): The frame / memory control section 3 is a section having a function of efficiently transmitting the image data to be sent to the transmission path. As a configuration for this highly efficient transmission, A frame memory A114, a frame memory B115 with a toggle structure, and a frame memory
A memory controller 113, a V & H eliminator 112,
A D flip-flop (hereinafter referred to as DF / F) 109 is used.

In order to efficiently transmit image data according to the image transmission control method of the present invention, the amount of data is reduced and the number of transmission frames per unit time is increased. In the frame memory control unit of the present invention, as a process for reducing the amount of data, (a) frame dropping performed by speed conversion of writing timing and reading timing of image data by the frame memory A114 and the frame memory B115 having a toggle structure. As the processing and (b) the sub-sampling processing of the pixel by the V & H eliminator 112, and the processing of increasing the number of transmission frames per unit time, (c) the circuit control unit of the LAN of the image data in the frame memory For the transfer to the RAM built in 4, the burst DMA transfer processing is performed in units of long packets in LAN control. Hereinafter, the processing will be described in order.

(A) First, a frame with a toggle structure
The configurations of the memory A 114 and the frame memory B 115 and the frame dropping process will be described. FIG. 2 is a block diagram of a frame memory having a toggle structure of the image transmission control system of the present invention. In the figure, the frame memories of the toggle configuration are frame memory A114 and frame memory B1.
Image data digitized via the DF / F 109 is input in parallel to each of the frame memory A 114 and the frame memory B 115, and the write signal WR (A) and the writing are performed. It is written by the signal WR (B). The image data stored in the frame memory A 114 and the frame memory B 115 are read by the read signal RD (A) and the read signal RD (B) and input to the circuit control unit 4. The write signal WR (A) and the read signal RD (A) are signals for the frame memory A 114, and the write signal WR (B) and the read signal R
D (B) is a signal to the frame memory B115.

FIG. 3 is a block diagram of the frame memory control unit 113, which is an image data transfer request signal TRFPU.
Field identification signal F of LSE and NTSC image signals
LD is input to write signals WR (A), WR (B),
And read signals RD (A) and RD (B). The frame memory control unit 113 uses the DF / F
113-1 and DF / F 113-2, and NOT circuit 113
-3. The DF / F 113-1 inputs the image data transfer request signal TRFPULSE via the NOT circuit 113-3 to the clock terminal CLK, and the DF / F 11-1.
A read signal RD (A) from the inverted output terminal 3-1 (hereinafter referred to as Q *) to the frame memory A 114 and an inverted output of the read signal to the frame memory B 115 (hereinafter referred to as RD (B) *). ) And D
Input to the terminal. Further, the DF / F 113-2 inputs the field identification signal FLD of the image signal of NTSC system to the clock terminal CLK, and the DF / F 113-1 to the D terminal.
Input Q output of DF / F113-2 and write signal WR (A) from frame output A114 to frame memory A114
Output (hereinafter, referred to as WR (A) *) and a write signal WR (B) to the frame memory B115.

The frame memory A114 and the frame memory A115 having a toggle structure are connected to the write signal WR.
(A), WR (B), and read signals RD (A), R
With D (B), the write operation and the read operation are alternately performed, and the speed conversion is performed by delaying the read timing as compared with the write timing.
Out of the NTSC signals input at 30 frames / sec, for example, while writing image data for 5 frames, only one frame is output to perform frame dropping processing, thereby converting the transfer rate.

(B) Next, the configuration of the V & H eliminator 112 and the pixel sub-sampling process will be described. When writing to the frame memory, NTSC
In the case of a CCD device of the system, pixel data of about 250,000 pixels (510H × 792V) is generated per frame. Therefore, the amount of data is too large and the amount of information is too large for the LAN.
It is difficult to transmit a digital moving image by the control block. Therefore, the V & H eliminator 112 provided in the frame memory control unit 113 thins out and deletes the pixel data in the vertical and horizontal directions of the NTSC signal to a required size and deletes the number of display pixels. This process is performed by sub-sampling the pixel data to 1
This is performed by thinning out pixels forming a frame and inputting and writing the thinned out data into a frame memory. The pixels can be thinned out in the vertical and horizontal directions of the frame, the degree of thinning can be set arbitrarily, and the number of display pixels can be changed according to the degree.

The DF / F 109 is, for example, a D flip-flop for latching 8-bit digital data, and the timing of inputting the image data digitized by the timing signal from the timing correction unit 111 to the frame memory. Are synchronized.

(C) Next, a high-speed transfer process by burst DMA transfer in units of long packets will be described. In the following description, an Arcnet LA will be used as a LAN.
N will be described as an example.

In the transmission via the LAN, the data to be transmitted is sent to the LAN transmission line through the LAN control 116 in the circuit control unit 4 in FIG. In FIG. 1, data is transferred from the frame memory A or the frame memory B to the RAM 119 inside the LSI of the LAN control 116.
Data to be transferred to the LAN transmission path, and then to increase the number of transmission frames per unit time, the data transfer time from this frame memory to the RAM 119 should be shortened as much as possible. It is necessary to increase the amount of data transferred in a unit time. The LAN control 116 is, for example, an Arcnet LA that operates according to a token passing protocol.
A local MPU 11 composed of an N control LSI
8 and a RAM 119.

Therefore, in the image transmission control system of the present invention, (c-1) LA for controlling transmission by LAN.
Packet processing of image data is performed using the maximum data packet length that can be processed by the LSI of N control 116, and (c
-2) In the packet processing of the image data, data transfer is performed between the frame memory and the LSI of the LAN control 116 by direct memory access transfer (hereinafter referred to as DMA transfer).

Regarding the packet processing of the image data by the maximum data packet length of (c-1), referring to FIG. 5 for explaining the image data amount and FIG. 6 for explaining the image data packet processing. explain. Normally, packet transfer requires a certain amount of transfer processing time for each packet transfer, and in order to transfer a certain amount of data,
The smaller the number of packets to be transferred, the shorter the time required for the entire transfer.

In FIG. 5, for example, one frame is 10 vertically.
If each pixel is represented by 8 bits and the number of pixels is 0 pixels and 100 pixels horizontally, the data amount of one frame is 100
× 100 × 8 = 80000 bits (= 10000 bytes). When the data amount of one frame is transmitted in packet units, for example, a LAN of Arcnet LAN
Among the transfer modes of the LSI of the control 116, the maximum packet length that can be handled in the long packet mode is 512 bytes, of which 12 bytes are used as the header part and the remaining 500 bytes are the image data storage area. Hereinafter, this packet is referred to as a long packet. If all of the image data storage area is used to efficiently transmit the image data, the number of long packets required to transmit the image data amount of 10,000 bytes is (image data amount) / (1 packet) The amount of image data per unit) = 10,000 bytes / 500 bytes = 20 packets. Therefore, 100 pixels vertically and 100 pixels horizontally are 1
The image data as a frame can be transferred by a long packet of 20 packets, and the transfer by the 20 packets is the data transfer processing of the shortest time by the LSI of the LAN control 116.

Next, the (c-2) frame memory and L
The DMA transfer between the LSIs of the AN control 116 will be described. The DMA transfer is to directly access the memory and directly perform the read or write operation from the memory. The program specifies the start address of the memory,
The transfer process can be performed at a higher speed than program transfer, which transfers data by a move instruction. In the present invention, the frame memory and the LAN control 116 LSI
Between the frame memory reading process and LA
By performing the write processing of the N control 116 to the LSI by DMA transfer, the efficiency of image data is improved.

Burst D in units of long packets according to the present invention
When the processing of high-speed transfer processing by MA transfer is evaluated by the number of frames Fn (frame / second) per unit time,
The Fn is represented by the following formula.

Fn = 1 / [{(n + 1) × 28.2 (μsec) + n (141.0 (μsec) + 4.4 × B)} × Pl / 2 + (500 × Pl × Td)] (1 In the above equation, Pl is the number of transfer packets of one frame, B is the number of bytes constituting the image packet, and Td is the DMA transfer time per byte of the image data (2 in this embodiment).
00 nsec), n is the number of connected cameras.

In the above equation, when the number of display pixels is 10,000 pixels and transfer is performed in 20 packets, 38.4 per second.
Frames can be transferred. This transfer capability is sufficient for transmitting moving image data.

(Circuit control section 4): The circuit control section 4 is a section having a function of transmitting the image data read from the frame memory by DMA transfer to the image switching apparatus section and sending it to the LAN. The control unit 116 and the media driver 117 are included. The LAN controller 116 uses the DMA from the frame memories 114 and 115.
The image data read out by the transfer is stored in the built-in RAM 119 in units of long packets, and further transmitted to the image switching device section (not shown) via the media driver 117. The LAN control unit 116 is used in the long packet mode, and is 500
Process with bytes. Also, the media driver 117
Drives the transmission medium transmitted from the LAN control unit 116. For example, when an RS-485 insulation type media driver is used as the media driver, a signal in the NRZ code format or the like is transmitted to the RS-485 differential type. Convert to output and drive to transmission medium via pulse transformer.

The LAN control section 116 is formed in the LAN control LSI 121 together with a local MPU 118 and a RAM 119 which will be described later.

(Local MPU 5): Local MPU
The unit 5 is a unit having a function of controlling the entire device such as parameter setting for each LSI, DMA transfer control, and interrupt control, and includes a local MPU 118 and a built-in RAM.
119, an external ROM 120, and peripheral control logic (not shown).

Since transfer control of moving image data is performed by DMA transfer control to the LAN control unit 116,
The throughput of this device can be set independently of the processing speed of the local MPU 118.

[Operation of the Embodiment] Next, the operation of the embodiment of the present invention will be described with reference to FIGS. 1, 2, 3 and 4, 5. FIG. 4 is a time chart for explaining the operation of the frame memory of the present invention, and FIG. 7 is a packet DMA of the present invention.
It is a time chart explaining a transfer process.

CCD scan / timing generator 104
C synchronized with the timing of the NTSC system supplied from
The analog value of each pixel is output from the CD solid-state image sensor 101 and the CCD control board 102. In FIG. 4, FL
D is a field identification signal of an NTSC video signal, and represents the time when the image data of the odd field is valid when FLD is in the high state, and F
When the LD is in the low state, it represents the time when the image data of the even field is valid, and one frame is composed of this odd field and the even field. In the figure, fifteen frames F0 to F15 are displayed, and image data of an odd field (hatched part) and an even field are shown in the CCD part.

The analog signal corresponding to each pixel is input to the sample hold unit 105, sampled by the sample hold signal from the CCD scan timing generation unit 104, and the sample value is temporarily held. After that, the sampled value is limited to the signal component only in the video band (4.5 MHz) by the LPF 106 and supplied to the pedestal clamp circuit 107. The pedestal clamp circuit 107 is composed of, for example, an analog switch, an operational amplifier, a voltage level fixing capacitor, and the like, and the “0 level” of the analog signal at the time of A / D conversion by the A / D converter 108 is the pedestal of the NTSC signal.・ Fix to the level.

The NTSC video signal that has passed through the pedestal clamp circuit 107 is quantized into, for example, 8 bits in the A / D conversion circuit 108, passes through the DF / F 109 as an 8-bit digital B / W signal, and is then timed. Is adjusted and then supplied to the frame memory 114 and the frame memory 115.

(Operation of Frame Memory): Next, the operation of the frame memory will be described. In the present embodiment, it is assumed that the image data of only the odd field (hatched portion) is handled, the state of the frame memory A is shown in FRMMEM (A), and the state of the frame memory B is shown in FRMMEM (B). ).

In FIG. 4, first, the frame memory A
The write field WR (A) of 1 writes the odd field in the frame F0 to the frame memory A114. The image data written in the frame memory A114 is represented by "W0" in the figure. Then L
When the image data transfer request signal TRFPULSE to the inside of the LSI of the AN control 116 is generated, the write operation and the read operation of the frame memory A114 and the frame memory B115 are reversed, and RD (A), RD (B), WR
The control signals of (A) and WR (B) are inverted, the frame memory A is in the read mode, and the frame memory B is in the write mode. By reversing the read mode and the write mode, the frame memory B becomes the write mode. This mode is between frames F1 to F5 in FIG. 4, and the frame data of the odd field during this mode is written in the frame memory B as W1 to W5. In this writing, the capacity of the frame memory B is a capacity for storing only the data for the odd field of one frame, and when new data is written after the writing process, the data is written last time. The data disappears and is overwritten with new data.
Therefore, for example, when the next frame data W2 is written after the writing of the frame data W1, the previous frame data W1 is erased, and instead the frame data W1 is written.
2 is stored. Therefore, the data read when the read is performed by switching from the write mode to the read mode is the last written data.

During the same period as this period, since the frame memory A114 is in the read mode, the frame memory A114 to the R of the LAN control LSI 121 is read.
Data transfer processing is performed to the AM 119. This data transfer process is represented by the frame data R (0) of FRMMEM (A) in FIG. The data read from the frame memory A114 in the transfer process is the data W0 written in the period of F0.

In R0 in the figure, the shaded portion indicates data and the blank portion indicates a control portion for data transfer.

Next, when the transfer of the image data for one frame of the frame data R0 from the frame memory A114 is completed, the image data transfer request signal TRFPUL is sent.
SE is regenerated. Image data transfer request signal TRF
At the time when PULSE is generated, the write operation and the read operation of the frame memory A114 and the frame memory B115 are reversed in the same manner as described above. That is, the frame
Memory A 114 is in write mode and frame memory B 115 is in read mode. Since the frame memory A114 is in the writing mode, the image data of the odd field of the frame data W6 to W9 in the figure is written. During the same period as this period, the frame memory B
Since 115 is in the read mode, data transfer processing is performed from the frame memory B115 to the RAM 119 of the LAN control LSI 121. This data transfer process is represented by the frame data R (5) of FRMMEM (A) in FIG. The data read from the frame memory B115 in the transfer process is the data W5 written in the period of F5.

Therefore, in the operation of the frame memory of the present invention, the write operation and the read operation of the frame memory A and the frame memory B are inverted every time the image data transfer request signal TRFPULSE is generated, and TRFPULSE if the memory is in read mode
The last written frame data (N) before is input is read and transferred to the LAN control 116.

By the operation of this frame memory, the data transferred from the frame memory to the LAN control 116 becomes one frame for several input frames, and the frame dropping processing is performed. Therefore, even if the image data has a large amount of data such as a moving image, it can be transferred to the LAN control 116.

FIG. 4 shows a case where 5 frames are dropped into 1 frame and a case where 4 frames are dropped into 1 frame.

Further, with respect to the frame dropping processing of the frame memory, the V & H eliminator 112 can further reduce the amount of data to be handled. CCD
The control signal from the scan timing generator 104 is
The V & H eliminator 112 converts it into a control signal for sub-sampling. The number of pixels written in the frame memory by the CDD solid-state imaging device 101 is, for example, 250,000 pixels per frame (510H × 4).
92V), which is too much information and LAN
Since the transfer by the control 116 is impossible, the V & H eliminator 112 performs a process of thinning out the pixels in the vertical direction and the horizontal direction to a required size to reduce the number of pixels to be handled.

(Long Packet DMA Transfer Processing): Next, the operation of the DMA transfer processing by long packets will be described. FIG. 7 is a DM according to the long packet of the present invention.
It is a time chart of A transfer processing.

When TRFPULSE is generated, the write operation and the read operation of the frame memory A and the frame memory B are reversed, and when the frame memory is in the read mode, it is written at the end before the TRFPULSE is input. The frame data is read and transferred to the LAN control 116. In FIG. 7, the image data to be read is performed in packet units. In the embodiment of the present invention, the image data for one packet is 500 bytes (in long packet units), and the packet DMA transfer processing period is set by the control signal in the LAN control LSI 121. Transfer is done in. The next packet DMA transfer process is performed by the LAN control 116.
Is performed after the token waiting time defined by the token passing system protocol, and the image data for one packet is again packet DM in units of 500 bytes.
A transfer processing is performed.

In the present invention, since the memory is directly accessed and the transfer processing is performed in units of long packets, the transfer efficiency is improved.

By the long packet DMA transfer processing, the image data stored in the RAM 119 is sent from the LAN line connection terminal 121 to the LAN line via the media driver 117 according to the LAN control token passing protocol.

(Application Example) Next, an example in which the image transmission control system of the present invention is applied to an image monitoring system will be described. FIG. 8 is a block diagram of a conventional image monitoring system using an analog transmission system, and FIG. 9 is a block diagram of an image monitoring system using the image transmission control system of the present invention.

In FIG. 8, in the conventional analog transmission system, in order to monitor a plurality of cameras 1 to n by a CRT, power adapters 1 to n for superimposing an image signal and a power source on each camera are required. However, since the image data is sent as it is from the camera, the amount of processing becomes enormous, and it is difficult to process a digital moving image. On the other hand, in FIG. 9, in the image transmission control method of the present invention, a power adapter is not required when monitoring a plurality of cameras 1 to n by a CRT, and sub-sampling of the image data and frame dropping are performed. Processing, long packet DM
High-speed transfer is possible by processing such as A transfer, and processing of digital moving images is possible.

FIG. 10 shows a plurality of digital camera units 10.
Digital image switching device 2 for processing image data from an image
2 is a block diagram of 0, which is a line control unit including a receiver 201 and a LAN control device 202, and a local MPU including a local MPU 203, a ROM 204, and a RAM 205.
Unit, a window memory control unit including a window memory control unit 206 and window memories 207 to 212, and a display control unit.
The image data is switched to the CRT 30 under the control of the above.

FIG. 11 shows the number of frames per unit time when a plurality of cameras are connected by the image monitoring system according to the image transmission control system of the present invention. FIG. 11 is a value calculated by using the number of frames per unit time Fn (frames / second) of the high-speed transfer processing by the burst DMA transfer of the long packet unit of the present invention shown in the formula (1), Even when multiple cameras are connected,
It is possible to secure a sufficient number of frames per unit time, and it is possible to process a moving image.

The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the present invention, and these modifications are not excluded from the scope of the present invention.

[0065]

As described above, according to the present invention,
In the image transmission control, it is possible to easily and inexpensively transmit image data having a large data amount such as moving image data through a digital transmission path.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment for implementing an image transmission control system of the present invention.

FIG. 2 is a block diagram of a frame memory having a toggle structure of an image transmission control system of the present invention.

FIG. 3 is a block diagram of a frame memory control unit.

FIG. 4 is a time chart explaining the operation of the frame memory of the present invention.

FIG. 5 is a diagram illustrating an image data amount.

FIG. 6 is a diagram illustrating packet processing of image data.

FIG. 7 is a time chart of a DMA transfer process using long packets according to the present invention.

FIG. 8 is a block diagram of a conventional image monitoring system using an analog transmission system.

FIG. 9 is a block diagram of an image monitoring system according to the image transmission control method of the present invention.

FIG. 10 is a block diagram of a digital image switching device.

FIG. 11 is a table showing the number of frames per unit time when a plurality of cameras are connected in the present invention.

FIG. 12 is a block diagram of a conventional digital transmission I / F included in a camera device.

[Explanation of symbols]

 1 CCD input processing unit 2 A / D conversion unit 3 frame / memory control unit 4 circuit control unit 5 local MPU unit 10 digital camera unit 11 timing correction unit 101 CCD camera 102 CCD control board 103 CCD driver 104 CCD scan / timing generation unit 105 Sample and Hold Unit 106 Low Pass Filter (LPF) 107 Pedestal Clamp Unit 108 A / D Conversion Circuit 109 DF / F 110 Clock Generator 111 Timing Correction Unit 113 Frame Memory Control Unit 112 V & H Eliminator 114 Frame Memory A 115 Frame Frame Memory B 116 LAN control 117 Media driver 118 Local MPU 119 RAM 121 LAN control LSI

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H04N 5/00 B 5/907 B 7734-5C 7/00 7/24 H04N 7/13 Z

Claims (3)

[Claims] 1. An image transmission control system for controlling transmission of image data by a digital transmission line, wherein a two-sided frame for storing digital image data capable of writing and reading operations is provided in an interface section of the digital transmission line. .Conversion of transfer rate of digital image data by providing a memory and performing writing and reading operations of the two-sided frame memory complementarily and differentiating the number of frames per unit time of writing and reading Image transmission control method characterized by. 2. An image transmission control system for controlling the transmission of image data by a digital transmission line, comprising: reading processing of a frame memory for storing digital image data in an interface section of the digital transmission line;
Direct write processing to the digital transmission control unit
An image transmission control system characterized by performing the memory access transfer and performing the direct memory access transfer in packet units of the maximum length that can be handled by the digital transmission control unit. 3. An image transmission control system for controlling the transmission of image data by a digital transmission line, wherein the interface section of the digital transmission line reads out two frame memories for storing digital image data, and digital transmission. The writing process to the control unit is performed complementarily, the number of frames per unit time of the reading process is made smaller than the number of frames per unit time of the writing process, and the frame is the maximum length packet unit that can be handled by the digital transmission control unit. The image transmission control method is characterized in that all packets constituting one frame are transferred by direct memory access during one read processing period.