JPH0775012A - Picture display device and picture display method - Google Patents

Abstract

PURPOSE:To provide a picture display device and a picture display method capable of inexpensively performing the interpolation processing of picture signals by one memory. CONSTITUTION:An interpolation circuit 25 writes picture signals converted into digital in a D/A converter 30 in a field memory 31 by a write start signal from a clock generator 37. At this time, the clock generator 37 outputs the write start signal to the field memory 31 at a timing for completing the read of the picture signals before a write address based on the write start signal passes a read address based on a read start signal. Also, a vertical synchronization conversion circuit 38 outputs correction vertical synchronizing signals for which vertical synchronizing signals are converted into the timing faster than the output timing of the read start signal only for the fixed time. The picture signals of the field memory 31 are read based on the read start signal, multiplied with a coefficient in a multiplier 33 and the multiplier 34, then added in an adder 35, converted into analog in a D/A converter 36 and then outputted as interpolated picture signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device,
More specifically, the present invention relates to an image display device for enlarging / reducing an image in the vertical direction.

[0002]

2. Description of the Related Art In recent years, image display devices such as television receivers have been developed which enlarge and reduce images with the progress of technology.

In particular, as a method for enlarging an image, generally, an image is enlarged by increasing the circuit constant of the deflection circuit, and a method is enlarged by simply increasing the number of scanning lines. There is.

Of the above methods, the former method of changing the circuit constant of the deflection circuit is effective only for an image display device using a CRT (Cathode Ray Tube), and an image using a liquid crystal display device is used. Not applicable to display devices.

In the latter method of simply increasing the number of scanning lines, there is no problem when the display screen is magnified by an integral multiple, but when the display screen is enlarged by a magnification other than the integral multiple, There is a problem that an enlarged image is displayed unnaturally by simply increasing the number of scanning lines.

Therefore, as shown in FIG. 4, an image display device using a conventional liquid crystal display device is provided with an interpolation circuit 1 for interpolating a video signal in accordance with an enlargement magnification. The analog video signal is converted into a digital video signal by the A / D converter 2.

A clock generator 3 generates a clock for controlling each part of the interpolation circuit 1 and a control signal for controlling reading and writing of a memory from an input video signal, and outputs the control signal to each part of the interpolation circuit 1. To do.

The A / D converter 2 outputs the digitally converted video signal to two field memories 4 and 5, and the field memory 4 and field memory 5 input the video signal to the clock generator 3.
The data is sequentially stored based on the control signal input from.

That is, when a video signal as shown in FIG. 5 is input, the clock generator 3 controls the write signal 1-WE (before WE) for controlling writing and reading of the field memory 4 from this video signal. "-" Indicates that it is an inverted signal. The same shall apply hereinafter) and a read signal 1-OE are generated and output to the field memory 4 as a control signal, and writing and reading of the field memory 5 are performed. A write signal 2-WE and a read signal 2-OE for controlling the control signal are generated and output to the field memory 5 as control signals.

The field memory 4 has a write signal 1-WE.
Is low, a write operation is performed, and when the read signal 1-OE is low, a read operation is performed. Also, the field memory 5
Performs a write operation when the write signal 2-WE is low,
When the read signal 2-OE is low, the read operation is performed.

Each of the field memories 4 and 5 has a capacity for storing a video signal for one field, and writing and reading are alternately performed based on the control signal, and the read video signal is read. Is output to the line memory 6 and the multiplier 8.

Therefore, as shown in FIG. 5, the video signals A, B, C, ... For one field are, for example, when the video signal A is read into the field memory 4, the next video signal B is converted into the field. The video signal A of the field memory 4 is read at the timing when it is read into the memory 5 and the video B is read. This operation is sequentially repeated, and the video signals sequentially output from the field memory 4 and the field memory 5 in this manner are 1-field video signals A, B, C ... As shown in the bottom column of FIG. The video signal is input to the line memory 6 and the multiplier 8.

The line memory 6 delays the video signals a, b, c ... For one horizontal scan, which are sequentially input from the field memory 4 and the field memory 5, by one horizontal scanning period and outputs the delayed video signals to the multiplier 7. The multiplier 7 multiplies the video signal for one horizontal scan by the coefficient K1 and outputs it to the adder 9. The multiplier 8 includes a field memory 4 and a field memory 5.
The coefficient K2 is added to the video signal for one horizontal scan sequentially input from
And outputs to the adder 9.

Assuming that the image is magnified at a magnification of 4/3, as shown in FIG. 6, the video signal a for each horizontal scanning from one field memory 4 (or 5) by the read start signal, b, c ... Are read. In addition,
By the write start signal, the video signal for the next one field is written in the other field memory 5 (or 4) for each horizontal scanning. Here, based on the control signal from the clock generator 3, the multiplier 7 sets the coefficient K1 to 0/4, 1/4, 2/4 and 3/4 for each horizontal scanning, as shown in FIG. The multiplier 8 sequentially changes the coefficient K2 to 4 based on the control signal from the clock generator 3.
/ 4, 3/4, 2/4, and 1/4 are sequentially changed for each horizontal scanning, and the video signals are multiplied by the coefficients K1 and K2.

Then, the video signal multiplied by the coefficient K1 and the coefficient K2 thus changing is sequentially input to the adder 9 from the multiplier 7 and the multiplier 8, and the adder 9 outputs these video signals. The sum is added and output to the D / A converter 10.

Therefore, as shown in the bottom column of FIG. 6, the output of the adder 9 multiplies the video signal of each scanning line by a coefficient and adds it, and the number of scanning lines becomes a number corresponding to the enlargement ratio. Has been increased.

That is, when the magnification of the image is 4/3, as shown in FIG. 7, 4 out of the image signals of the three scanning lines.
The video signals of the book scanning lines are generated and interpolated by performing coefficient calculation between the scanning lines.

[0018]

However, in such a conventional image display device, since the image signal is interpolated using two field memories, the image display device is expensive. There was a problem of becoming a thing.

Therefore, an object of the present invention is to provide an image display device and an image display method which can inexpensively perform interpolation processing of an image signal with a single memory.

[0020]

The image display device of the present invention includes a storage means for storing an image signal for one field in a predetermined address order, and at least a vertical synchronization signal from the image signal. A timing generation means for generating a writing start signal for instructing to start writing to the storage means and a reading start signal for instructing to start reading of the previously written image signal from the storage means, An image display device for displaying after performing a predetermined process on the image signal stored in the storage means, wherein the timing generation means is configured to determine a write address of the image signal to the storage means based on the write start signal. A timing that completes the reading of the image signal from the storage means before overtaking the read address of the image signal from the storage means based on the reading start signal. In, and outputs the read start signal, by outputting the vertical synchronizing signal in response to the output timing of the read start signal, it has achieved the above objects.

Further, according to the image display method of the present invention, the image signal of this time is written in the memory means based on the write start signal from the memory means for storing the image signal in the order of the predetermined address for one field, and the read start signal is used. A method for displaying an image signal previously written on the basis of the previously written image signal, applying a predetermined process to the image signal read from the memory means, and displaying the image signal, wherein the write address of the memory means is based on the write start signal. Outputs the read start signal at the timing of completing the reading of the image signal from the storage means before passing the read address of the storage means based on the read start signal, and corresponds to the output timing of the read start signal. The above object is achieved by outputting the vertical synchronizing signal.

[0022]

According to the image display device and the image display method of the present invention, the current image signal is written in the storage means based on the write start signal from the storage means for storing the image signal for one field in the order of predetermined addresses. When the previously written image signal is read based on the read start signal, the memory is stored before the write address of the storage means based on the write start signal exceeds the read address of the storage means based on the read start signal. The reading start signal is output at the timing when the reading of the image signal from the device is completed, and the vertical synchronizing signal is output corresponding to the output timing of the reading start signal.
It is possible to perform the interpolation processing of the image signal for enlarging / reducing the image, and to make the image display device and the image display processing inexpensive.

[0023]

Embodiments Embodiments will be described below with reference to the drawings.

1 to 3 are views showing an embodiment of the image display device and the image display method of the present invention.
It is applied to a television receiver.

First, the structure will be described.

FIG. 1 is a circuit block configuration diagram of the television receiver 20, and FIG. 1 shows a circuit block configuration diagram of the television receiver 20 particularly focusing on the image signal.

The television receiver 20 includes an antenna 21, a tuner 22, a TV linear circuit 23, a synchronization control circuit 24,
An interpolation circuit 25, a common drive circuit 26, a segment drive circuit 27, a liquid crystal display panel 28 and the like are provided.

The antenna 21 receives TV radio waves,
The received radio wave is supplied to the tuner 22.

The tuner 22 selects a designated channel according to a tuning signal input from a control circuit (not shown), converts the received radio wave supplied from the antenna 21 into an intermediate frequency signal, and outputs it to the TV linear circuit 23. Output.

The TV linear circuit 23 is composed of an intermediate frequency amplification circuit, a video detection circuit, a video amplification circuit, an AFT detection circuit, etc., and an intermediate frequency signal input from the tuner 22 is amplified by the intermediate frequency amplification circuit. After that, AFT
AFT detection is performed by the detection circuit, image detection is performed by the video detection circuit to extract an image signal, and the image signal output from the video detection circuit is amplified by the video amplification circuit, and then the synchronization control circuit 24 and the interpolation circuit Output to 25.

The audio signal separated by the TV linear circuit 23 is sent to an audio circuit (not shown), the audio circuit detects the audio, converts the audio signal into a low frequency signal, amplifies the audio, and outputs from the speaker. Loud output is output.

The synchronization control circuit 24 is the TV linear circuit 23.
The horizontal and vertical synchronizing signals included in the image signal input from the are separated, the timing signal for display control is created based on the horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V-SYNC, and the segment drive circuit 27 and common The timing signal and the control signal are output to the interpolation circuit 25 while being output to the drive circuit 26.

The interpolating circuit 25 interpolates the image signal and outputs it to the segment drive circuit 27, as will be described later in detail.

The segment drive circuit 27 includes an interpolation circuit 25.
The image signal input from the liquid crystal display panel 28 is sequentially read by the timing signal input from the synchronization control circuit 24, the image signal for one line is read, and the gradation signal is created according to the image signal. Output to.

The common drive circuit 26 is the synchronization control circuit 24.
A scanning signal is generated in accordance with a timing signal input from, and the common electrodes of the liquid crystal display panel 28 are sequentially driven.

The interpolation circuit 25 and the synchronization control circuit 2
A part of 4 is configured as shown in FIG.

That is, the interpolation circuit 25 includes an A / D converter 30, a field memory 31, a line memory 32, a multiplier 33, a multiplier 34, an adder 35 and a D / A converter 36.
The synchronization control circuit 24 includes a clock generator 37 and a vertical synchronization conversion circuit 38.

An image signal is input to the A / D converter 30 and the clock generator 37 from the TV linear circuit 23 of FIG. 1, and the A / D converter 30 converts the analog image signal input from the TV linear circuit 23. It is converted into a digital image signal and output to the field memory 31.

The clock generator 37 is a TV
From the image signal input from the linear circuit 23, the interpolation circuit 2
A clock for controlling each part of 5 and a control signal for controlling reading and writing of the memory are generated and output to each part of the interpolation circuit 25, and a vertical synchronization signal is extracted from the image signal to generate a vertical signal. It outputs to the synchronous conversion circuit 38.

The clock generator 37 instructs the field memory 31 to start writing the image signal into the field memory 31, and to start reading the image signal previously written from the field memory 31. A read start signal is output. At this time, as will be described later, this read start signal has a write address based on the write start signal for the field memory 31 and a read address from the field memory 31 based on the read signal. Before passing, the image signal is output at the timing of completing the reading of the image signal from the field memory 31.

The field memory 31 has a capacity for storing an image signal for one field, and a digital image signal input from the A / D converter 30 is supplied with a control signal (writing start) from the clock generator 37. Based on the control signal (readout start signal), the stored image signals are sequentially read out,
Output to the line memory 32 and the multiplier 34.

The line memory 32 is based on the control signal from the clock generator 37 and the field memory 31.
The image signal of one horizontal scanning period read from is stored,
The image signal is delayed by one horizontal scanning period and output to the multiplier 7.

The multiplier 35 is a clock generator 37.
In accordance with the enlargement or reduction ratio of the image based on the control signal input from the, the image signal input from the line memory 32 is multiplied by a coefficient K1 that changes as shown in FIG. Output to.

The multiplier 34 is a clock generator 37.
In accordance with the enlargement or reduction ratio of the image based on the control signal input from, the image signal input from the field memory 31 is multiplied by, for example, a coefficient K2 that changes as shown in FIG. Output to.

The adder 35 has a coefficient K that changes in this way.
The image signals multiplied by 1 and the coefficient K2 are added, and the addition result is output to the D / A converter 36.

The D / A converter 36 converts the digital image signal of the addition result input from the adder 35 into an analog image signal, and as an interpolated image signal (interpolated image signal), the segment drive of FIG. Output to the circuit 27.

On the other hand, the vertical synchronizing conversion circuit 38 performs timing conversion of the vertical synchronizing signal input from the clock generator 37 to a timing earlier than the read start signal output from the clock generator 37 to the field memory 31, by a predetermined timing. Output as a corrected vertical sync signal.

Next, the operation of this embodiment will be described.

Now, it is assumed that the television receiver 20 multiplies the image signal in the vertical direction by 4/3 by the interpolation circuit 25 and displays it on the liquid crystal display panel 28.

That is, the interpolation circuit 25 converts the image signal input from the TV linear circuit 23 of FIG. 1 into a digital image signal by the D / A converter 30, and outputs it to the field memory 31.

As shown in FIG. 3, the field memory 31 starts writing the image signal input from the D / A converter 30 on the basis of the write start signal input from the clock generator 37, and also starts writing the image signal. Generator 3
Reading is started based on the reading start signal input from 7.

The image signal output from the field memory 31 is output to the multiplier 34 as it is, and after being delayed by one line in the line memory 32, input to the multiplier 33. Then, the multiplier 33 multiplies the image signal input from the line memory 32 by the coefficient K1 to be sequentially converted shown in FIG. 6, and outputs it to the adder 35.
The image signal input from the field memory 31 is multiplied by the sequentially changing coefficient K2 shown in FIG. 6 and output to the adder 35.

The adder 35 adds the image signal of the multiplication result of the multiplier 33 and the image signal of the multiplication result of the multiplier 34, and from the image signals of three scanning lines, as shown in FIGS. 6 and 7. Image signals for four scanning lines are generated and output to the D / A converter 36. The D / A converter 36 converts the input digital image signal into an analog image signal and outputs it as an interpolated image signal to the segment drive circuit 27.

However, the writing of the image signal to the field memory 31 and the reading of the image signal from the field memory 31 are conventionally performed by vertical synchronization extracted from the image signal, as shown in FIG. 3 as an old field memory read start signal. Since the read start signal was output at a timing slightly later than the signal and the write start signal was output after a predetermined time from this read start signal, the write start signal was output during the reading of the image signal started by this read start signal. The write address for writing the image signal started by the write start signal exceeds the read address.

That is, in the field memory 31, the time required for reading is longer than the time required for writing, and one field memory 31 is used to set the timing of the conventional old field memory read start signal. At the timing of the write start signal, the field memory 3
When writing and reading 1 are performed, the read address overtakes the write address on the way, and as shown in the old field memory output data in FIG. 3, not only the previously written data but also the output data of the field memory 31 is output. The data written this time is output. for that reason,
A proper image signal interpolation process cannot be performed.

Therefore, in the present embodiment, as indicated by the field memory read start signal in FIG. 3, the writing is performed during the reading of the image signal from the time required for reading the field memory 31 and the time required for writing. The clock generator 37 outputs a read start signal at the timing when the reading of the image signal is completed before the address passes the read address.

As a result, from the field memory 31,
As shown in FIG. 3, only the previously written image signal is set to 1
It can be surely read within the field period.

Since the timing of the read start signal of the field memory 31 of the interpolation circuit 25 is advanced, the timing shown in FIG.
As shown in (4), the timing of the vertical synchronizing signal is also output earlier in the vertical synchronizing conversion circuit 28 accordingly. Specifically, the vertical synchronization conversion circuit 38 outputs the vertical synchronization signal extracted by the clock generator 37 to the field memory 31.
The read start signal is output at a predetermined timing.

Since the corrected vertical synchronizing signal is created on the basis of the vertical synchronizing signal before being corrected or the horizontal synchronizing signal corresponding to the vertical synchronizing signal, the horizontal synchronizing signal does not need to be corrected and can be used as it is. Can be used.

As described above, before the write address of the field memory 31 based on the write start signal exceeds the read address of the field memory 31 based on the read start signal,
At the timing of completing the reading of the image signal from the field memory 31, the read start signal is output and the vertical synchronizing signal is output by a predetermined time earlier than the output timing of the read start signal. By using only 31, the interpolation processing of the image signal for enlarging / reducing the image can be performed, and the interpolation circuit 25 and thus the television receiver 20 can be made inexpensive.

In the above embodiment, the case where the present invention is applied to the television receiver 20 has been described, but the present invention is not limited to this, and the present invention is applied to an image display device for changing the vertical magnification of an image and its image display method. can do.

[0062]

According to the present invention, the timing for completing the reading of the image signal from the storage means before the write address of the storage means based on the write start signal exceeds the read address of the storage means based on the read start signal. In addition to outputting the read start signal, the vertical synchronizing signal is output earlier by a predetermined time than the output timing of the read start signal. Interpolation processing can be performed, and the image display device and the image display processing can be made inexpensive.

[Brief description of drawings]

FIG. 1 is a circuit block configuration diagram of a television receiver to which an embodiment of an image display device and an image display method of the present invention is applied.

FIG. 2 is a detailed circuit block diagram of an interpolation circuit and a clock generator of FIG.

FIG. 3 is an operation timing chart of the interpolation circuit and the clock generator of FIG.

FIG. 4 is a circuit block diagram of an example of an interpolation circuit of a conventional image display device.

5 is a diagram showing a relationship between a write signal and a read signal for the two field memories of FIG. 4 and an output of the field memory.

FIG. 6 is a diagram showing the operation timing of the interpolation processing of FIG.

FIG. 7 is a diagram showing a relationship between an image before interpolation and an image after interpolation.

[Explanation of symbols]

 20 TV receiver 21 Antenna 22 Tuner 23 TV linear circuit 24 Synchronous control circuit 25 Interpolation circuit 26 Common drive circuit 27 Segment drive circuit 28 Liquid crystal display panel 30 A / D converter 31 Field memory 32 Line memory 33, 34 Multiplier 35 Addition 36 D / A converter 37 Clock generator 38 Vertical synchronization conversion circuit

Claims (2)

[Claims] 1. A storage means for storing an image signal for one field in a predetermined address order, and a writing operation for taking out at least a vertical synchronizing signal from the image signal and for instructing to start writing the current image signal into the storage means. A timing generation means for generating a start signal and a read start signal for instructing the start of reading of the previously written image signal from the storage means, and subjecting the image signal stored in the storage means to predetermined processing. An image display device for displaying after the addition, wherein the timing generation means is such that the write address of the image signal to the storage means based on the write start signal is an image from the storage means based on the read start signal. The read start signal may be output at the timing of completing the reading of the image signal from the storage unit before overtaking the read address of the signal. An image display apparatus characterized by in response to the output timing of the read start signal to output the vertical synchronizing signal. 2. An image signal previously written based on a read start signal from a memory means for storing an image signal for one field in order of a predetermined address, based on a write start signal. Is an image display method in which the image signal read from the storage means is subjected to predetermined processing and then displayed, wherein the write address of the storage means based on the write start signal is based on the read start signal. The read start signal is output at the timing when the reading of the image signal from the storage means is completed before the read address of the storage means is overtaken, and the vertical synchronization signal is output corresponding to the output timing of the read start signal. Image display method characterized by.