JPH0774791A - Digital signal demodulator - Google Patents

Abstract

PURPOSE:To easily receive a digital signal at a different transmission clock speed by applying PLL control to a voltage controlled clock oscillation signal and varying an oscillated frequency based on output data from a microcomputer. CONSTITUTION:A voltage controlled clock oscillation circuit 21 uses a PLL circuit 22 and a reference oscillation circuit 26 to apply PLL control. That is, an output of the circuit 21 is fed to a 1st frequency divider 25 where the signal is frequency-divided into 1/M and a reference oscillation signal from a reference oscillation circuit 26 is given to a 2nd frequency divider 23, in which the signal is frequency-divided into 1/N, the frequency divided signals are phase- compared at a phase comparator 24 and an error voltage is fed back to the voltage controlled oscillation circuit 21 to control the clock frequency. Frequency division ratio of the frequency dividers 23, 25 are controlled by an output signal of the microcomputer 6 in response to a channel selection signal received from an input terminal 7 and the clock frequency in response to the reception channel is selected. A control signal from the microcomputer 6 is adjusted by a signal fed back from a phase detection circuit 20 to the microcomputer 6 to fine-adjust the frequency division ratio of the frequency dividers 23, 24.

Description

Detailed Description of the Invention

[0001]

The present invention relates to MSK (Minimum S
hift keing) modulation, QPSK (Quadrature Phase)
The present invention relates to a digital signal demodulating device that is suitable for use in a receiver or the like that receives a digitally modulated signal such as e Shift Keing) modulation.

[0002]

2. Description of the Related Art Received MSK, QPSK or QA
A digital signal demodulator using a synchronous detection method for demodulating a digital signal such as M requires a clock recovery circuit for recovering a clock signal synchronized with the transmission clock speed of the signal. As a conventional clock recovery circuit,
For example, in the technique described in Japanese Patent Laid-Open No. 4-172840,
I (In Phase) output signal and Q (Q) after synchronous detection
A clock component is extracted from the output signal of the quadrature phase), the oscillation frequency of the voltage controlled clock oscillator is controlled by this extracted component, and a clock signal synchronized with the transmission clock speed is obtained. This method is applicable to a transmission system with a constant transmission clock speed, and cannot be used in a system in which the transmission speed changes or a system which receives signals of different transmission speeds.

[0003]

At present, in Japan, the transmission rate by the MSK modulation method using a communication satellite is about 24 Mbp.
s digital music broadcasting is being carried out, and in the future,
Digital TV broadcasting by broadcasting satellite is also planned.
In this digital TV broadcasting, the TV signal is 2 to 3 on 1ch.
Since wave multiplexing is used for transmission, QPSK will be used as the modulation method, and a transmission rate of about 40 Mbps is planned. In the United States, about 1 using QAM modulation
7 Mbps terrestrial digital HDTV broadcasting, Q
Direct TV (satellite broadcasting) with a transmission rate of 30 Mbps using PSK modulation is also planned.

As described above, an inexpensive receiver capable of supporting digital broadcasts having different transmission speeds will be required in the future.

The above-mentioned prior art does not consider a system in which the transmission rate changes in the same channel or a multi-channel transmission system in which signals of different transmission rates are received for each channel. Since it is variable, there is a problem that the circuit configuration becomes complicated and the circuit scale increases, and it cannot be applied to a consumer receiver.

An object of the present invention is to solve the above problem and to provide a digital signal demodulating device having a simple structure capable of receiving signals having different transmission rates.

[0007]

In order to achieve the above object, the present invention uses the following means. First of all
Then, the clock component of the received signal is extracted from the I output signal and the Q output signal of the synchronous detection output. Next, the oscillation frequency of the voltage controlled clock oscillator is divided by a frequency divider, a PLL for phase comparison with the reference oscillator is applied, and the frequency division ratio of the frequency divider is controlled by a control signal from a microcomputer for channel selection. As a result, the oscillation frequency of the voltage controlled clock oscillator is changed. Further, in order to synchronize with the transmission clock of the received signal, the extracted clock component of the received signal is phase-compared with the oscillation frequency of the voltage controlled clock oscillator applied with the PLL, and the error component is used as the clock AFC signal for channel selection. Return to the microcomputer. The control signal from the microcomputer is changed by this feedback signal, and the frequency division ratio of the frequency divider is changed to establish synchronization between the oscillation frequency of the voltage controlled clock oscillator and the transmission clock of the received signal to perform clock regeneration.

As other means, a low-frequency oscillation circuit, a switching circuit for switching oscillation signals from the low-frequency oscillation circuit, and whether or not the oscillation signal of the voltage-controlled clock oscillator is synchronized with the transmission clock of the received signal. It is equipped with a synchronous detection circuit that detects the phase of the clock component of the extracted signal and the voltage-controlled clock oscillator, and returns the composite signal of the error voltage output of the phase comparator and the output of the low-frequency oscillator to the voltage-controlled clock oscillator. The low-frequency oscillation signal is switched by turning on and off the switching circuit according to the synchronization detection signal from the synchronization detection circuit. That is, when the oscillation signal of the voltage-controlled clock oscillator is not in synchronization with the transmission clock of the received signal, the oscillation frequency of the voltage-controlled clock oscillator is swept by the low frequency signal, and when it is in the synchronized state, the sweep is stopped. With this configuration, even when the transmission clock speed changes, the oscillation frequency of the voltage-controlled clock oscillator and the transmission clock of the received signal are instantly synchronized with each other to perform clock recovery.

[0009]

First, the clock component of the received signal is extracted from the I output signal and the Q output signal of the synchronous detection output. Next, the oscillation frequency of the voltage controlled clock oscillator is divided by a frequency divider, a PLL for phase comparison with the reference oscillator is applied, and the frequency division ratio of the frequency divider is controlled by a control signal from a microcomputer for channel selection. By doing so, the oscillation frequency of the voltage controlled clock oscillator is changed. Further, in order to synchronize with the transmission clock of the received signal, the phase of the extracted clock component of the received signal and the oscillation frequency of the voltage-controlled clock oscillator applied with PLL are compared, and the error component is used as a clock AFC signal for channel tuning. By returning to the microcomputer, changing the control signal from the microcomputer and changing the frequency division ratio of the frequency divider, the oscillation frequency of the voltage controlled clock oscillator and the transmission clock of the received signal are synchronized, and the clock is regenerated.

As other means, a low-frequency oscillation circuit, a switching circuit for switching oscillation signals from the low-frequency oscillation circuit, and whether or not the oscillation signal of the voltage controlled clock oscillator is synchronized with the transmission clock of the received signal. Equipped with a synchronous detection circuit to detect the phase of the extracted signal and the phase of the voltage controlled clock oscillator, the composite signal of the error voltage output of the phase comparator and the low frequency oscillator is sent to the voltage controlled clock oscillator. The low-frequency oscillation signal is switched by feeding back and switching the switching circuit ON and OFF according to the synchronization detection signal from the synchronization detection circuit. That is, when the oscillation signal of the voltage-controlled clock oscillator is not in synchronization with the transmission clock of the received signal, the oscillation frequency of the voltage-controlled clock oscillator is swept by the low frequency signal, and when it is in the synchronized state, the sweep is stopped. With this configuration, even when the transmission clock speed changes, the oscillation frequency of the voltage-controlled clock oscillator and the transmission clock of the received signal can be instantly synchronized and clock recovery can be performed.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a digital signal demodulating device according to the present invention. Reference numeral 1 is an input terminal, 2 is a frequency conversion circuit, 3 is a local oscillation circuit, 4 is a tuning PLL circuit, 5 is a first reference oscillation circuit, 6 is a microcomputer (hereinafter referred to as microcomputer), and 7 is channel selection. Station signal input terminal, 8 is an intermediate frequency filter, 9, 10
Is a synchronous detection circuit, 11 is a voltage-controlled oscillator circuit for synchronous detection,
12 is a π / 2 phase shifter, 13 and 14 are low-pass filters,
Reference numeral 15 is a carrier reproduction circuit, 16 is a clock component extraction circuit, 17 and 18 are output terminals, 19 is an AFC circuit, 20 is a first phase detection circuit, 21 is a voltage control clock oscillation circuit, and 22 is a PLL circuit which is a first circuit. It is composed of a frequency divider 23, a second frequency divider 25, and a second phase detection circuit, and 26 is a second reference oscillation circuit.

In FIG. 1, a digitally modulated received high frequency (RF) signal input from an input terminal 1 is mixed with an output signal of a local oscillation circuit 3 for channel selection in a frequency conversion circuit 2 to obtain an intermediate frequency. (IF) signal. Here, the tuning data corresponding to the channel tuning signal input from the input terminal 7 is output from the microcomputer 6, is input to the tuning PLL 4, and the tuning voltage is output from the tuning PLL 4 to the local oscillation circuit 3. Supplied.

The output signal of the frequency conversion circuit 2 is supplied to the IF filter, which is a bandpass filter, so that the received signal other than the channel designated by the channel selection signal input from the input terminal 7 and the unnecessary band. External noise, interference, etc. are removed, and the IF signal of the channel designated by this channel selection signal is selected.
The IF filter 8 also performs waveform equalization so as to optimize the characteristics of the transmission line.

The IF signal output from the IF filter 8 is divided into two and supplied to the synchronous detection circuits 9 and 10. In the synchronous detection circuit 9, the oscillation signal output from the voltage controlled oscillation circuit 11 is phase-shifted and supplied by the π / 2 phase shifter 12, whereby the IF signal from the IF filter 8 is synchronously detected. Further, even in the synchronous detection circuit 10, the IF signal from the IF filter 8 is generated by the oscillation signal from the voltage controlled oscillation circuit 11.
The signal is synchronously detected. The outputs of the synchronous detection circuits 9 and 10 are output from the output terminals 17 and 18 as digital demodulation signals via the low pass filters (LPF) 13 and 14.

The outputs of the LPFs 13 and 14 are also input to the carrier recovery circuit 15 and the clock extraction circuit 16. The carrier reproduction circuit 15 detects the frequency error signal and the phase error signal of the IF signal input to the synchronous detection circuits 9 and 10 and the oscillation signal of the voltage controlled oscillation circuit 11. The frequency error signal is fed back to the microcomputer 6 via the AFC circuit 19, the output data of the microcomputer 6 is changed, the oscillation frequency of the local oscillation circuit 3 is controlled, and the IF signal and the voltage control oscillation circuit 11
AFC is applied so that the frequencies of the oscillation signals of are matched. On the other hand, the phase error signal is fed back to the voltage controlled oscillator circuit 11 and a phase locked loop is applied so that the IF signal and the phase of the voltage controlled oscillator circuit 11 are matched.

The clock extraction circuit 16 extracts a clock component from the digital demodulated signal using, for example, a square circuit, and inputs it to the first phase comparison circuit 20. Similarly, the first phase comparison circuit includes a voltage control clock oscillation circuit 2
The oscillation signal from 1 is input, and the phase error signal with the above clock component is fed back to the microcomputer 6.

The voltage control clock oscillation circuit 21 is a PLL.
PLL control is performed by the circuit 22 and the reference oscillation circuit 26. That is, the voltage controlled clock oscillator circuit 21 is divided into 1 / M (M is an integer) by the first frequency divider 25, and is similarly divided into 1 / N (N is an integer) by the second frequency divider 23. The frequency of the divided reference oscillation signal of the reference oscillation circuit 26 is compared with that of the phase comparison circuit 24, and the error voltage is fed back to the voltage control clock oscillation circuit 21 to control the clock frequency. Here, the frequency division ratio of the first and second frequency dividers 23 and 25 is controlled by the control signal output from the microcomputer 6 in accordance with the channel selection signal input from the input terminal 7, and the control signal is input to the receiving channel. The corresponding clock frequency is selected. The control signal output from the microcomputer 6 is adjusted by the phase error signal fed back to the microcomputer 6 from the first phase detection circuit described above,
A loop that finely adjusts the frequency division ratio of the frequency dividers 23 and 24 is configured. With this configuration, the output signal of the voltage control clock oscillation circuit 21 can be synchronized with the clock of the received signal, and even when signals with different clock frequencies are received, the output signal of the voltage control clock oscillation circuit 21 is changed. The received clock can be easily followed.

In the present invention, PLL control is applied to the voltage control clock oscillation signal 21 and the oscillation frequency is changed according to the output data from the microcomputer 6, so that digital signals having different transmission clock speeds can be easily received. Further, the clock extraction component from the clock extraction circuit 16 and the output signal of the voltage control clock oscillation circuit are compared in phase by the phase comparator 20, and the error signal is fed back to the microcomputer 6 to adjust the oscillation frequency of the voltage control clock oscillation circuit. As a result, a clock oscillation signal synchronized with the transmission clock can be obtained.

FIG. 2 is a block diagram showing still another embodiment of the digital signal demodulating device according to the present invention.
Is a low-frequency oscillator circuit, 27 is a switching circuit, and 29 is a synchronization detection circuit. The parts corresponding to those in FIG. The clock component output from the clock extraction circuit 16 is input to the first phase comparison circuit 20. Similarly, the oscillation signal from the voltage control clock oscillation circuit 21 is input to the first phase comparison circuit, and the phase error signal with the clock component is output. A low-frequency signal from the low-frequency oscillation circuit 28 is superimposed on the phase error signal via the switching circuit 27 and fed back to the voltage control clock oscillation circuit. The switching circuit 27 is turned on / off according to a synchronization detection signal from the synchronization detection circuit 29. That is, when the transmission clock of the received signal and the output signal of the voltage control clock oscillator 21 are in an asynchronous state, the switching circuit 27 is turned on by the control signal from the synchronization detection circuit 29.
Then, the oscillation frequency of the voltage controlled clock oscillator is swept and synchronized with the low frequency signal. When the transmission clock of the received signal and the output signal of the voltage controlled clock oscillator 21 are in a synchronous state, the switching circuit 27 is turned off by the control signal from the synchronization detection circuit 29, and only the phase error signal from the phase comparison circuit 20 is used. It forms a feedback loop and keeps the synchronization state.

In the present embodiment, when the synchronization detection circuit 29 detects the synchronization or the asynchronism and is in the asynchronous state,
The low-frequency sweep causes the voltage-controlled clock oscillator circuit to follow the clock of the received signal for synchronization, and when the synchronized state is reached, the low-frequency sweep is cut off, and the received signal is automatically received without applying a control signal from the outside. Since the clocks can be synchronized with each other, it is possible to receive signals having different transmission rates with a simple configuration.

FIG. 3 is a block diagram showing still another embodiment of the digital signal demodulating device according to the present invention.
Is a clock switching circuit, and 31 is a switching signal. The parts corresponding to those in FIG. This embodiment is a receiver that receives, for example, an MSK-modulated signal and a QPSK-modulated signal, and outputs a switching signal 31 output from the microcomputer 7 in accordance with a channel selection signal input from the input terminal 7. It is applied to the IF filter 8, LPFs 13 and 14, the switching circuit 30, the carrier reproducing circuit 15, and the clock extracting circuit 16. For example, when the transmission rates of the received MSK signal and the QPSK signal are different, the IF filter 8 and LPF
It is necessary to set the bandwidth of 13 and 14 to a value suitable for the transmission rate, and for this purpose, the switching signal 31 switches the bandwidth of the filter. Also, MSK signal and Q
Since the carrier reproducing circuit 15 and the clock extracting circuit 16 have different configurations in the PSK signal, the configurations of these circuits are simultaneously switched by the switching signal 31. Furthermore, MSK
Since a clock signal is also required for the signal carrier reproducing circuit, the switching signal 31 is applied to the switching circuit 30 and the switching circuit 30 is turned on when the MSK signal is received.
However, the switching circuit 30 is turned off when the QPSK signal is received.
It was configured to do.

According to this embodiment, M having different transmission rates is used.
The SK modulation signal and the QPSK signal can be received with a simple configuration by using the control signal from the microcomputer. Further, since the filter bandwidth is switched by the control signal from the microcomputer, it is possible to always receive signals with different transmission rates in an optimum state.

FIG. 4 is a block diagram showing still another embodiment of the digital signal demodulating device according to the present invention.
Is a clock switching circuit, 31 is a switching signal, 32
2 is a frequency detection circuit, and 33 is a control signal generation circuit. The parts corresponding to those in FIG. The present embodiment is a receiver that receives, for example, an MSK-modulated signal and a QPSK-modulated signal, and the frequency of the output signal of the voltage control clock oscillation circuit 21 (in the synchronous state, the frequency of the output signal matches the clock of the received signal. Is detected by the frequency detection circuit 32, the detection signal is input to the control signal generation circuit 33, and the control signal generation circuit 33 is input according to the detection signal.
Generates a switching signal 34 from the switching signal 34
Are applied to the IF filter 8, LPFs 13 and 14, switching circuit 30, carrier regeneration circuit 15, and clock extraction circuit 16, respectively. For example, when the reception MSK signal and the QPSK signal have different transmission rates, the IF filter 8,
It is necessary to set the bandwidth of the LPFs 13 and 14 to a value suitable for the transmission rate. For this reason, the switching signal 31 switches the bandwidth of the filter. Further, since the configurations of the carrier recovery circuit 15 and the clock extraction circuit 16 are different between the MSK signal and the QPSK signal, the configurations of these circuits are also switched by the switching signal 31. further,
Since a clock signal is also required for the carrier reproducing circuit for the MSK signal, the switching signal 31 is applied to the switching circuit 30 and the switching circuit 30 is turned on when the MSK signal is received.
When the QPSK signal is received, the switching circuit 30 is turned off.
It was set to F.

According to this embodiment, M having different transmission rates is used.
The SK modulation signal and the QPSK signal can be received with a simple configuration by using the control signal from the microcomputer. Further, since the filter bandwidth is switched by the control signal from the microcomputer, it is possible to always receive signals with different transmission rates in an optimum state. Further, in the present embodiment, the frequency detection circuit 32 and the control signal generation circuit 33 are used to automatically switch the bandwidth of the filter and the like, and no control signal from the outside is required. There is an effect that the signal of the transmission speed can be received.

[0026]

As described above, according to the present invention,
By subjecting the voltage control clock oscillation signal to PLL control and changing the oscillation frequency according to the output data from the microcomputer, it is possible to easily receive digital signals of different transmission clock speeds. In addition, the clock extraction component from the clock extraction circuit and the output signal of the voltage control clock oscillation circuit are compared in phase by the phase comparator, and the error signal is fed back to the microcomputer to adjust the oscillation frequency of the voltage control clock oscillation circuit. A clock oscillation signal synchronized with the transmission clock can be obtained.

Further, a synchronization detection circuit for detecting synchronization or asynchronism is provided, and when in an asynchronous state, the voltage control clock oscillation circuit is made to follow the clock of the received signal by the low frequency sweep to perform synchronization, and when in a synchronized state, By using the configuration that cuts off the frequency sweep, it is possible to automatically synchronize the clock of the received signal without applying a control signal from the outside, so it is possible to receive signals of different transmission rates with a simple configuration. You can

Further, if the filter bandwidth is switched by the control signal from the microcomputer or the control signal from the control signal generating circuit, there is an effect that signals of different transmission rates can always be received in an optimum state.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Input terminal, 9 and 10 ... Synchronous detection circuit, 16 ... Clock extraction circuit, 20 ... Phase detection circuit, 22 ... PLL circuit, 26 ... Reference oscillation circuit, 21 ... Voltage control clock oscillation circuit.

Claims (4)

[Claims] 1. At least a clock extraction circuit for extracting a transmission clock component from a demodulated signal, a phase comparison circuit, a voltage control clock oscillation circuit, and a microcomputer (hereinafter referred to as a microcomputer) to demodulate and demodulate a digitally modulated high frequency signal. In a demodulator that outputs a digital signal,
The extracted transmission clock component and the oscillation signal from the voltage control clock oscillation circuit are phase-compared by the phase comparison circuit, and the error signal component output from the phase comparison circuit is fed back to the microcomputer. Outputting correction data in which the error signal component is superimposed on data preset according to the reception channel, controlling the oscillation frequency of the voltage control clock oscillation circuit with the correction data, and oscillating the voltage control clock oscillation circuit. A digital signal demodulating device characterized in that a frequency is synchronized with the transmission clock. 2. A digital demodulated high frequency signal is demodulated by at least a clock extraction circuit for extracting a transmission clock component from a demodulated signal, a phase comparison circuit, a voltage control clock oscillation circuit, a synchronization detection circuit, and a low frequency signal generation circuit. Then
In a demodulation device that outputs a demodulated digital signal, the extracted transmission clock component and the oscillation signal from the voltage control clock oscillation circuit are phase-compared by the phase comparison circuit, and an error signal component output from the phase comparison circuit is obtained. Superimposing a low frequency signal from the low frequency signal generation circuit, switching the low frequency signal with a synchronization detection signal from the synchronization detection circuit, controlling the oscillation frequency of the voltage control clock oscillation circuit with the superposition signal, A digital signal demodulating device characterized in that the oscillation frequency of the voltage control clock oscillation circuit is synchronized with the transmission clock. 3. At least an intermediate frequency filter, a low-pass filter (hereinafter referred to as LPF) that removes unnecessary noise components from a demodulated digital signal, a clock extraction circuit that extracts a transmission clock component from the demodulated signal, a phase comparison circuit, and a voltage control clock oscillator circuit. , Microcomputer (hereinafter referred to as "microcomputer")
In a demodulator for demodulating a digitally modulated high frequency signal and outputting a demodulated digital signal, the extracted transmission clock component and the oscillation signal from the voltage controlled clock oscillation circuit are phase-compared by the phase comparison circuit. ,
The error signal component output from the phase comparison circuit is fed back to the microcomputer, and the microcomputer outputs correction data obtained by superimposing the error signal component on the preset data according to the reception channel, and the correction data is used for the correction data. A digital signal demodulation device characterized in that the oscillation frequency of a voltage control clock oscillation circuit is controlled, and the bandwidths of the intermediate frequency filter and LPF are switched by an output control signal preset according to the receiving channel from the microcomputer. . 4. At least an intermediate frequency filter, a low-pass filter (hereinafter referred to as LPF) that removes unnecessary noise components from a demodulated digital signal, a clock extraction circuit that extracts a transmission clock component from a demodulated signal, a phase comparison circuit, and a voltage control clock oscillation circuit. , A synchronization detection circuit, a low-frequency signal generation circuit, a frequency detection circuit that detects the frequency of the oscillation signal from the voltage control clock oscillation circuit, and a control signal generation circuit that generates a control signal according to the detection signal from the frequency detection circuit In a demodulator for demodulating a digitally modulated high frequency signal and outputting a demodulated digital signal, the extracted transmission clock component and the oscillation signal from the voltage control clock oscillation circuit are phase-compared by the phase comparison circuit, The error signal component output from the phase comparison circuit is added to the low frequency from the low frequency signal generation circuit. Superimposing the signal, ON said low frequency signal by the synchronization detection signal from the synchronization detection circuit, and OFF,
A digital signal demodulating device characterized in that the bandwidths of the intermediate frequency filter and the LPF are switched according to an output signal of the control signal generating circuit.