JPH0773108B2 - Optical device substrate manufacturing equipment - Google Patents

Optical device substrate manufacturing equipment

Info

Publication number
JPH0773108B2
JPH0773108B2 JP4311844A JP31184492A JPH0773108B2 JP H0773108 B2 JPH0773108 B2 JP H0773108B2 JP 4311844 A JP4311844 A JP 4311844A JP 31184492 A JP31184492 A JP 31184492A JP H0773108 B2 JPH0773108 B2 JP H0773108B2
Authority
JP
Japan
Prior art keywords
minute
punch
die
substrate
micro
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP4311844A
Other languages
Japanese (ja)
Other versions
JPH06163555A (en
Inventor
宏 本望
正隆 伊藤
純一 佐々木
義信 金山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4311844A priority Critical patent/JPH0773108B2/en
Publication of JPH06163555A publication Critical patent/JPH06163555A/en
Publication of JPH0773108B2 publication Critical patent/JPH0773108B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)
  • Semiconductor Lasers (AREA)
  • Punching Or Piercing (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、光通信用光モジュール
などに用いられる光素子を固定する基板の製造装置に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate manufacturing apparatus for fixing an optical element used in an optical module for optical communication.

【0002】[0002]

【従来の技術】光通信は、半導体レーザ(LD)、発光
ダイオード(LED)、ファトダイオード(PD)、光
変調器を始めとして、光ファイバ、光スイッチ、光アイ
ソレータ、光導波路等の能動、受動素子の高性能、高機
能化により応用範囲が拡大されつつある。近年、この応
用範囲の一つとして一般加入者系への適用が考えられて
おり、これに伴い、光素子を搭載したモジュールの低価
格化が要求されている。モジュール低価格化の有効な手
段として、複数個の微小接合バンプを介して光素子を無
調整で基板上に実装する無調整光実装が注目されてい
る。
2. Description of the Related Art Optical communications include semiconductor lasers (LDs), light emitting diodes (LEDs), photodiodes (PDs), optical modulators, active fibers such as optical fibers, optical switches, optical isolators, and optical waveguides. The range of applications is expanding due to the high performance and functionality of devices. In recent years, application to general subscriber systems has been considered as one of the application ranges, and along with this, there has been a demand for cost reduction of modules equipped with optical elements. As an effective means for reducing the cost of a module, unadjusted optical mounting, in which an optical element is mounted on a substrate without adjustment through a plurality of micro-junction bumps, has been attracting attention.

【0003】微小接合バンプを形成する方法は、微小ポ
ンチとダイスとを用いてリボン状の接合金属を打ち抜
き、基板上に微小接合バンプを転写するもので、微小接
合バンプとして信頼性の高いAuSnバンプを用いたも
のが特開平4−152682号公報、「アレイ状光素子
用サブ基板の作製方法」に詳細に記されている。
A method of forming a micro-bonding bump is to punch a ribbon-shaped bonding metal using a micro-punch and a die and transfer the micro-bonding bump onto a substrate. The AuSn bump is highly reliable as the micro-bonding bump. The method using is described in detail in Japanese Patent Application Laid-Open No. 4-152682, "Method for producing array-shaped optical element sub-substrate".

【0004】[0004]

【発明が解決しようとする課題】微小ポンチとダイスと
を用いてリボン状の接合金属を打ち抜く際、微少ポンチ
の中心軸とダイス穴の中心軸は、装置の組立精度上の問
題から必ずしも一致していない。このため、打ち抜きご
との微少AuSnバンプの形状、重量は異なる。これに
より、複数個の微少接合バンプを介して接合された光素
子は、傾き、接合不良などの欠陥を生じ、実装歩留まり
が低下するという大きな問題があった。
When punching a ribbon-shaped joining metal using a minute punch and a die, the center axis of the minute punch and the center axis of the die hole do not always coincide with each other due to problems in assembly accuracy of the apparatus. Not not. Therefore, the shape and weight of the minute AuSn bump are different for each punching. As a result, an optical element bonded via a plurality of micro-bonded bumps suffers from defects such as tilting and bonding failure, resulting in a large problem of reduced mounting yield.

【0005】[0005]

【課題を解決するための手段】本発明の光素子用基板の
製造装置は、微小ポインチとダイスを用いてリボン状の
接合金属を打ち抜き、基板上に微小接合バンプを形成す
る光素子用基板の製造装置において、前記ダイス穴形状
が入口で広く出口で狭くなっていることを特徴とる。
An optical element substrate manufacturing apparatus according to the present invention is an optical element substrate for punching a ribbon-shaped bonding metal using a minute poinch and a die to form minute bonding bumps on the substrate. In the manufacturing apparatus, the shape of the die hole is wide at the inlet and narrow at the outlet.

【0006】[0006]

【作用】微小ポンチをリボン状の接合金属に打付け、微
少接合バンプを基板上のパット表面に打ち抜く際に、ポ
ンチの中心軸がダイスの穴中心から多少ずれていても、
ダイスの穴形状が入口で広く出口で狭くなっているた
め、微少ポンチがダイスの穴の内側に押し込まれるに従
い微少ポンチの中心軸は、強制的にダイスの穴中心に一
致する。これにより、形状、重量ともに同等な微少接合
バンプを再現性良く形成することができる。
[Function] When a micro punch is punched on a ribbon-shaped bonding metal and a micro bonding bump is punched on the surface of a pat on a substrate, even if the center axis of the punch is slightly displaced from the center of the die hole,
Since the hole shape of the die is wide at the inlet and narrow at the outlet, the central axis of the minute punch is forced to coincide with the center of the hole of the die as the minute punch is pushed inside the hole of the die. As a result, it is possible to reproducibly form minute bonding bumps having the same shape and weight.

【0007】[0007]

【実施例】以下、本発明について、図面を参照して説明
する。図1は、本発明の第1の実施例を示す概要図であ
る。本構成では、厚さ50μmのリボン状のAuSn箔
3が、外径50μmの超鋼製微小ポンチ1と大穴径10
0μm、小穴直径60μmの厚さ1mmのステンレス製
ダイ2の間に挿入されている(図1(a))。ここで、
微少ポンチ1の中心軸とダイス2の穴の中心軸がズレて
いても、微少ポンチ1をAuSn箔3に打付け、微少A
uSnバンプ6を打ち抜く際、ダイス2の穴形状が入口
で広く出口で狭くなっているため、微少ポンチ1がダイ
ス2の穴の内側に押し込まれるに従い、微少ポンチの中
心軸は強制的にダイス2の穴の中心軸に一致し、Si基
板4上の直径60μmのAuパット5表面に打ち抜かれ
る(図1(b))。これにより、形状、重量ともに同等
な微少接合バンプを再現性良く形成することができる。
従って、打ち抜きごとの微少接合バンプの形状、重量は
一定となる。複数個の微少AuSnバンプを介して接合
された光素子の接合状態は良好で、実装歩留まりが向上
する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram showing a first embodiment of the present invention. In this configuration, a ribbon-shaped AuSn foil 3 having a thickness of 50 μm is used as a micro steel punch 1 having an outer diameter of 50 μm and a large hole diameter 10
It is inserted between a stainless steel die 2 having a thickness of 0 μm and a small hole diameter of 60 μm and a thickness of 1 mm (FIG. 1A). here,
Even if the center axis of the minute punch 1 and the center axis of the hole of the die 2 are misaligned, the minute punch 1 is struck on the AuSn foil 3 and the minute A
When punching out the uSn bump 6, the hole shape of the die 2 is wide at the entrance and narrow at the exit. It is punched on the surface of the Au pad 5 having a diameter of 60 μm on the Si substrate 4 in conformity with the central axis of the hole (FIG. 1B). As a result, it is possible to reproducibly form minute bonding bumps having the same shape and weight.
Therefore, the shape and weight of the micro-bonded bump for each punching are constant. The optical element bonded via the plurality of minute AuSn bumps has a good bonding state, and the mounting yield is improved.

【0008】以上、本実施例では微少ンチの数を1つと
したが、これに限定されず、多数個の微少ポンチを用い
ても良い。さらに微少ポンチは丸形のポンチを用いた
が、これに限らず四角形や多角のポンチを用いても良
く、その場合、穴の内形はポンチの外形に相似となる。
As described above, the number of the minute punches is one in this embodiment, but the number is not limited to this, and a large number of minute punches may be used. Further, although the round punch is used as the minute punch, the punch is not limited to this and a square or polygon punch may be used. In that case, the inner shape of the hole is similar to the outer shape of the punch.

【0009】また、接合金属材料としてAuSnを用い
たがこれに限定されず、例えばPbSn、AuSi等で
も良い。
Although AuSn is used as the joining metal material, it is not limited to this and may be PbSn, AuSi, or the like.

【0010】[0010]

【発明の効果】以上述べた通り、形状、重量ともに同等
な微少接合バンプを再現性良く形成することができるた
め、実装歩留まりを向上できる。
As described above, since the minute bonding bumps having the same shape and weight can be formed with good reproducibility, the mounting yield can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を示す概略図である。FIG. 1 is a schematic diagram showing a first embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 微小ポンチ 2 ダイス 3 AuSn箔 4 シリコン基板 5 Auパット 6 微少AuSnバンプ 1 Micro Punch 2 Dice 3 AuSn Foil 4 Silicon Substrate 5 Au Pad 6 Micro AuSn Bump

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 微小ポンチとダイスとを用いてリボン状
の接合金属を打ち抜き、基板状に微小接合バンプを形成
する光素子用基板の製造方法において、前記ダイスの穴
形状が穴入口で広く出口で狭くなっていることを特徴と
する光素子用基板の製造装置。
1. A method of manufacturing a substrate for an optical element in which a ribbon-shaped bonding metal is punched out by using a minute punch and a die to form a minute bonding bump in a substrate shape. A device for manufacturing a substrate for an optical element, which is narrowed by.
JP4311844A 1992-11-20 1992-11-20 Optical device substrate manufacturing equipment Expired - Lifetime JPH0773108B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4311844A JPH0773108B2 (en) 1992-11-20 1992-11-20 Optical device substrate manufacturing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4311844A JPH0773108B2 (en) 1992-11-20 1992-11-20 Optical device substrate manufacturing equipment

Publications (2)

Publication Number Publication Date
JPH06163555A JPH06163555A (en) 1994-06-10
JPH0773108B2 true JPH0773108B2 (en) 1995-08-02

Family

ID=18022089

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4311844A Expired - Lifetime JPH0773108B2 (en) 1992-11-20 1992-11-20 Optical device substrate manufacturing equipment

Country Status (1)

Country Link
JP (1) JPH0773108B2 (en)

Also Published As

Publication number Publication date
JPH06163555A (en) 1994-06-10

Similar Documents

Publication Publication Date Title
EP1561142B1 (en) Optical communications module and substrate for the same
US7703993B1 (en) Wafer level optoelectronic package with fiber side insertion
KR100441810B1 (en) Electronic device to align light transmission structures
JP2629435B2 (en) Manufacturing method of sub-substrate for arrayed optical element
US4501637A (en) LED having self-aligned lens
US6825065B2 (en) Method for optical module packaging of flip chip bonding
US6393171B2 (en) Optical module for optical transmission and manufacturing process therefor
JP2005094016A (en) Packaging of optoelectronic device with hermetically sealed cavity and integrated optical element
JP4969775B2 (en) Optical device package having reflector and alignment post
US6249627B1 (en) Arrangement for self-aligning optical fibers to an array of surface emitting lasers
US5360761A (en) Method of fabricating closely spaced dual diode lasers
JPH0773108B2 (en) Optical device substrate manufacturing equipment
JPH0773107B2 (en) Method for manufacturing optical element substrate
JPH11326662A (en) Optical planar circuit
JP3056513B2 (en) Optoelectronic converter
JPH02154208A (en) Parallel transmission optical module
JPH03184384A (en) Optical module submount and manufacture thereof
JPH04221912A (en) Parallel transmission light module
JP2616550B2 (en) Optical module
JPH0758149A (en) Method for mounting chip part
JPH06283536A (en) Solder bump packaging substrate
JPH10223690A (en) Optical element mounting method
Sasaki et al. Self-aligned assembly technology for laser diode modules using stripe-type AuSn solder bump flip-chip bonding
JPH07174941A (en) Optical element coupling module for optical communication and its production
JPH05152605A (en) Arrayed optical element and mounting board thereof

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19960123

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070802

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080802

Year of fee payment: 13

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080802

Year of fee payment: 13

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090802

Year of fee payment: 14

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090802

Year of fee payment: 14

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100802

Year of fee payment: 15

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110802

Year of fee payment: 16

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110802

Year of fee payment: 16

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120802

Year of fee payment: 17

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130802

Year of fee payment: 18

EXPY Cancellation because of completion of term
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130802

Year of fee payment: 18