JPH0770997B2 - Phase comparator - Google Patents

Description

The present invention relates to a phase locked loop (PLL), and more particularly to a phase comparator which is one of the components of the phase locked loop.

〔Overview〕

The present invention detects a phase difference between an input signal and a voltage controlled oscillator (VCO) output signal, and in a phase comparator in a phase locked loop having means for outputting a control signal, delays the input signal in multiple stages, From these delayed output signals, two delayed output signals having different delay times are selected and a logical operation is performed to generate a pulse output signal having a predetermined pulse width, and this pulse output signal and the output signal of the voltage controlled oscillator are By providing means for comparing the phases of the above and outputting a signal proportional to the phase difference as the control signal, the loop gain of the phase locked loop can be changed without switching the switch.

[Conventional technology]

Conventionally, as shown in FIG. 7, a phase locked loop of an optical disk device or the like is composed of a phase comparator 11, a low-pass filter 12 and a voltage controlled oscillator (VCO) 13, and an input signal due to a defect of the medium or the like. With respect to the phase shift of 201, the up signal 210 or the down signal 211 from the phase comparator 11 changes the characteristics of the low-pass filter 12 to change the loop gain of the system to prevent the synchronization shift.

[Problems to be solved by the invention]

The phase locked loop using the conventional phase comparator described above,
The phase comparator 11 detects a phase shift, and the up signal 210 or the down signal 211 output drives a field effect transistor or an analog switch for controlling the filtering characteristic of the low-pass filter 12, By changing the value of the resistor or the capacitor forming the low-pass filter 12, the characteristics are changed to prevent the synchronization deviation. Therefore, the phase comparator 11 needs to be complicated and highly accurate, and if the switching noise of the field effect transistor or the analog switch is large, the switching noise causes a synchronization shift.

It is an object of the present invention to provide a phase comparator which can be simply configured by changing the loop gain of a phase locked loop using the same by eliminating the above drawbacks and which can prevent the generation of switching noise. .

[Means for solving problems]

The present invention relates to a phase comparator in a phase locked loop including a phase comparison circuit for detecting a phase difference between an input signal and an output signal of a voltage controlled oscillator and outputting a control signal, wherein each delay time is based on the input signal. A delay circuit for outputting a plurality of delayed output signals delayed only by the above, and a first selection circuit for selecting and outputting one delayed output signal from the plurality of delayed output signals in accordance with a selection signal from the outside. A second selection circuit for selecting and outputting a delayed output signal delayed from the delayed output signal selected by the first selection circuit according to the external selection signal; and the first selection circuit. And a pulse output circuit for outputting a pulse output signal having a pulse width based on the delayed output signal from the second selection circuit and the phase comparison circuit, For performing a logical product operation on the basis of the pulse output signal from the voltage circuit and the output signal from the voltage controlled oscillator, and correcting the phase shift between the resulting input signal and the output signal from the voltage controlled oscillator. A circuit means for outputting a phase error signal as the control signal is provided.

[Action]

According to the present invention, a delay circuit generates a delayed output signal in which an input signal is delayed in multiple stages, the first and second selection circuits select different delayed output signals, and a pulse output circuit outputs these two delayed outputs. A pulse output signal having a predetermined pulse width is obtained by performing a predetermined logical operation with respect to. Then, a signal proportional to the phase difference between this pulse output signal and the output signal of the voltage controlled oscillator is output as a control signal. Therefore, the pulse width of the control signal can be arbitrarily changed by arbitrarily changing the pulse width of the pulse output signal by selecting the delayed output signal, and thus the gain of the phase locked loop can be arbitrarily changed without switching the switch. Can be changed to.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Delayed output signal 102 by delaying input signal 101 in multiple stages
A delay line 1 as a delay circuit for outputting ~ 108 and one of the delay output signals 102-108 under the control of select signals 109-111, and a first selection for outputting a select output signal 115. The delayed output signal 102 is arranged so as to be delayed from the selector 2 as a circuit and the select output signal 115 of the selector 2.
To 108 are selected under the control of the select signals 112 to 114, and the selector 3 as the second selection circuit that outputs the select output signal 116, the select output signal 115,
An AND gate 5 which performs a logical product of the select output signal 116 and the select inverted output signal 117 which is inverted by the inverter 4 and outputs a pulse output signal 118 having a prescribed pulse width;
An AND gate 7 that outputs an up signal 121 that is an output signal proportional to the phase difference by taking the logical product of the pulse output signal 118 and the VCO output signal 119 that is the output of a voltage controlled oscillator (VCO) (not shown). , Pulse output signal 118 and VCO
VCO inverted output signal obtained by inverting output signal 119 with inverter 6.
AND gate 8 which outputs a down signal 122 which is an output signal proportional to the phase difference by taking a logical product with 120
Includes and. Inverter 4 and AND gate 5
Form a pulse output circuit, and the inverter 6 and AND gates 7 and 8 form a phase comparison circuit.

The feature of the present invention resides in that in FIG. 1, a delay line 1, selectors 2 and 3, inverters 4 and 6, and AND gates 5, 7 and 8 are provided.

Next, the operation of this embodiment will be described with reference to FIGS. 2 to 7 and tables. FIG. 2 shows the pulse output signal 11
When 8 is the pulse width 1 / 2T and 3 / 4T, the operation timing chart of FIG. 1 is shown. In FIG. 3, the pulse output signal 118 is the pulse width 1 / 2T.
Fig. 4 shows the phase comparison characteristics of the pulse output signal 118
Is a phase comparison characteristic diagram when the bus width is 3 / 4T, FIG. 5 is an operation timing diagram when the pulse output signal 118 has a phase shift when the pulse width is 1 / 2T, and FIG. 6 shows the pulse output signal 118. The operation timing chart and table when there is a phase shift when the pulse width is 3 / 4T show the relationship between the select output of the selectors 2 and 3 and the select signal.

In FIG. 2, assuming that the pulse width of the output signal 101, that is, the high level width is T and the low level width is an integral multiple of T, the delay line 1 delays the input signal 101 by 1 / 8T and outputs the delayed output signal 102. Delayed output signal 103 that is output and sequentially delayed by 1 / 8T
It outputs ~ 108. First select signals 109, 110 and 111
Are low level, high level and low level respectively, the selector 2 outputs the delayed output signal 103 as the select output signal 115, and the select signal 112, When 113 and 114 are low level, high level and high level, respectively, the selector 3 outputs the delayed output signal 107 as the select output signal 116, so that the AND gate 5 outputs the select output signal 115 and the select output signal 116 by inversion. The logical product of a certain select inversion output signal 117 is calculated and a pulse output signal 118 having a pulse width of 1/2 T is output. And gate 7 outputs pulse output signal 118 and VCO output signal.
AND gate 119 outputs the up signal 121 having a pulse width of 1 / 4T when synchronized, and the AND gate 8 outputs the VCO inverted output signal which is the inversion of the pulse output signal 118 and the VCO output signal 119.
The logical product with 120 is taken, and if synchronized, the down signal 122 having a bus width of 1 / 4T is output.

The phase comparison characteristic at this time is a triangular wave characteristic as shown in FIG. 3, and referring to FIG. 5, both the up signal 121 and the down signal 122 have a pulse width of 1 / 4T when they are synchronized.
, The phase error output is relatively “0”,
When the phase of the input signal 101 is deviated by ± π / 2, the pulse width of the up signal 121 or the down signal 122 becomes 1 / 2T, and the pulse width of the down signal or the up signal on the opposite side becomes 0T. It is relatively “1” or “−1”.

Next, when the select signals 109, 110 and 111 are high level, low level and laurel, respectively, the selector 2 outputs the delayed output signal 102 as the select output signal 115, and the select signals 112, 113 and 114 are high level, respectively. At the high level and the high level, the selector 3 outputs the delayed output signal 108 as the select output signal 116, so that the AND gate 5 outputs the select output signal 115.
The AND output of the select output signal 116, which is the inversion of the select output signal 116, is output, and the pulse output signal 118 having a pulse width of 3 / 4T is output.
AND the VCO output signal 119, and outputs the up signal 121 with a pulse width of 3 / 8T if the AND gate 8
Takes a logical product of the pulse output signal 118 and the VCO inversion output signal 120 which is the inversion of the VCO output signal 119, and outputs the down signal 122 having a pulse width of 3 / 8T if they are synchronized.

The phase comparison characteristic at this time is a trapezoidal wave characteristic as shown in FIG. 4, and referring to FIG. 6, when synchronized, the pulse width of both the up signal 121 and the down signal 122 is 3 / 8T. And the phase error output is relatively “0”. If the phase of the input signal deviates ± π / 2, the pulse width of the up signal 121 or the down signal 122 becomes 1 / 2T.
Since the pulse width of the down signal 121 or the up signal 122 on the opposite side is 1 / 8T and -1 / 8T, the phase error output is relatively "1/2" or "-1/2" (actually, Is ± π / 4 and the phase error output is relatively ± 1/2.).

In FIG. 1, the delay output signal of the delay line 1 is shown as seven, but the number of output signals is set as necessary. As a matter of course, the number of input lines and the number of select signals of the selectors 2 and 3 are set by the number of delayed output signals of the delay line 1.

Further, as shown in Table 1, when the select signals 109 to 111 or 112 to 114 are all at the low level, the select output signal 115 or 116 is at the low level. Since the up signal 121 and the down signal 122 become low level when the select output signal 115 becomes low level, it is assumed that this phase comparator is in the reset state at this time.

Although not shown in FIG. 1 but only in FIG. 2, select signals 109-111 and 112-114 are shown.
The change in the value of is synchronized with the falling edge of the delayed output signal 108.

〔The invention's effect〕

As described above, according to the present invention, by appropriately selecting the delayed output signal from the delay circuit with the selector to change the pulse width of the pulse output signal and changing the phase error output,
There is an effect that the loop gain of the phase synchronization circuit can be easily changed at any time without causing switching noise and the phases can be synchronized.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Figure 2 shows that the pulse width of the pulse output signal 118 is 1 / 2T and 3/4.
FIG. 3 is an operation timing chart of FIG. 1 when T is set. FIG. 3 is a phase comparison characteristic diagram when the pulse width of the pulse output signal 118 is 1 / 2T. FIG. 4 is a phase comparison characteristic diagram when the pulse width of the pulse output signal 118 is 3 / 4T. FIG. 5 is an operation timing chart of FIG. 1 when there is a phase shift when the pulse width of the pulse output signal 118 is 1 / 2T. FIG. 6 is an operation timing chart of FIG. 1 when there is a phase shift when the pulse width of the pulse output signal 118 is 3 / 4T. FIG. 7 is a block diagram showing the configuration of a phase locked loop (PLL). 1 ... Delay line 2, 3 ... Selector, 4, 6 ... Inverter, 5, 7, 8 ... AND gate, 11 ... Phase comparator, 12 ... Low-pass filter, 13 ... Voltage Controlled oscillator, 101, 2
01 …… input signal, 102-108 …… delayed output signal, 109-114
...... Select signal, 115,116 …… Select output signal, 11
7, 120 …… VCO inverted output signal, 118 …… Pulse output signal,
119,202 …… VCO output signal, 121,210 …… Up signal, 1
22, 211 …… Down signal, 203 …… Control signal.

Claims (1)

[Claims] 1. A phase comparator in a phase locked loop including a phase comparison circuit for detecting a phase difference between an input signal and an output signal of a voltage controlled oscillator and outputting a control signal, wherein each delay is based on the input signal. A delay circuit that outputs a plurality of delayed output signals delayed by time, and a first selection circuit that selects and outputs one delayed output signal from the plurality of delayed output signals according to a selection signal from the outside. A second selection circuit for selecting and outputting a delayed output signal delayed from the delayed output signal selected by the first selection circuit according to the selection signal from the outside, and the first selection A pulse output circuit that outputs a pulse output signal having a pulse width based on the delayed output signal from the circuit and the delayed output signal from the second selection circuit, the phase comparison circuit comprising: To perform a logical product operation based on the pulse output signal from the pulse output circuit and the output signal from the voltage controlled oscillator, and correct the phase shift between the resulting input signal and the output signal from the voltage controlled oscillator. 2. A phase comparator comprising circuit means for outputting the phase error signal of 1. as the control signal.