JPH0770664B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0770664B2 JPH0770664B2 JP62306458A JP30645887A JPH0770664B2 JP H0770664 B2 JPH0770664 B2 JP H0770664B2 JP 62306458 A JP62306458 A JP 62306458A JP 30645887 A JP30645887 A JP 30645887A JP H0770664 B2 JPH0770664 B2 JP H0770664B2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- lead frame
- bonding
- bumped
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法に係り、特に、半導体
素子（チップ）のリードフレームへの実装に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to mounting a semiconductor element (chip) on a lead frame.
リードフレームと半導体素子（チップ）との接続方式
は、ワイヤを用いるワイヤボンディング方式と、ワイヤ
を用いることなく半導体素子を導体パターン面に直接固
着するワイヤレスボンディング方式とに大別される。The connection method between the lead frame and the semiconductor element (chip) is roughly classified into a wire bonding method using a wire and a wireless bonding method in which the semiconductor element is directly fixed to the conductor pattern surface without using the wire.
これらのうちワイヤボンディング方式は、第３図に示す
ようなリードフレームのダイパッド１に、第４図に示す
如くチップ２を熱圧着によりあるいは導電性接着剤等に
より固着し、このチップ２のボンディングパッドとリー
ドフレームのインナーリード３の先端とを金線等を用い
て電気的に接続するもので、１本ずつ接続するためボン
ディングに要する時間が長く信頼性の面でも問題があっ
た。Of these, the wire bonding method is one in which a chip 2 is fixed to a die pad 1 of a lead frame as shown in FIG. 3 by thermocompression bonding or a conductive adhesive as shown in FIG. And the tip of the inner lead 3 of the lead frame are electrically connected by using a gold wire or the like, and since they are connected one by one, the time required for bonding is long and there is a problem in reliability.
また、ワイヤレスボンディング方式にもいろいろな方式
があるが、その代表的なものの１つに第５図に示す如く
高価なポリイミドテープに銅箔を貼り付けてその後エッ
チングして成るTAB（タブ:Tape Automated Bonding）用
パターンを前もって作っておき、このパターンの先端の
バンプ5aをチップ６のボンディングパッド6aに接続し、
続いてパターン５の他端のパッドのないリードフレーム
のインナーリード７の先端に接続することによりチップ
６のインナーリード７とを電気的に接続するダンプ式ボ
ンディング方式（バンプ付TAB方式）がある。上記ダン
プ式ボンディングは、ワイヤボンディングのように１本
づつボンディングするのではなく、チップに全てのリー
ドの先端を１度にボンディングすることができるため、
ボンディング時間の大幅な短縮を図ることができる。し
かしながら、高価なテープを使用してTAB用パターンを
作らなければならず、またTAB用パターンをチップのボ
ンディングパッドとインナーリードの先端の２箇所で接
続しなければならないため、工程数が多い上、ボンディ
ングの信頼性の低下の原因となっていた。There are various wireless bonding methods, one of which is a TAB (Tape Automated Tape) formed by attaching copper foil to expensive polyimide tape as shown in Fig. 5 and then etching. Bonding) pattern is made in advance, and the bump 5a at the tip of this pattern is connected to the bonding pad 6a of the chip 6,
Next, there is a dump-type bonding method (TAB method with bumps) in which the other end of the pattern 5 is electrically connected to the inner lead 7 of the chip 6 by connecting to the tip of the inner lead 7 of the lead frame having no pad. The above-mentioned dump-type bonding can bond the tips of all the leads to the chip at once, instead of bonding one by one like wire bonding.
The bonding time can be greatly shortened. However, since the TAB pattern must be made using expensive tape and the TAB pattern must be connected at two points, the chip bonding pad and the tip of the inner lead, the number of steps is large and This has been a cause of deterioration in the reliability of bonding.
そこで、本発明者らは上記ダンプ式ボンディングにおけ
る問題点を解決し、実装が容易で信頼性の高い半導体装
置を提供すべくインナーリードの先端に、インナーリー
ドよりも薄くかつその先端にバンプを有したパターンを
一体形成してなるリードフレームを提案している。Therefore, in order to solve the problems in the dump-type bonding and to provide a semiconductor device that is easy to mount and has high reliability, the present inventors have a tip thinner than the inner lead and a bump at the tip. We propose a lead frame formed by integrally forming the above pattern.
ところで従来このようなリードフレームの製造に際して
は、アウターリードの成形後インナーリード形成予定部
先端を薄板状に形成し、更にこの後インナーリードおよ
び肉薄のバンプ付パターンをエッチングにより形成する
という方法がとられている。By the way, conventionally, in the production of such a lead frame, there is a method in which after forming the outer lead, the tip of the inner lead formation scheduled portion is formed into a thin plate shape, and then the inner lead and the thin bumped pattern are formed by etching. Has been.
すなわち、第６図（ａ）および（ｂ）に示す如く、プレ
ス加工によってリードフレームのアウターリード10を形
成する際、インナーリード形成予定部先端12が臨む箇所
にスリット状の逃げ窓14を形成する。ここで、第６図
（ｂ）は第６図（ａ）のＣ−Ｃ断面を示す図である。That is, as shown in FIGS. 6A and 6B, when the outer lead 10 of the lead frame is formed by press working, a slit-shaped escape window 14 is formed at a position facing the tip 12 of the inner lead formation scheduled portion 12. . Here, FIG. 6 (b) is a view showing a cross section taken along line CC of FIG. 6 (a).
続いて、第６図（ｃ）に示す如く、上記インナーリード
形成予定部先端12をコイニングによって薄くし薄肉部16
を形成する。なお、前記逃げ窓14は、コイニングの際
に、素材の延びる空間を確保するためのものである。Then, as shown in FIG. 6 (c), the tip 12 of the portion where the inner lead is to be formed is thinned by coining to make a thin portion 16
To form. The escape window 14 is for securing a space in which the material extends during coining.
この後、第６図（ｄ）および第６図（ｅ）に示す如く
（第６図（ｅ）は第６図（ｄ）のＢ−Ｂ断面図）、薄肉
部16の斜線で示した部分22をエッチングによって除去す
ることにインナーリード18およびバンプ付パターン20を
形成する。After this, as shown in FIGS. 6 (d) and 6 (e) (FIG. 6 (e) is a cross-sectional view taken along the line BB of FIG. 6 (d)), the thin-walled portion 16 is shown by hatching. Inner leads 18 and bumped patterns 20 are formed by removing 22 by etching.
更に、通常はボンディング性を高めるために第６図
（ｆ）に示す如くバンプ20aの表面には金等の貴金属メ
ッキ層20bが形成されリードフレームが完成する。Further, usually, in order to improve the bonding property, a noble metal plating layer 20b of gold or the like is formed on the surface of the bump 20a to complete the lead frame as shown in FIG. 6 (f).
そして、このリードフレームを使用して半導体装置を製
造する場合には、第７図に示すように、まずフィルムキ
ャリア８にチップ２を固着し、続いてフィルムキャリア
をリードフレーム上に搬送しチップ２のボンディングパ
ッド2aとインナーリード18の先端のバンプ付パターン20
のバンプ20aとが当接するように両者を接続する。When a semiconductor device is manufactured using this lead frame, as shown in FIG. 7, the chip 2 is first fixed to the film carrier 8, and then the film carrier is conveyed onto the lead frame and the chip 2 is transferred. Pattern 20 with bumps at the tips of the bonding pads 2a and inner leads 18
The bumps 20a are connected to each other.
このようなリードフレームを用いることにより、高価な
テープを使用してバンプ付パターンを作るという工程、
このパターンの他端をインナーリードの先端に接続する
工程等を省略することができる。また接続箇所を低減で
きることによりボンディングの信頼性の向上を図ること
も可能である。By using such a lead frame, a step of making a bumped pattern using an expensive tape,
The step of connecting the other end of this pattern to the tip of the inner lead can be omitted. Further, it is possible to improve the reliability of bonding by reducing the number of connection points.
しかしながら、バンプ付きパターンは極めて薄く形成さ
れるため、リードフレームの形成工程において変形し易
く特にメッキ工程や搬送工程において変形し易い。また
実装に際しても変形による位置ずれが生じ易く、チップ
のボンディングパッドからずれる等のボンディング不良
を生じ易いという問題があった。However, since the bumped pattern is formed to be extremely thin, it is easily deformed in the lead frame forming step, particularly in the plating step and the carrying step. In addition, there is a problem in that when mounting, a positional shift is likely to occur due to deformation, and a bonding defect such as displacement from a chip bonding pad is likely to occur.
本発明は前記実情に鑑みてなされたもので、肉薄のバン
プ付パターンの変形を防止し、信頼性の高い半導体装置
を提供することを目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a highly reliable semiconductor device that prevents deformation of a thin bumped pattern.
そこで本発明の方法では、インナーリードの先端に一体
形成される肉薄のバンプ付パターンの先端部が互いに連
結するように連結部を形成しておき、ボンディング終了
後に、前記連結部を切除するようにしている。Therefore, in the method of the present invention, the connecting portion is formed so that the tip portions of the thin pattern with bumps integrally formed at the tip of the inner lead are connected to each other, and the connecting portion is cut off after the bonding is completed. ing.
望ましくは、リードフレームの連結部は、バンプ付きパ
ターンの先端に各パターンに対して垂直となるように一
体的に連結するリング状体であることを特徴とする。Desirably, the connecting portion of the lead frame is a ring-shaped body integrally connected to the tip of the bumped pattern so as to be perpendicular to each pattern.
さらに望ましくは、リードフレーム形成工程は、リード
フレームの連結部と前記パターンとの境界に切除用の溝
を形成する工程を含むことを特徴とする。More preferably, the lead frame forming step includes a step of forming a cutting groove at a boundary between the connecting portion of the lead frame and the pattern.
上記方法によれば、バンプ付パターンは肉薄であるにも
かかわらず、バンプ付パターンの先端が互いに補強固定
されているため、バンプ付パターンの間隔のずれ等が防
止され、精度良くボンディングすることが可能となり信
頼性が向上する。According to the above method, although the bumped pattern is thin, the tips of the bumped pattern are reinforced and fixed to each other, so that the gaps in the bumped pattern are prevented from shifting and the bonding can be performed accurately. It is possible and reliability is improved.
また、この連結部は肉薄であるため、切除も容易であ
り、実装作業性が向上する。Further, since the connecting portion is thin, it can be easily cut off, and the mounting workability is improved.
そして、何等付加工程を要することなく高精度で信頼性
の高い半導体装置を提供することができる。Then, a highly accurate and highly reliable semiconductor device can be provided without any additional process.
またバンプの部分でチップに固着された状態で、引っ張
り力がかかる際、バンプはパターンに一体的に形成され
ているため、その隣接領域で容易に切断され得、連結部
の切除が容易である。Further, when the bump portion is fixed to the chip, when the tensile force is applied, the bump is formed integrally with the pattern, so that it can be easily cut in the adjacent region, and the connection portion can be easily cut off. .
さらに、リードフレームの連結部を前記バンプ付きパタ
ーンの先端に各パターンに対して垂直となるように一体
的に連結するリング状体で構成することにより連結部を
切除するに際し、リング状体を引っ張ればよく、極めて
作業性よく実装することができる。Furthermore, the connecting part of the lead frame is integrally connected to the tip of the bumped pattern so as to be perpendicular to each pattern, so that the ring-shaped body is pulled when the connecting part is cut off. It can be implemented easily and with extremely good workability.
望ましくは、この連結部はバンプ付パターンの先端に各
パターンに対して垂直となるように一体的に連結するリ
ング状体とし、これとバンプ付パターンとの境界部に切
欠を形成しておくようにすれば、極めて容易に切除する
ことができる。Desirably, the connecting portion is a ring-shaped body integrally connected to the tip of the bumped pattern so as to be perpendicular to each pattern, and a notch is formed at the boundary between the bumped pattern and the bumped pattern. If so, it can be excised very easily.
以下、本発明の実施例について図面を参照しつつ詳細に
説明する。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第１図（ａ）および（ｂ）は、本発明実施例の方法で用
いられるリードフレームを示す図である。ここで第１図
（ｂ）は第１図（ａ）のＡ−Ａ断面を示す図である。1 (a) and 1 (b) are views showing a lead frame used in the method of the embodiment of the present invention. Here, FIG. 1 (b) is a view showing an AA cross section of FIG. 1 (a).
このリードフレームは、各インナーリード18の先端に夫
々一体形成された肉薄のバンプ付パターン20の先端を連
結する肉薄のリング状体30を更に一体形成してなるもの
で、他は第６図（ｄ）に示した従来のリードフレームと
同様である。なお、第６図（ｄ）と同一の構成部材には
同一記号を付した。This lead frame is formed by further integrally forming a thin ring-shaped body 30 that connects the ends of thin bumped patterns 20 integrally formed on the ends of the inner leads 18, respectively. This is the same as the conventional lead frame shown in d). The same components as those in FIG. 6 (d) are designated by the same symbols.
このリング状体30は、中央に形成された支持パターン31
から４方に延設された補助パターン32を一体的に具備し
ており、バンプ付パターン20の先端との境界には切欠33
が形成されて、支持パターン31に引っ張り力を与えるこ
とにより、切欠33の部分から切り離すことができるよう
になっている。The ring-shaped body 30 has a support pattern 31 formed in the center.
The auxiliary pattern 32 extending in four directions is integrally provided, and the notch 33 is provided at the boundary with the tip of the bumped pattern 20.
Is formed so that the support pattern 31 can be separated from the notch 33 by applying a tensile force to the support pattern 31.
このリードフレームの製造に際しては、第６図（ａ）乃
至第６図（ｆ）と共に示した従来の方法と全く同様にす
ればよいが、インナーリード18およびバンプ付パターン
20をエッチングによって形成する際、エッチング用マス
クを変更し、リング状体30および切欠33をも同時に形成
するようにする。The lead frame may be manufactured in the same manner as the conventional method shown in FIGS. 6 (a) to 6 (f), but the inner lead 18 and the bumped pattern are used.
When forming 20 by etching, the etching mask is changed so that the ring-shaped body 30 and the notch 33 are also formed at the same time.
次に、このリードフレームを用いた半導体装置の実装方
法について説明する。Next, a method of mounting a semiconductor device using this lead frame will be described.
まず、フィルムキャリア８上に半導体チップ２を載置し
てリードフレーム上まで搬送し、第２図（ａ）に示す如
く、半導体チップ２のボンディングパッド2aと各バンプ
付パターン20とが符合するように位置決めを行ないボン
ダーＢによってバンプ付パターン20を加熱しつつ押圧し
直接接合する。このときボンダーＢがバンプ付パターン
20を加熱押圧している間に、反対側から支持パターン31
に引っ張り力を与えてリング状体をバンプ付パターン20
の先端から切除し、バンプ付パターン20を個々にに分割
した後、ボンダーＢがバンプ付パターンから離れるよう
にする。First, the semiconductor chip 2 is placed on the film carrier 8 and conveyed to the lead frame, so that the bonding pads 2a of the semiconductor chip 2 and the bumped patterns 20 match each other as shown in FIG. 2 (a). Then, the pattern 20 with bumps is heated and pressed by the bonder B while being directly bonded. At this time, the bonder B has a bumped pattern
While heating and pressing 20, support pattern 31 from the opposite side
Pattern 20 with bumps
Of the bumped pattern 20 is divided into individual pieces, and the bonder B is separated from the bumped pattern.
そして最後に、タイバーおよびサイドバーを切除し、所
望の形状に曲げ成形した後、樹脂ケースＰ内に封止し、
第２図（ｂ）に示す如く半導体装置が完成される。And finally, the tie bar and the side bar are cut off, bent and formed into a desired shape, and then sealed in the resin case P,
A semiconductor device is completed as shown in FIG.
このようにして形成された半導体装置はボンディングの
位置ずれもなく、極めて信頼性の高いものとなる。The semiconductor device formed in this manner has extremely high reliability without any displacement in the bonding position.
また、連結部としてのリング状体は肉薄でかつ各バンプ
付パターンの１辺を切り離せば切除できるため、実装作
業性も極めて良好である。Further, the ring-shaped body as the connecting portion is thin and can be cut off by cutting off one side of each bumped pattern, so that the mounting workability is also very good.
なお、実施例では連結部をリング状に形成したが、形状
および連結箇所については適宜変更可能である。In addition, although the connecting portion is formed in a ring shape in the embodiment, the shape and the connecting portion can be appropriately changed.
以上説明してきたように、本発明の方法によれば、イン
ナーリードの先端に一体形成される肉薄のバンプ付パタ
ーンの先端部が互いに連結するように連結部を形成して
おき、ダンプ式ボンディング法により直接ボンディング
の終了後に、前記連結部を切除するようにしているた
め、位置ずれもなく極めて信頼性の高い半導体装置を形
成することが可能となる。As described above, according to the method of the present invention, the connecting portion is formed in advance so that the tip portions of the thin bumped pattern integrally formed at the tip of the inner lead are connected to each other, and the dump-type bonding method is performed. Thus, since the connecting portion is cut off after the direct bonding is completed, it is possible to form a highly reliable semiconductor device without positional displacement.
また、製造作業性も極めて高いものとなる。In addition, manufacturing workability is also extremely high.
第１図（ａ）および第１図（ｂ）は、本発明実施例の方
法で用いられるリードフレームの平面図および断面図、
第２図（ａ）および第２図（ｂ）は第１図のリードフレ
ームを用いた本発明の半導体装置の製造工程図、第３図
乃至第５図は、従来のボンディング方式を示す説明図、
第６図（ａ）乃至第６図（ｆ）は、本発明者らの作成し
た従来のリードフレームの製造工程図、第７図は、第６
図で形成したリードフレームを用いた実装工程を示す説
明図である。 １……ダイパッド、2,6……チップ、2a……ボンディン
グパッド、3,7,18……インナーリード、5a……バンプ、
８……フィルムキャリア、10……アウターリード、12…
…インナーリード形成予定部先端、14……逃げ窓、20…
…バンプ付パターン、20a……ハンプ、30……リング状
体、31……支持パターン、32……補助パターン、33……
切欠、Ｂ……ボンダー。1 (a) and 1 (b) are a plan view and a sectional view of a lead frame used in the method of the embodiment of the present invention,
2 (a) and 2 (b) are manufacturing process diagrams of a semiconductor device of the present invention using the lead frame of FIG. 1, and FIGS. 3 to 5 are explanatory diagrams showing a conventional bonding method. ,
6 (a) to 6 (f) are manufacturing process drawings of a conventional lead frame prepared by the present inventors, and FIG.
It is explanatory drawing which shows the mounting process using the lead frame formed in the figure. 1 ... die pad, 2,6 ... chip, 2a ... bonding pad, 3,7,18 ... inner lead, 5a ... bump,
8 ... Film carrier, 10 ... Outer lead, 12 ...
… Tip of inner lead formation planned part, 14… Escape window, 20…
… Bumped pattern, 20a… Hump, 30… Ring-shaped body, 31… Support pattern, 32… Auxiliary pattern, 33 ……
Notch, B ... Bonder.
Claims (3)
ドよりも薄くかつその先端にバンプを有すると共に先端
を同じ肉厚の連結部によって互いに連結されてあるダン
プ式ボンディング用のバンプ付きパターンを一体的に形
成したリードフレームを形成するリードフレーム形成工
程と、 前記リードフレームの前記バンプ付きパターンに対し半
導体チップを直接接合するボンディング工程と、 前記リードフレームの連結部を切除し各パターンを分離
する分離工程とを含むことを特徴とする半導体装置の製
造方法。1. A bumped pattern for dump-type bonding is integrally formed at the tip of each inner lead, which has a bump thinner than the inner lead and is connected to each other by a connecting portion having the same thickness. A lead frame forming step of forming a lead frame formed on the lead frame; a bonding step of directly bonding a semiconductor chip to the bumped pattern of the lead frame; and a separating step of cutting off the connecting portion of the lead frame to separate each pattern. A method of manufacturing a semiconductor device, comprising:
付きパターンの先端に各パターンに対して垂直となるよ
うに一体的に連結するリング状体であることを特徴とす
る特許請求の範囲第１項記載の半導体装置の製造方法。2. The connecting portion of the lead frame is a ring-shaped body integrally connected to the tip of the bumped pattern so as to be perpendicular to each pattern. A method of manufacturing a semiconductor device according to the item.
レームの連結部と前記パターンとの境界に切除用の溝を
形成する工程を含むことを特徴とする特許請求の範囲第
１項記載の半導体装置の製造方法。3. The semiconductor device according to claim 1, wherein the lead frame forming step includes a step of forming a cutting groove at a boundary between the connecting portion of the lead frame and the pattern. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62306458A JPH0770664B2 (en) | 1987-12-03 | 1987-12-03 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62306458A JPH0770664B2 (en) | 1987-12-03 | 1987-12-03 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01147847A JPH01147847A (en) | 1989-06-09 |
| JPH0770664B2 true JPH0770664B2 (en) | 1995-07-31 |
Family
ID=17957250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62306458A Expired - Fee Related JPH0770664B2 (en) | 1987-12-03 | 1987-12-03 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770664B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01305552A (en) * | 1988-06-03 | 1989-12-08 | Dainippon Printing Co Ltd | Lead frame |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5326480B2 (en) * | 1972-05-11 | 1978-08-02 |
-
1987
- 1987-12-03 JP JP62306458A patent/JPH0770664B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01147847A (en) | 1989-06-09 |
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