JPH0767098B2 - Multiplexing circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexing circuit, and more particularly to a multiplexing circuit for an optical communication terminal station.

[0002]

2. Description of the Related Art In recent years, an optical fiber transmission system using an optical fiber as a transmission medium (hereinafter referred to as "optical communication") has been developed in recent years due to its inherent high speed and large capacity due to its wide band property and the progress of optical fiber and optical element technology. , Is developing more and more. Optical communication handles a large amount of data, so multiple relatively low-speed data
For example, it is common to multiplex eight channels and transmit data as one multiplexed channel. Therefore, the terminal equipment in the optical communication terminal equipment has as its basic component an N / 1 multiplexer that multiplexes the data of the plurality (N) channels to generate the data of one multiplexed channel. This N / 1 multiplexer is basically a parallel-serial conversion circuit, and the high-speed data of one multiplexed channel with respect to the low-speed data of N channels has a bit rate of N times. The frequency of the high-speed clock corresponding to the high-speed data with respect to the low-speed clock is also N times as high.

These N-channel low-speed data input from the outside are asynchronous with respect to the high-speed / low-speed clocks for the multiplexing process inside the multiplexer. For the purpose of synchronization between the two, for example, in the past, for example, in the 1992 United States, "IEE CUSTOM INTEG (Custom Integrated Circuit Conference)" was published.
RATED CIRCUITS CONFERENCE)
29.4-1.29.4.4 page article "10Gb
/ S Silicon Bipolar 8: 1 Multiplexer and 1: 8 Demultiplexer (10Gb / S
Silicon Bipolar Multiplexe
r and Demultiplexer) ", the phase of the low-speed clock for multiplexing processing obtained by dividing the high-speed clock is adjusted by a variable phase shifter to obtain a phase-synchronized clock that is a low-speed clock for phase synchronization of data. It was generated and the low-speed data was phase-synchronized by using this phase-locked clock.

As shown in FIG. 5, a conventional multiplexing circuit of this type includes an 8: 1 multiplexer 6 for multiplexing low-speed data D1 to D8 of 8 channels to generate multiplexed data DO of 1 channel. , 8-channel low speed data D1 to D for optical transmission of communication data supplied from a communication device lower than the terminal device
The low-speed data conversion circuit 3 for converting to 8 and the high-speed clock for phase-shifting the phase-shifted divide-by-8 clock CO supplied from the multiplexer 6 with the phase of the low-speed clock CL supplied from the low-speed data conversion circuit 3 as a reference. A phase locked loop (PLL) 7 that outputs CH and a phase shifter 5 that adjusts the phase of the high-speed clock CH and outputs a phase-shifted high-speed clock CV are provided.

The multiplexer 6 includes flip-flops F11-F18 for latching low-speed data D1-D8, and flip-flops F11, F1 for four channels, respectively.
5, F13, F17 and F12, F16, F14, F
18 output data f11, f15, f13, f1
7 and f12, f16, f14, and f18, multiplexed circuits 11 and 12 for outputting multiplexed data DQ1 and DQ2 of four channels, respectively, and two multiplexed data DQ.
1, a multiplexer circuit 13 for further multiplexing DQ2 and outputting multiplexed data DP of 8 channels, a flip-flop 14 for latching the multiplexed data DP and retiming with a phase shift high-speed clock CV, and supply of outputs from the flip-flop 14. In response to the supply of the high-speed clock CH, the buffer 15 which outputs the multiplexed data DO and the divided-by-2 clock CX, the divided-by-2 clock CX is divided into two, and the divided-by-4 clock CY is divided by four. Counters 16 and 1 for further dividing CY by 2 and outputting the divided clock CZ by 8 respectively
Received 7 and 18 and CZ divided by 8 clock and 180 °
It includes a phase shifter 24 that shifts (inverts) a phase, and a buffer 25 that receives the output of the phase shifter 24 and outputs the inverted frequency-divided clock CO of 8.

The low-speed data conversion circuit 3 includes a data conversion unit 31 for converting the communication data into low-speed data D1 to D8,
A clock source 32 for generating a low speed clock CL.

Referring to FIG. 6 showing the configuration of the multiplex circuit 11 of the same multiplex circuits 11 and 12, the multiplex circuit 11 parallel-serial converts input data for two channels into one channel by using a clock CZ. Two 2: 1 multiplex circuits 111 and 112 to be multiplexed, and a 2: 1 multiplex circuit 113 which further multiplexes the outputs of the multiplex circuits 111 and 112 into one channel by using the clock CY and outputs multiplexed data DQ1.
With. The multiplexing circuit 111 receives the signals f11 and f15 and outputs the data k15, and the multiplexing circuit 112 receives the data f13 and f17 and outputs the data k37. Similarly, the multiplexing circuit 121 of the multiplexing circuit 12 outputs the data f
12, k16 is supplied to the multiplexing circuit 112 in accordance with the supply of f12 and f16.
Outputs k48 according to the supply of the data f14 and f18.

Referring to FIG. 7 showing the configuration of the PLL 7,
This PLL 7 is a phase comparator 7 that compares the phase of the low-speed clock CL and the inverted frequency-divided clock CO of 8 and outputs an error signal.
1, a low-pass filter 72 that receives the error signal and smoothes it to convert it into a DC error voltage, and a voltage controlled oscillator (VCO) 73 whose frequency is controlled by the error voltage. Equipped with.

Next, the operation of the conventional multiplexing circuit will be described. The low-speed data conversion circuit 3 converts the communication data supplied from the communication device subordinate to the terminal device into low-speed data D1 to D8 synchronized with the clock CL, and supplies the low-speed data D1 to D8 to the multiplexer 6. On the other hand, the PLL 7 controls the VCO 73 by an error voltage obtained by comparing the phase of the inverted frequency-divided clock CO by the phase comparator 71 with the clock CL as a reference, smoothing the error signal of the comparison result by the low pass filter 72, and the low speed clock. A high-speed clock CH having a frequency eight times that of CL is output.
Since the clock CO is obtained by dividing the clock CH by eight, the clock CL and the clock CO are stabilized in a phase-synchronized state. The clock C is used for this synchronization.
The reason why the inverted frequency-division clock CO of which Z is phase-shifted by 180 ° is used is to optimize the phase relationship between the low-speed data D1 to D11 input to the flip-flops 11 to 18 and the latch clock CZ.

Referring to FIG. 8 showing a time chart in the synchronous state of the clocks CL and CO, the low speed data D1
~ The cross point of D8 and the rising edge of the low-speed clock CL are output in the same phase (in-phase), and at the same time, the clock C is output.
O has the same frequency of the same phase, clocks CH, CX and CY have frequencies of 8 times, 4 times and 2 times that of the same phase, respectively, and clock CZ has the same frequency of the opposite phase.

Referring to FIG. 9 showing a time chart of the parallel-serial conversion operation of the multiplexer 6, the low speed data D1 and D5 are divided by 8 by the flip-flops F11 and F15.
Are respectively latched by and are held as data f11 and f15. The multiplexing circuit 111 is supplied with the data f11 and f15 and receives the data f1 during the "H" level of the clock CZ.
1 produces data k15 which outputs data f15 during the "L" level. Similarly, the multiplexing circuit 112 is supplied with the data f13 and f17, the data f13 during the "H" level of the clock CZ, and the data f1 during the "L" level.
The data k37 for outputting 7 is generated. next,
The multiplexing circuit 112 receives the data k15 and k37, performs similar parallel-serial conversion by the clock CY, and outputs the data DQ1. Multiplexer 12 of Multiplexer 12
The data f12, f16,
Similar parallel-serial conversion is performed on f14 and f18, and the data DQ2 is output. The multiplexing circuit 13 uses these data D
Similar parallel-serial conversion is performed by the clock CX according to the supply of Q1 and DQ2, and the data DP is output. The data DP is high-speed data obtained by parallel-serial converting the low-speed data D1 to D8 into 8: 1. The flip-flop 14 latches this data DP, adjusts the timing by the clock CV generated by adjusting the phase of the clock CH by the phase shifter 5, and outputs it as the data DO via the buffer 15.

[0012]

In the conventional multiplexing circuit described above, the low-speed clock for low-speed data synchronization and the high-speed clock divided by 8 are synchronized by using the PLL. The VCO, which is the main component of the PLL, is expensive, and it is difficult to make it monolithic in the high frequency band. Further, there is a drawback that the phase of the clock divided by 8 must be adjusted.

[0013]

The multiplexing circuit of the present invention comprises:
A clock source that generates a first clock having a predetermined cycle, a low-speed data conversion circuit that supplies the low-speed data in synchronization with the first clock, and each of the low speeds in synchronization with the first clock. Eight data latch means for latching data, and a second clock having the same cycle as the first clock
, And a third clock having a half cycle of the first clock, the predetermined output data of the four data latch means are parallel-serial-converted to perform 4: 1 multiplexing. The output data of the first and second 4: 1 multiplexing circuits and the output data of the first and second 4: 1 multiplexing circuits are synchronized with the fourth clock having a half cycle of the third clock. And 2: 1 multiplexing circuit for parallel-to-serial conversion to perform 2: 1 multiplexing. 8 channels of low-speed data supplied in parallel are converted to 1-channel serial high-speed data to 8: 1. In a multiplexing circuit for multiplexing
Means for multiplying the clock of No. 8 by 8 to generate a fifth clock, and a cascade for sequentially resetting the fifth clock by 2 by a reset pulse to divide the fifth clock by two to generate the fourth, third and second clocks. Connected first, second and third frequency divider circuits, and a reset for generating the reset pulse having a predetermined pulse width in synchronization with the rising of the fifth clock after the rising of the first clock. And means.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the multiplexing circuit of the present invention.

As shown in FIG. 1, the multiplexer circuit of this embodiment multiplexes low-speed data D1 to D8 of 8 channels similarly to the conventional multiplexer 6 to multiplex data DO of 1 channel.
8: 1 multiplexer 1, low-speed data conversion circuit 3 similar to the conventional one, and phase shifter 5, and a multiplier 4 that multiplies the low-speed clock CL by 8 to generate a high-speed clock CH.
With.

The multiplier 4 constitutes an 8-multiplier by cascading the 2-multipliers shown in FIG. 2 in three stages. Referring to FIG. 2, the doubler includes a low-pass filter 41 for removing high-frequency components of the supplied clock CL, a full-wave rectifier circuit 42 for full-wave rectifying the output of the low-pass filter 41, and a full-wave rectifier circuit. The comparator 43 is provided with the output of 42 as the positive phase input and the reference voltage VR as the negative phase input.

The multiplexer 1 includes flip-flops F11 to F18 similar to the conventional multiplexer 6 and multiplexing circuits 11, 12,
13, the flip-flop 14, the buffer 15, and the flip-flops F15, F17, F16, F1.
Flip-flops F25, F27, F26, F28 which latch the respective data of 8 again with the clock CL and output the data f15, f17, f16, f18, and the counters 16-18, which are reset by the reset signal R and are reset at high speed. In response to the supply of the clock CH, the frequency-divided clock CX is divided into two, and the clock CX is divided into two and the frequency-divided clock CY is divided into four.
, The clock CY is further divided by 2, and the clock is divided by 8 CZ
And a reset circuit 22 for supplying a reset pulse R to the counters 19, 20, 21 in response to the supply of the clocks CL, CH.
An inverter I11 that inverts the clock CH to output the clock ICH, inverts the clock CZ to output the clock ICZ, and inverts the clock CL to output the clock ICL, respectively.
I12 and I13 are provided.

Referring to FIG. 3, the reset circuit 22 includes a flip-flop 221 to which a data terminal d is supplied with a clock CL and a clock terminal c is supplied with a clock ICH, and output terminals q and iq output signals s and t, respectively.
The signal s is sent to the data terminal d and the clock IC is sent to the clock terminal c.
A flip-flop 221 to which H is supplied and a signal u is output from the output terminal q, and a NAND gate 223 that performs a NAND operation of the signals t and s and outputs a reset pulse R are provided.

Next, the operation of the multiplexing circuit of this embodiment will be described.

The low speed clock CL from the clock source 32 is supplied to the data converter 31 as in the conventional example, and the reset circuit 22 and the inverter I13 of the multiplexer 1 are also provided.
To the multiplier 4. A multiplier 4, which is a three-stage cascade connection of two multipliers, multiplies the clock CL by 8 to generate a high-speed clock CH. The doubler is a low-pass filter 41.
Full-wave rectification of the input signal via the full-wave rectification circuit 42,
By folding the negative potential side of the amplitude waveform of this input signal to the electrostatic potential side, a full-wave rectified signal in which the number of peaks of this waveform is doubled is supplied to the comparator 43. Comparator 43
Uses the level of this full-wave rectified signal as a threshold for the reference voltage VR to determine "H" and "L", and generates an output signal having a frequency twice that of the input signal. The clock CH is supplied to the inverter I11 and the phase shifter 5. Clock C
The clock ICH obtained by inverting H by the inverter I11 is supplied to the counter 19 and the reset circuit 22.

FIG. 4 is a time chart showing the phase relationship between the input data D1 to D8 of the multiplexer 1 and the clocks CL, ICH, CX, CY, CZ, ICZ, the reset pulse R, and the signals s, t, u. The cross points of the low speed data D1 to D8 and the rising edge of the low speed clock CL are output in the same phase (in phase). The flip-flop 221 of the reset circuit 22 responds to the supply of the clocks CL and ICH and outputs signals s and t having opposite phases at the rising edge of the clock ICH. Further, in response to the supply of the signal s and the clock ICH, the flip-flop 222 outputs the signal u, and the NAND gate 223 outputs the reset pulse R as the NAND output of these signals t and u. This reset pulse R
While the counters 19 to 21 are in the reset state during the "H" level, the clocks CX, CY and CZ from the respective counters are "H".
It is fixed at L "level. When the reset pulse R becomes" L "level, the reset state is released and the counter 19 to
21 restarts the frequency division operation, and the supply of the clocks CX, CY, CZ is started. Reset pulse R is clock CL
Occurs at the rising phase of the clock ICH after the rising of the clock CL, the phase difference α between the clock CL and the clocks CX, CY, CZ is always a constant value, and therefore the clock CL and the clocks CX, CY, CZ are in phase. It will be in sync.

On the other hand, the general operation of the multiplexer 1 of this embodiment is the same as that of the conventional multiplexer 6, and the description thereof will be omitted so that it is not redundant except the one directly connected to the present invention described later.

Multiplexing circuit 111,1 of multiplexing circuit 11,12
Since the clock ICZ supplied to 12, 121 and 122 has the cross point of the data f11 to f18 and the phase difference α, the data f15, f17, f16 and f18 supplied during the "L" level of the clock CL are data. Of the data f11, f13, f12, and f14 supplied during the "H" level so that the change point of
Flip-flop F2 for delaying a half cycle of L
5, F27, F26, F28.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made. For example, instead of the two flip-flops in the reset circuit, a monostable multivibrator triggered by a low-speed clock is used, and the reset time is controlled by a time constant determined by a capacitance value and a resistance value. Of course, it can be applied unless deviated.

[0026]

As described above, the multiplexing circuit of the present invention has a multiplying means for multiplying a low speed clock by 8 to generate a high speed clock, and a high speed clock which is reset by a reset pulse and sequentially divides the high speed clock by two. Since there are provided three-stage frequency dividing circuits for generating the divided-by-2, divided-by-4 and divided-by-8 clocks, and reset means for generating the reset pulse synchronized with the rise of the high-speed clock after the rise of the low-speed clock. , P for phase synchronization using an expensive VCO
There is an effect that the LL circuit becomes unnecessary and the monolithic structure can be easily obtained. Further, there is an effect that the phase adjustment of the clock divided by 8 which is conventionally required is not necessary.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a multiplexing circuit of the present invention.

FIG. 2 is a block diagram showing a configuration of a multiplication circuit of FIG.

FIG. 3 is a block diagram showing a configuration of a reset circuit of FIG.

FIG. 4 is a time chart showing the phase relationship of clocks in the multiplexing circuit of the present embodiment.

FIG. 5 is a block diagram showing an example of a conventional multiplexing circuit.

FIG. 6 is a block diagram showing a configuration of a multiplexing circuit.

7 is a block diagram showing the configuration of the PLL of FIG.

FIG. 8 is a time chart showing a phase relationship of clocks in a conventional multiplexing circuit.

FIG. 9 is a time chart showing an example of operation in a conventional multiplexing circuit.

[Explanation of symbols]

1,6 Multiplexer 3 Low-speed data conversion circuit 4 Multiplier 5,24 Phase shifter 7 PLL 11, 12, 13, 111, 112, 113, 121,
122,123 Multiplexing circuit 14,221,222, F11 to F18, F25, F2
7, F26, F28 Flip-flop 15, 25 Buffer 16-18, 19-21 Counter 22 Reset circuit 31 Data conversion unit 32 Clock source 41, 72 Low-pass filter 42 Full-wave rectifier circuit 43 Comparator 71 Phase comparator 73 VCO 223 NAND Gate I11 to I13 Inverter

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mamoru Kikuchi 3-20-4 Nishishimbashi, Minato-ku, Tokyo NEC Engineering Co., Ltd. (72) Inventor Hiroyuki Nakamura 1-403 Kosugicho, Nakahara-ku, Kawasaki-shi, Kanagawa No. 53 NEC IC Microcomputer System Co., Ltd.

Claims (2)

[Claims] 1. A clock source for generating a first clock having a predetermined cycle, a low-speed data conversion circuit for supplying the low-speed data in synchronization with the first clock, and a low-speed data conversion circuit for synchronizing with the first clock. Using eight data latch means for latching each of the low-speed data, a second clock having the same period as the first clock, and a third clock having a half period of the first clock. First and second 4: 1 multiplexing circuits for parallel-serial converting the output data of each of the four predetermined data latching means, and 1/2 of the third clock. A 2: 1 multiplexing circuit for parallel-serial converting the output data of the first and second 4: 1 multiplexing circuits in synchronization with the fourth clock of the cycle , 8 channels of low speed data supplied in parallel And parallel-to-serial conversion in series of high-speed data of 1 channel 8: 1
In a multiplexing circuit for multiplexing the first clock and the fifth clock by multiplying the first clock by 8 to generate a fifth clock; 4, 1st, 2nd and 3rd frequency divider circuits connected in cascade for generating 4th, 3rd and 2nd clocks, and in synchronization with the rise of the 5th clock after the rise of the 1st clock. A multiplexing circuit comprising: reset means for generating the reset pulse having a predetermined pulse width. 2. A first flip-flop in which the reset means has a data input terminal supplied with the first clock and a clock input terminal supplied with the fifth clock, and a data input terminal with the first flip-flop. Of the positive-phase output of the second flip-flop to which the fifth clock is supplied to the clock input terminal, and the NAND of the output of the second flip-flop and the negative-phase output of the first flip-flop The multiplexing circuit according to claim 1, further comprising a logic circuit for performing an operation.