JPH0766964B2 - Method for manufacturing vertical field effect transistor - Google Patents
Method for manufacturing vertical field effect transistorInfo
- Publication number
- JPH0766964B2 JPH0766964B2 JP62007796A JP779687A JPH0766964B2 JP H0766964 B2 JPH0766964 B2 JP H0766964B2 JP 62007796 A JP62007796 A JP 62007796A JP 779687 A JP779687 A JP 779687A JP H0766964 B2 JPH0766964 B2 JP H0766964B2
- Authority
- JP
- Japan
- Prior art keywords
- field effect
- region
- vertical field
- effect transistor
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000005669 field effect Effects 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000000034 method Methods 0.000 title claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 230000001133 acceleration Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 23
- 239000011229 interlayer Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、縦型電界効果トランジスタの製造方法に関
し、特にオン抵抗を低減できる縦型電界効果トランジス
タの製造方法に関する。The present invention relates to a method for manufacturing a vertical field effect transistor, and more particularly to a method for manufacturing a vertical field effect transistor capable of reducing on-resistance.
従来の縦型電界効果トランジスタの製造方法を第４図
（ａ），（ｂ）により説明する。まず第４図（ａ）に示
すように、N+型半導体基板１上にN-エピタキシャル層２
を成長し、エピタキシャル層２表面に酸化膜４を介して
低エネルギーイオン注入帯３を設けオン抵抗の低減をは
かっていた。その後チャネル部となるＰ層領域９更にそ
の外側にN+拡散領域を設けソースN+領域とする。次にこ
れらのソースN+領域を短絡するアルミニウムのソース電
極11を設けると共にＰ層領域９の表面に絶縁膜を介して
ゲート電極６を設けることにより、第３図（ｂ）に示す
縦型電界効果トランジスタが得られる。なお、７は層間
絶縁膜である。A conventional method for manufacturing a vertical field effect transistor will be described with reference to FIGS. 4 (a) and 4 (b). First, as shown in FIG. 4 (a), the N − epitaxial layer 2 is formed on the N + type semiconductor substrate 1.
Was grown and a low energy ion implantation zone 3 was provided on the surface of the epitaxial layer 2 through the oxide film 4 to reduce the on-resistance. After that, an N + diffusion region is provided further outside the P layer region 9 which will be the channel portion to serve as a source N + region. Next, by providing an aluminum source electrode 11 for short-circuiting these source N + regions and providing a gate electrode 6 on the surface of the P layer region 9 via an insulating film, the vertical electric field shown in FIG. An effect transistor is obtained. Reference numeral 7 is an interlayer insulating film.
上述した従来の縦型電界効果トランジスタではオン抵抗
を下げるために10〜100KeVの低エネルギーイオン注入の
ため表面濃度のみが高くなり、均一な濃度領域が形成し
にくいという欠点がある。The conventional vertical field effect transistor described above has a drawback in that only a surface concentration is increased due to low energy ion implantation of 10 to 100 KeV in order to reduce ON resistance, and it is difficult to form a uniform concentration region.
本発明の目的は、ベース−ベース間の表面のみの濃度を
向上させるだけでなく、均一な濃度分布の基板と同一導
電型の不純物領域を形成し、オン抵抗を低減できる縦型
電界効果トランジスタの製造方法を提供することにあ
る。An object of the present invention is to provide a vertical field effect transistor capable of not only improving the concentration only on the surface between bases but also forming an impurity region of the same conductivity type as that of a substrate having a uniform concentration distribution and reducing the on-resistance. It is to provide a manufacturing method.
本発明は、ドレイン領域を構成する一導電型のエピタキ
シャル層に逆導電型のベースが設けられ、該ベース内に
一導電型のソース領域が設けられ、該ベース上にゲート
が設けられ、基板の表面−裏面間に電流を流す縦型電界
効果トランジスタの製造方法において、前記エピタキシ
ャル層の選択的に限定された表面領域である前記ベース
間の領域に一導電型のイオンの超高エネルギーイオン注
入を行なって不純物濃度のピークが表面から離間した内
部に位置する濃度プロファイルを具備する一導電型の不
純物領域を形成する工程を有することを特徴とする縦型
電界効果トランジスタの製造方法にある。According to the present invention, a reverse conductivity type base is provided in a single conductivity type epitaxial layer forming a drain region, a single conductivity type source region is provided in the base, and a gate is provided on the base. In a method for manufacturing a vertical field effect transistor in which an electric current is passed between the front surface and the back surface, ultrahigh energy ion implantation of one conductivity type ion is performed in a region between the bases which is a selectively limited surface region of the epitaxial layer. A method of manufacturing a vertical field effect transistor, comprising the step of forming an impurity region of one conductivity type having a concentration profile in which the peak of the impurity concentration is located away from the surface.
なお。超高エネルギーイオン注入の工程は縦型電界効果
トランジスタの製造工程でゲート領域形成工程前か又は
多結晶シリコンゲート形成後の何れに行ってもよい。Incidentally. The ultra high energy ion implantation process may be performed either before the gate region formation process or after the polycrystalline silicon gate formation process in the vertical field effect transistor manufacturing process.
また、超高エネルギーイオン注入条件としてはイオン打
ち込みの加速電圧を0.1〜5MeVとすることにより効果的
に実施できる。Further, as an ultrahigh energy ion implantation condition, an ion implantation acceleration voltage of 0.1 to 5 MeV can be effectively performed.
次に、本発明の実施例について図面を参照して説明す
る。第１図（ａ），（ｂ）は本発明の一実施例を説明す
るために工程順に示した素子の断面図である。Next, embodiments of the present invention will be described with reference to the drawings. 1 (a) and 1 (b) are cross-sectional views of the device shown in the order of steps for explaining one embodiment of the present invention.
まず、第１図（ａ）に示すように、N+型半導体基板１に
N-エピタキシャル層２を成長し、N-エピタキシャル層２
の表面に酸化膜（SiO2）４を形成し、その酸化膜の上に
イオン注入カバー10（例えばアルミニウム）を形成し、
その上より、高エネルギーイオン注入（例えば0.1〜5Me
V）を行ないＮイオン注入層３を形成する。このように
して得られたＮイオン注入層を含む第１図（ａ）のAB間
の不純物濃度は第３図の濃度プロファイルＩに示すよう
になる。First, as shown in FIG. 1 (a), an N + type semiconductor substrate 1 is formed.
N - the growth of the epitaxial layer 2, N - epitaxial layer 2
An oxide film (SiO 2 ) 4 is formed on the surface of, and an ion implantation cover 10 (for example, aluminum) is formed on the oxide film,
In addition, high energy ion implantation (for example 0.1 ~ 5Me
V) is performed to form the N ion implantation layer 3. The impurity concentration between AB including the N ion-implanted layer thus obtained in FIG. 1 (a) is as shown in the concentration profile I in FIG.
次に、第１図（ｂ）に示すように、チャネル部となるＰ
層領域９、更にその外側にN+拡散領域を設けソースN+領
域８とする。次いでＰ層領域９の表面に絶縁膜（酸化
膜）４を介してゲート多結晶シリコンおよび層間絶縁膜
７を設け、次いでソース電極11を設けることにより本実
施例は完成する。Next, as shown in FIG.
A layer region 9 and an N + diffusion region outside the layer region 9 are provided as a source N + region 8. Then, the gate polycrystalline silicon and the interlayer insulating film 7 are provided on the surface of the P layer region 9 with the insulating film (oxide film) 4 interposed therebetween, and then the source electrode 11 is provided to complete the present embodiment.
第２図（ａ），（ｂ）は本発明の他の実施例を説明する
ために工程順に示した素子の断面図である。本実施例で
は第１の実施例と異なる点はＮイオン注入層の形成はゲ
ート多結晶シリコンを形成した後にイオン注入カバーを
形成して高エネルギーイオンを注入して形成する点であ
る。2 (a) and 2 (b) are sectional views of the device shown in the order of steps for explaining another embodiment of the present invention. The present embodiment is different from the first embodiment in that the N ion implantation layer is formed by forming gate polycrystalline silicon, then forming an ion implantation cover and implanting high energy ions.
すなわち、N+型半導体基板１にN-エピタキシャル層２、
チャネル部となるＰ層領域９、ソースN+領域８、酸化膜
４、ゲート多結晶シリコン６、層間絶縁膜７を形成した
後、アルミニウムのイオン注入カバー10を設け高エネル
ギーイオン注入（例えば0.1〜5MeV）を行うと0.5〜３μ
ｍに不純物濃度のピークを有するＮイオン注入層３を形
成できる。これによりオン抵抗の低減をはかることがで
きる。That is, the N + -type semiconductor substrate 1 N - epitaxial layer 2,
After the P layer region 9 serving as a channel portion, the source N + region 8, the oxide film 4, the gate polycrystalline silicon 6 and the interlayer insulating film 7 are formed, an aluminum ion implantation cover 10 is provided to perform high energy ion implantation (for example, 0.1 to 5 MeV) 0.5 ~ 3μ
It is possible to form the N ion implantation layer 3 having a peak of impurity concentration at m. This makes it possible to reduce the on-resistance.
なお、以上の説明はＮチャネル縦型電界効果トランジス
タについて説明したがＰチャネル縦型電界効果トランジ
スタについても同様の効果が得られる。Although the above description has been made with respect to the N-channel vertical field effect transistor, the same effect can be obtained with the P-channel vertical field effect transistor.
以上説明したように、本発明は、縦型MOSFETにおいて、
ベース−ベース間に、高エネルギー・イオン注入を行な
うことにより、ベース−ベース間のオン抵抗を低減し、
特性を改善することができる。またこのオン抵抗低減用
の不純物領域の不純物濃度のピークは表面から離間した
内部に位置しているから、表面の高濃度に依存すること
なく内部の高濃度に依存してオン抵抗の必要な低減をす
ることができる。したがって、表面の高濃度化を必要最
小限に抑えることができ、これにより耐圧値が不必要に
低下しすぎてしまうことや寄生容量が不必要に高すぎて
しまうことを回避することができる。さらにこの不純物
領域はエピタキシャル層の全表面にイオン注入を行なっ
て形成するのではなく、エピタキシャル層の選択的に限
定された表面領域であるベース間の領域にイオン注入を
行なって形成する。したがって不純物領域の形成がトラ
ンジスタのしきい値電圧に影響を及ぼして所定のしきい
値電圧を得ることが困難になるという不都合を回避する
ことができる。As described above, the present invention relates to a vertical MOSFET,
By performing high-energy ion implantation between the base and the base, the on-resistance between the base and the base is reduced,
The characteristics can be improved. Further, since the peak of the impurity concentration of the impurity region for reducing the on-resistance is located in the inside separated from the surface, the required reduction of the on-resistance does not depend on the high concentration of the surface but depends on the high concentration of the inside. You can Therefore, it is possible to suppress the concentration of the surface to a minimum, and thereby to prevent the breakdown voltage from unnecessarily decreasing too much and the parasitic capacitance from unnecessarily increasing. Further, this impurity region is not formed by implanting ions on the entire surface of the epitaxial layer, but is formed by implanting ions on the region between the bases, which is a selectively limited surface region of the epitaxial layer. Therefore, it is possible to avoid the inconvenience that the formation of the impurity region affects the threshold voltage of the transistor and it becomes difficult to obtain a predetermined threshold voltage.
Ｎ層は、エネルギー量により、濃度のピーク距離を変化
させることができ、コントロールの自由度がある。The N layer can change the peak distance of concentration depending on the amount of energy, and has a degree of freedom in control.
第１図（ａ），（ｂ）及び第２図（ａ），（ｂ）はそれ
ぞれ本発明の第１及び第２の実施例を説明するために工
程順に示した素子の断面図、第３図は本発明の第１の実
施例のドレイン領域の濃度プロファイル図、第４図
（ａ），（ｂ）は従来の縦型トランジスタの製造方法の
一例を説明するために工程順に示した素子の断面図であ
る。 １……N+半導体基板、２……N-エピタキシャル層、３…
…Ｎイオン注入層、４……酸化膜、５……イオン注入、
６……多結晶シリコンゲート、７……層間絶縁膜、８…
…ソースN+領域、９……Ｐ層領域、10……イオン注入カ
バー。FIGS. 1 (a) and (b) and FIGS. 2 (a) and (b) are cross-sectional views of an element shown in order of process for explaining the first and second embodiments of the present invention, respectively. The figure shows a concentration profile diagram of the drain region of the first embodiment of the present invention, and FIGS. 4 (a) and 4 (b) show the element in the order of steps for explaining an example of the conventional method of manufacturing a vertical transistor. FIG. 1 ... N + semiconductor substrate, 2 ... N - epitaxial layer, 3 ...
… N ion implantation layer, 4 …… oxide film, 5 …… ion implantation,
6 ... Polycrystalline silicon gate, 7 ... Interlayer insulating film, 8 ...
... Source N + region, 9 ... P layer region, 10 ... ion implantation cover.
Claims (4)
キシャル層に逆導電型のベースが設けられ、該ベース内
に一導電型のソース領域が設けられ、該ベース上にゲー
トが設けられ、基板の表面−裏面間に電流を流す縦型電
界効果トランジスタの製造方法において、前記エピタキ
シャル層の選択的に限定された表面領域である前記ベー
ス間の領域に一導電型のイオンの超高エネルギーイオン
注入を行なって不純物濃度のピークが表面から離間した
内部に位置する濃度プロファイルを具備する一導電型の
不純物領域を形成する工程を有することを特徴とする縦
型電界効果トランジスタの製造方法。1. A substrate of opposite conductivity type is provided in an epitaxial layer of one conductivity type constituting a drain region, a source region of one conductivity type is provided in the base, and a gate is provided on the base. In a method for manufacturing a vertical field effect transistor in which an electric current is passed between the front surface and the back surface of a substrate, the ultra high energy ion implantation of one conductivity type ion into a region between the bases which is a selectively limited surface region of the epitaxial layer. The method of manufacturing a vertical field effect transistor, comprising the step of performing the step of forming an impurity region of one conductivity type having a concentration profile in which the peak of the impurity concentration is located away from the surface.
ギーイオン注入の工程を行うことを特徴とする請求項
（１）記載の縦型電界効果トランジスタの製造方法。2. The method for manufacturing a vertical field effect transistor according to claim 1, wherein the step of implanting ultra-high energy ions is performed before forming the gate.
り、該多結晶シリコンゲートの形成後に、前記超高エネ
ルギーイオン注入の工程を行うことを特徴とする請求項
（１）記載の縦型電界効果トランジスタの製造方法。3. The vertical field effect according to claim 1, wherein the gate is a polycrystalline silicon gate, and the step of implanting the ultra-high energy ions is performed after the polycrystalline silicon gate is formed. Manufacturing method of transistor.
ち込みの加速電圧は0.1〜5MeVであることを特徴とする
請求項（１）記載の縦型電界効果トランジスタの製造方
法。4. The method of manufacturing a vertical field effect transistor according to claim 1, wherein an acceleration voltage for ion implantation of the ultra high energy ion implantation is 0.1 to 5 MeV.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62007796A JPH0766964B2 (en) | 1987-01-14 | 1987-01-14 | Method for manufacturing vertical field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62007796A JPH0766964B2 (en) | 1987-01-14 | 1987-01-14 | Method for manufacturing vertical field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63175478A JPS63175478A (en) | 1988-07-19 |
| JPH0766964B2 true JPH0766964B2 (en) | 1995-07-19 |
Family
ID=11675605
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62007796A Expired - Fee Related JPH0766964B2 (en) | 1987-01-14 | 1987-01-14 | Method for manufacturing vertical field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0766964B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0791965A3 (en) * | 1996-02-26 | 1998-09-16 | SILICONIX Incorporated | Vertical four terminal transistor |
| JP4440188B2 (en) * | 2005-01-19 | 2010-03-24 | パナソニック株式会社 | Manufacturing method of semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4593302B1 (en) * | 1980-08-18 | 1998-02-03 | Int Rectifier Corp | Process for manufacture of high power mosfet laterally distributed high carrier density beneath the gate oxide |
| GB2100507A (en) * | 1981-06-17 | 1982-12-22 | Philips Electronic Associated | Method of making a vertical igfet |
-
1987
- 1987-01-14 JP JP62007796A patent/JPH0766964B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63175478A (en) | 1988-07-19 |
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |