JPH0766677B2 - Writing device using writable / erasable storage medium - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a writing device that writes data that changes regularly such as the number of films of a camera to an erasable storage medium that writes data.

(Background of the Invention) In recent years, along with the computerization of cameras, various data such as the number of films is stored by an electric means and the data is controlled.
It is used for counting and displaying. As a medium for storing the data, there is an electrically writable and erasable semiconductor non-volatile memory EEPROM, which is capable of sustaining storage even if the power source is not backed up by a battery or the like. It can be said to be very effective.

However, since the time required for writing and erasing the EEPROM is relatively long, if the power supply is interrupted or interrupted during the writing or erasing of data, it is neither write data nor erase data. The data remains, and not only the data such as the number of films is displayed completely differently, but also the control of the system itself may be affected.

The writing condition of the EEPROM will be described by taking a conventional product as an example. For example, in the EEPROM of the Motorola MC68HC11 with a built-in microcomputer, there are the following write / erase restrictions (rules).

In the cleared state, all bits are 1 (high level).

Writing means charging the cells of the EEPROM with electric charges, and the writing bit changes from 1 to 0.

 Writing takes about 10 ms.

It is not allowed to write a further 0 to the bit that is being written, i.e. the bit that has a value of 0. (Overcharge prohibited) Erasure must be performed in 1-byte (BYTE) units.

 It takes about 10 ms to erase.

Erasing means discharging electric charge from the cells of the EEPROM, and the value changes from 0 to 1.

Further erasure of bits that have been erased, i.e. bits having a value of 1, is not allowed. (Prohibition of over-discharging) Due to the above restrictions, writing to EEPROM is performed with a slightly complicated algorithm. However, among the above eight conditions, the essence of the EEPROM is that the data cannot be rewritten unless it takes a relatively long time as compared with the RAM like the condition.

A conventional writing method that complies with the above constraint conditions will be described.

FIG. 7 is a memory map of the EEPROM. There are 4 bytes of memory of 8 bits = 1 byte, and their addresses are A0, A1, A
2, A3. This address shall be 4 consecutive bytes.
MSB is the most significant bit and LSB is the least significant bit.

Next, the case where the film count value is updated from $ 05 to $ 06 according to the order shown in FIG. 8 will be described as an example. The symbol $ means a hexadecimal number.

At time T1, data of $ 05 is written in the address A0, and the data of the addresses A1 to A3 are erased. Due to the constraint conditions, $ 05 of data is $ 00 at time T3.
And is cleared to $ FF at time T5, then time T7
Will be updated to $ 06. Times T2, T4, T6 are T1 → T3, T3 → T respectively
5, Shows the transitional state of T5 → T7.

A conventional example will be described at the bit level according to FIG. Times of Day
When changing the value from T1 to time T3, bit 0 and bit 2 are changed from 1 to 0 in order to change from $ 05 to $ 00. This process is done by writing $ FA, which is a $ 05 complement due to constraints. Also, it takes about 10 ms due to the constraint condition. Next, from time T3 to time T5, byte erase is performed according to the constraint condition. This also takes about 10ms due to the constraints. Time T5 to time T7
At, write $ 06. This is also about 10
It takes ms.

As described above, in order to change the value from $ 05 to $ 06, three processes were required over a total of about 30 ms in accordance with the above-mentioned constraint prohibition of overcharge and prohibition of overdischarge. In such a conventional example, in the middle of the time T2 to the time T6, if the power supply is interrupted or the microcomputer is reset and the rewriting process is interrupted, write data or erase data such as ??, 00, FF is written. I am left with odd data that is neither.

The EEPROM is technically still in the process of being improved. At the present time, the rewriting life is about 10,000 times and the writing time is on the order of 10 ms. Also, overcharge prohibition and overdischarge prohibition as seen in the EEPROM of MC68HC11 are prohibited. There are also many restrictions. In the conventional example, as a measure for the rewriting life, it corresponds by using the memory area of the EEPROM by using multiple bytes. For example, when using an area of n bytes,
After the first 1-byte area is used several times, the next byte is used to equalize the stress. Therefore, in the case of $ 05 → $ 06, all bits are stressed 3 times per rewriting, so if you use the n-byte area, x times of rewriting x times 3 / n It takes stress, and the rewriting time at that time is about 30 ms.

(Object of the Invention) An object of the present invention is to change from the interrupted state when the data rewriting / erasing operation is interrupted in the state before the data rewriting / erasing operation is completed due to interruption of the power supply during the data rewriting / erasing. It is an object of the present invention to provide a writing device capable of shifting to a completed state of data rewriting / erasing operation.

(Characteristics of the Invention) In order to achieve the above object, the present invention specifies a writable and erasable storage medium having a plurality of addresses, a writable address specified in a predetermined order, and an erasing address of a predetermined number of 2 or more. Addressing means for designating an address to which data is previously written, and data for a designated write address are changed according to a predetermined rule to rewrite the data with new data, and designated erasure is performed. It has a data writing / erasing means for erasing data by changing the data for the address according to a predetermined rule, and when writing new data, the writing address and the erasing address designated by the address designating means are set. In addition to causing the data transition by the data write / erase means, A determination means for determining the transition state of the data by the data write / erase means is provided based on the data of the designated write address and erase address, and the data rewrite / erasure is performed during the data rewrite / erase by the data write / erase means. When the erasing is interrupted, the data rewriting / erasing by the data writing / erasing means is completed according to the data transition state before the interruption judged by the judging means.

(Embodiment of the Invention) FIG. 1 is a block diagram showing a basic configuration of an embodiment of the present invention.

The data input unit 1 inputs regular data such as a film count value to the writing / erasing unit 2. A writable / erasable storage medium 3 such as an EEPROM has a plurality of addresses, for example, A0 to A3. The address designating unit 4 designates a write address in a predetermined order at the time of writing, and at the time of erasing, designates an address at which data is written a predetermined number of times 2 or more, for example, twice before as an erase address.

The rewriting process will be described with reference to the example of FIG. FIG. 2 shows the case where the data changes to $ 06 and is written to address A3.

When new data $ 06 is input from the data input means 1, the writing / erasing means 2 starts the rewriting process.
At this time, $ 05 has already been written to address A2 due to the previous write.
Is stored, and $ 04 is written in address A1 due to the writing two times before.
Is remembered. When writing this time, the address designating means 4 designates A3 as the writing address. The writing / erasing means 2 writes $ 06 in the designated address A3 from time T1 to time T3. After this writing, the address designating means 4 designates the address A1 written twice before as the erase address, and the writing and erasing means 2 writes the complement of $ 04 to the address A1 from the time T3 to the time T5. Rewrite from $ 04 to $ 00. Next, from time T5 to time T7, the byte of address A1 is erased to set it to $ FF.

By performing the above-mentioned writing, at any two times from time T1 to T7, at least two consecutive addresses are
Since the adjacent data is retained, even if the rewriting process is interrupted during the write operation, the time T1
Alternatively, if it is interrupted at T2, it can be determined as $ 05, and if it is interrupted at times T3 to T7, it can be determined as $ 06.

In the case of the writing method of FIG. 2, if the data is updated x times for n bytes, the stress of xx3 / n and the rewriting time of about 30 ms are enough. Compare with the case of the conventional example of FIG. Therefore, the required storage area, the amount of stress, and the rewriting time are the same.

FIG. 4 shows a specific example in which an embodiment of the present invention is realized in a film counter of a camera, and FIGS. 5 and 6 are flowcharts showing the operation.

The DC / DC converter connected to the battery Vbat is controlled by turning on the metering switch SW1.
When ▼ becomes low level, it starts up and DC power supply voltage Vcc is generated at its output terminal OUT. By applying this DC power supply voltage Vcc, the microcomputer μCOM starts up.
At the same time, the power-up clear circuit PUC applies a reset signal to the input port RESET of the microcomputer μCOM, and the microcomputer μCOM program starts.

Step 1: When the DC converter DC / DC rises, the microcomputer μCOM turns on the transistor TR1 by setting the output port OUT1 to the high level and holds the control terminal ▲ ▼ of the DC converter DC / DC at the low level.

Step 2: Microcomputer μCOM is AD converter AD,
Comprised of an arithmetic unit CPU and an EEPROM that is an electrically writable and erasable storage medium. By calling a film counter read subroutine, addresses A0 to A3 in the EEPROM
Capture the current correct film count value from the.
The correct film count value is input to the register RD of the arithmetic unit CPU and the next write address is input to the index register IX, respectively, and the film counter read subroutine returns.

Step 3: The microcomputer μ is used to determine whether the shutter charge or film feed charge has been terminated halfway due to removal of the battery Vbat, etc.
Charge switch connected to COM input port IN3
Take in the on / off state of SWcg and determine whether or not charging is complete. The charge switch SWcg is a switch that is turned off when the front curtain of the shutter is running, and is turned on when charging is completed as a result of rotation of the charge motor MTR that performs shutter charging and film feeding. As a result of the condition determination in this step, if the charging is not completed, the process proceeds to step 4 in order to charge. When the charge is complete, jump to step 9.

Step 9: The film count value stored in the register RD is output from the output port OUT4 to the display device DISP to display the film count.

Step 10: Logarithmic compression and IS of the signal from the photometric sensor SPC
Analog signal from photometric circuit CKT1 for O correction is converted to AD converter A
Captured in D and converted to digital signal.

Step 11: Exposure calculation is performed from the photometric value obtained in step 10, and shutter time Tv and aperture value Av are calculated.

Step 12: Release switch SW2 status is input port IN
Take in via 2, and proceed to step 13 when the release switch SW2 is on, and proceed to step 14 when it is off.

Step 14: Determine whether the metering switch SW1 is on or off.If it is off, proceed to step 15.If it is on, steps 10 to 12,1.
Repeat 4

Step 15: Turn off the transistor TR1 by setting the output port OUT1 to the low level, and turn on the DC / DC converter.
Down.

Step 13: A release sequence is entered by turning on the release switch SW2, and the exposure control circuit CKT2 drives the aperture AX and raises a main mirror (not shown). Further, the front curtain magnet MG1 is excited, and the shutter speed T
After the passage of v, excite the rear curtain magnet MG2.

At this time, the charge switch SWcg is turned off by the start of the first curtain, and the charge is incomplete.

Step 4: When exposure control ends, shutter charge,
For mirror down and film feeding, the microcomputer μCOM sends a signal from the output port OUT3 to the motor driver MD to drive the charge motor MTR.

Step 5: When the charge motor MTR rotates and all charging is completed, the charge switch SWcg is turned on and the process proceeds to step 6.

Step 6: The charge motor MTR is stopped when the charging is completed.

Step 7: Increment the film count value of the register RD.

Step 8: The incremented film count value
Call the write film counter subroutine to write to the EEPROM.

The above is the main flow of the camera system. Next, the film counter writing subroutine will be described with reference to FIG.

Step 44: Register RD contains the new film count value and index register IX contains the address of the EEPROM to be written next. Therefore, by writing the data in the register RD to the address designated by the index register IX, the processing from time T1 to T3 in FIG. 2 is performed.

Step 45: Wait for the writing time.

Step 35: The index register IX is moved back by 2, and the address to be erased is designated. Here, the decrement is performed twice and the AND with $ 3 is taken, but this is on the premise that the code number of address A0 is divisible by 4.

Step 36: The data at the address designated by the index register IX is transferred to the register RA in order to execute the processing from time T3 to T5 in FIG. Therefore, in the example of FIG.
Address A1 is the index register as the erase address
Specified by IX, data $ 04 at address A1 is loaded into register RA.

Step 37: Complement the register RA according to the constraint condition.

Step 38: Write the data in the register RA to the address specified by the index register IX. This realizes time T5.

Step 39: Wait for writing time.

Step 40: Byte erase is performed for the processing from time T5 to T7. This is the act of discharging one byte of the address specified by the index register IX.

Step 41: Wait for the erase time.

Step 42: The index register IX is incremented three times and ANDed with $ 3 in order to specify the address to be written next in the index register IX. This completes the writing and returns to the main flow.

Next, the film counter reading subroutine will be described.

Step 21: The film counter read subroutine is
In order to execute after the DC converter DC / DC rises, it is necessary to find out which address in the EEPROM contains the correct film count value. Therefore, the code number $ of the start address A0 is first stored in the index register IX.
Load 00. In this example, the code number of address A0 is set to $ 00, but if it is not $ 00,
It is necessary to add the code number of address A0 for all calculations of IX → IX AND $ 3.

Step 22: Load the data of the address specified by the index register IX into the register RA.

Step 23: Increment the index register IX to specify the next address.

Step 24: When the register RA is not $ FF, steps 22 to 24 are repeated until $ FF is found. When an address having $ FF is found, the process proceeds to step 25.

Step 25: Load the data of the address specified by the index register IX into the register RA.

Step 26: Increment the index register IX to specify the next address.

Step 27: When the register RA is $ FF, steps 25 to 27 are repeated until an address having non- $ FF data is found. When an address having non- $ FF data is found, the process proceeds to step 28.

Step 28: Load the data of the address specified by the index register IX into the register RB.

Step 29: Increment the index register IX to specify the next address.

Step 30: Load the data of the address specified by the index register IX into the register RC. by this,
After the rewriting process is interrupted at each of the times T1 to T7 in FIG. 2, the battery Vbat is replaced and the photometric switch SW
When the film counter read subroutine is executed by restarting the operation when 1 is turned on, each register R
Data is loaded into A, RB, and RC as shown in FIG.

Step 31: Start data analysis to read the correct film count value using the registers RA to RC. First, if the register RC is $ FF, this corresponds to the case of interruption at times T1 and T7, and the process proceeds to step 32.

Step 32: If interrupted at time T1, the correct film count value is $ 05; if interrupted at time T7, the correct film count value is $ 06. Therefore, the data in the register RB is transferred to the register RD, and the process returns to the main flow. This causes the correct film count value to enter register RD and the next EEPROM address to be written to index register IX.

Step 33: The case of NO in step 31 corresponds to the case of interruption at time T2 to T6. The difference between register RC and register RB is $
The case of 1 corresponds to the case of interruption at times T3 to T6, the correct film count value is $ 06, and it exists in the register RC. Therefore, if YES, the process proceeds to step 34.

Step 34: In order to transfer the correct film count value stored in the register RC to the register RD and clear the data of the address two times before to $ FF, the above-mentioned step 35 to
Executes 42 processes. As a result, the memory configuration at time T7 is realized, the rewriting state can be returned to the rewriting complete state, the correct film count value is stored in the register RD, and the address to be written next is stored in the index register IX. It

Step 43: The case of NO in step 33 corresponds to the case of interruption at time T2. At this time, the correct film count value should be $ 06. To achieve this, RD ← RB + $
1 is performed, that is, the calculation of $ 05 + $ 01 = $ 06 is performed and stored in the register RD. Then, in order to write $ 06, a step which is a film counter writing subroutine after this
Proceed to 44 and later. As a result, the data ?? remaining in the address A3 when interrupted at time T2 is rewritten to $ 06, and the address A1 is cleared to $ FF.

According to the algorithm shown above, data whose value changes regularly by 1 like a film counter is stored in the EEPROM.
Can be rewritten without error. That is, EEPR
Even if the rewriting is interrupted while rewriting the OM, the effective data store in the EEPROM with long writing time can be done by reading the data according to the above algorithm when reading the data next time.

In the illustrated embodiment, the increment data such as the film count value is used as the regular data,
Conversely, decrement data may be used. At this time, in step 33 of the film counter reading subroutine
The condition determination of RC-RB = $ 1 may be changed to RB-RC = $ 1 and step 43 may be changed to RD ← RB- $ 1.

In addition, both increment and decrement change the data by one, but even in a pattern in which the data changes by two, only step 33 and step 43 need be changed. If the previous data is D (n-1) and the current data is D (n), and if the values of the data have a regularity in a series, it can be applied in almost all cases by simply changing step 33 and step 43. . The data pattern is an arithmetic progression and is expressed as D (n) = D (n-1) + m. Step 33 is RC-RB = m. Step 43 is RD ← RB + m.

In the case of geometric progression, it is expressed as D (n) = m × D (n−1), step 33 is RC ÷ RB = m, and step 43 is RD ← m × RB.

If the regularity of the data is a power, it is expressed as D (n) = {D (n-1)} ^m , step 33 is RC = RB ^m, step 43 is RD ← RB ^m .

As described above, the present invention can be applied as an effective error-free data writing device to an EEPROM, which can be applied to almost any data having a change with mathematical regularity.

Therefore, the application range is not limited to the film counter of the camera, but can be applied to all related devices using the EEPROM. Further, as the storage medium pair, not only the EEPROM but also a memory using light, magnetism, and chemistry, such as a writable and erasable magneto-optical disk having a relatively long writing time, can be used.

Further, the reading is not limited to the means shown in FIG. 6, and various means can be adopted.

(Effect of the Invention) As described above, according to the present invention, when the data rewriting / erasing is interrupted during the execution of the data rewriting / erasing by the data writing / erasing means, the interruption judged by the judging means is interrupted. Since the data rewriting / erasing by the data writing / erasing means is completed according to the previous data transition state, before the data rewriting / erasing operation is completed due to the interruption of the power supply during the data rewriting / erasing, etc. When it is interrupted in the state, it is possible to shift from the suspended state to the completed state of the data rewriting / erasing operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of an embodiment of the present invention, FIG. 2 is a diagram showing an example of a rewriting process according to an embodiment of the present invention, and FIG. 3 is a data holding state at the time of reading. FIG. 4 is a block diagram showing a concrete structure of an embodiment of the present invention, FIG. 5 is a flow chart showing a main flow of operation of the concrete example shown in FIG. 4, and FIG. 6 is a concrete diagram shown in FIG. 7 is a flowchart showing a general memory map of an EEPROM, FIG. 8 is a diagram showing an example of a rewriting process according to a conventional example, and FIG. 9 is a rewriting process according to a conventional example. It is a figure which shows a bit level. 1 ... Data input means, 2 ... writing / erasing means, 3 ...
Storage medium, 4 ... Address designation means, .mu.COM ... Microcomputer, CPU ... Arithmetic unit, RA, RB, RC, RD ...
Register, IX Index register, A0, A1, A2, A
3 …… Address.

Claims (1)

[Claims] 1. A writable and erasable storage medium having a plurality of addresses, and an address for designating a write address in a predetermined order and for designating an address to which data is written as an erase address two or more times before a fixed number of times. Designating means and data for a designated write address are changed according to a predetermined rule to rewrite the data with new data, and data for a designated erase address is predetermined rule. The data write / erase means for erasing the data by changing the data in accordance with the data write / erase means for the write address and the erase address designated by the address designating means. And the specified write address and erase address. When the data rewriting / erasing is interrupted during the execution of the data rewriting / erasing by the data writing / erasing means, the determining means for determining the transition state of the data by the data writing / erasing means based on the data A writing apparatus using a writable / erasable storage medium, characterized in that the data rewriting / erasing by the data writing / erasing means is completed in accordance with the data transition state before the interruption determined by the determining means.