JPH0764502A - Pdp driving circuit - Google Patents

Abstract

PURPOSE:To improve picture quality with simple circuit constitution by adding weighted multi-valued errors of the peripheral piwels to an output objective pixel and storing the data making a gradation error between an input signal and a light emission luminance minimum in a ROM. CONSTITUTION:An error output obtained by an error detection circuit 35 is added to an h line delay circuit 36 and a (d) dot delay circuit 37, and the regenerative error is integrated into an original pixel video signal inputted to a video signal input terminal 30. The error detection circuit 35 is provided with a memory 38 storing the data with a corrected luminance level, a subtraction circuit 39 for obtaining an error output from a difference between an inputted diffused output signal and the data with the corrected luminance level in the memory 38 and weighting circuits 40, 41 weighting the h line delay data and the d dot delay data to the output of the subtraction circuit 39, and the error is integrated into an original video input signal and diffused, and a smooth response is obtained by the signal with the number of bits less than the original video input signal without lowering the light emission luminance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PDP driving circuit equipped with a circuit for processing such that a change in luminance gradation is continuously and naturally performed.

[0002]

2. Description of the Related Art Recently, as a thin and lightweight display device, P
Attention has been paid to DP (plasma display panel). This PDP driving method is completely different from the conventional CRT driving method and is a direct driving method using a digitized video input signal. Therefore, the brightness gradation emitted from the panel surface is determined by the number of bits of the signal to be handled. PDPs can be divided into two types, AC type and DC type, which have different basic characteristics. In DC type PDPs, there have been reports of improvement methods for brightness and life, which have already been issues, and progress toward practical application is being made. is there.

However, in the AC type PDP, although sufficient characteristics have been obtained in terms of brightness and service life, with regard to gradation display, only a maximum of 64 gradation display has been reported at the prototype level. A future 256-gradation method based on the die driving method (ADS subfield method) has been proposed. A panel structure of a PDP (plasma display panel) 10 used in this method is shown in FIG.
The drive sequence and drive waveforms are shown in FIGS.

In FIG. 7, an X sustain electrode 12 and a Y sustain electrode 13 which form a pair are formed on the lower surface of the surface glass substrate 11 on the display surface side by a transparent electrode and an auxiliary electrode. The auxiliary electrode forms the bus electrode 23 on a part of the transparent electrode in order to prevent a voltage drop due to the resistance of the transparent electrode. A dielectric layer 14 is provided on the X sustain electrode 12 and the Y sustain electrode 13, and a stripe rib 18 is formed on the dielectric layer 14 to separate the coupling between the cells. Further, a protective layer 15 made of a MgO film is deposited. Address electrodes 17 are formed on the back glass substrate 16 facing each other. The stripe-shaped ribs 18 on the stripes are provided between the address electrodes 17, and the address electrodes 17 are covered with R.
The (red) phosphor 19, the G (green) phosphor 20, and the B (blue) phosphor 21 are separately formed. In the discharge space 22, Ne +
Xe mixed gas is enclosed.

In FIG. 8A, one frame has a relative luminance ratio of 1, 2, 4, 8, 16, 32, 64, 128.
It is composed of 8 sub-fields, and 256 gradations are displayed by combining the brightness of 8 screens. Each subfield is composed of an address period for writing refreshed data for one screen and a sustain period for determining the luminance level of the subfield. In the address period, wall charges are initially formed in each pixel at the same time on the entire screen, and then sustain pulses are applied to the entire screen for display. The brightness of the subfield is proportional to the number of sustain pulses and is set to a predetermined brightness. In this way, 256 gradation display is realized.

[0006]

In the AC driving method as described above, as the number of gradations increases, the number of bits in the address period as the preparation period for lighting and emitting the panel within one frame period increases. The sustain period as a light emitting period becomes relatively short, and the maximum brightness decreases. In this way, the brightness gradation emitted from the panel surface is
Since it depends on the number of bits of the signal to be handled, if the number of bits of the signal to be handled is increased, the image quality is improved, but the light emission brightness is reduced. Conversely, if the number of bits of the signal to be handled is reduced, the light emission brightness is increased. The number of displays is reduced and the image quality is deteriorated.
Therefore, in the field of printing, electronic copying, etc., as a method of continuously and naturally changing the gradation with a small number of gradations-pseudo-halftone display-, research and development in which two gradations of white and black represent a halftone. Has been done and many schemes have been proposed. However, in the field of video, there is currently no definitive method for displaying pseudo-halftones of this kind.

According to the present invention, a simple circuit structure is achieved by adding to an output target pixel a multivalued error of its peripheral pixels and storing data in a ROM that minimizes a grayscale error between an input signal and emission luminance. The purpose is to achieve the purpose.

[0008]

According to the present invention, the error output obtained by the error detection circuit 35 is added to the h line delay circuit 36 and the d dot delay circuit 37, and this reproduction error is input to the video signal input terminal 30. In the PDP drive circuit adapted to be incorporated in the original pixel video signal, the error detection circuit 35
Is a memory 3 for storing the corrected brightness level data.
8, a subtraction circuit 39 for obtaining an error output from the difference between the diffused output signal input to the error detection circuit 35 and the corrected luminance level data of the memory 38, and the subtraction circuit 3
The output of 9 is provided with weighting circuits 40 and 41 for weighting h line delay data and d dot delay data.
It is a DP drive circuit.

[0009]

The emission luminance level for the drive signal is actually measured, a corrected luminance line represented by y = ax + b is obtained based on the measured line, and the corrected luminance line is expressed as {(corrected luminance line gradient a-1)- Corrected luminance line contact piece b} is corrected,
The memory 38 stores the stepwise data when the correction luminance line is corrected so that y = x. The correction luminance line is y
= X, the corrected luminance level is the same as the emission luminance level, so if the number of drive output bits is m, 2 m to the power, specifically, if m = 4, 2 4 = 16 words The data of the luminance level of 1 may be stored in the memory 38. In the above configuration, the difference between the diffusion output signal input to the error detection circuit 35 and the stepwise data of FIG. 4 from the memory 38 is subtracted by the subtraction circuit 39 to obtain the error output signal. This error output signal becomes an error weight output signal weighted by the weight circuits 40 and 41.
The error weight output from the input pixel is input to the h-line delay circuit 36, the reproduction error Ej-h generated in the past by h lines from the original pixel Ai, j is corrected, and the original pixel is Ai, j in the vertical direction addition circuit 31. The error weighted output from the weighting circuit 41 is input to the d dot delay circuit 37, and the reproduction error Ei− that occurs d dots earlier than the original pixel Ai, j.
d is corrected and incorporated in the original pixel Ai, j by the horizontal addition circuit 32. In this way, the original video input signal is diffused by incorporating an error, and a signal having a bit number smaller than that of the original video input signal allows a smooth response to be obtained without lowering the emission brightness.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a so-called error diffusion circuit. In this circuit, 30 is a video signal input terminal of an n-bit original pixel Ai, j, and this video signal input terminal 30 is a vertical direction addition circuit 31 and a horizontal direction addition circuit. After 32, the bit conversion circuit 33 further reduces the number of bits and is connected to the video output terminal 34. In addition, the horizontal direction addition circuit 32
An error detection circuit 35 is connected to the output side of. The error detection circuit 35 is a memory 38 that stores data of a preset correction error level, and a subtraction that outputs an error signal by taking the difference between the output of this memory 38 and the diffusion output signal from the horizontal direction addition circuit 32. The circuit 39 includes weight circuits 40 and 41 for outputting an error weight for weighting the error signal with a predetermined weight.

The load circuits 40, 4 of the error detection circuit 35
The output side of 1 is connected to the vertical direction adder circuit 31 via an h line delay circuit 36 that outputs a reproduction error Ei-d generated by d dot pixels earlier than the original pixel Ai, j, and A d-dot delay circuit 37 for outputting a reproduction error Ej-h generated in the past by h lines from the pixel Ai, j
It is connected to the horizontal direction addition circuit 32 through.

The operation of the circuit configured as above will be described. (1) When the correction luminance line is a straight line The light emission luminance level for the drive signal to the PDP 10 is actually measured, and the light emission luminance level is normalized by its maximum value to obtain the stepwise measurement line shown in FIG. And In this example, the video input signal is 8 bits, and the drive signal is 4 bits. A corrected luminance line represented by y = ax + b is obtained based on the measured line. Since this corrected luminance line is slightly deviated from the ideal line of y = x, it is necessary to correct it. The luminance line corrected for this is shown in FIG. 4, and the diffusion output signal level is corrected by {(corrected luminance line gradient a-1) -corrected luminance line contact b}. As shown in FIG. 4, stepwise data when the correction luminance line is corrected to be y = x is stored in the memory 38.

When the corrected luminance line is y = x, the corrected luminance level becomes the same as the emission luminance level. Therefore, if the number of drive output bits is m, 2 to the m-th power, specifically, m = 4
Then, the data of the brightness level of 2 4 = 16 words may be stored in the memory 38. In FIG. 3, when the corrected luminance line y = ax + b almost coincides with y = x, the actual measurement value data shown in FIG. 3 is stored in the memory without performing the processing shown in FIG. 38 may be stored.

In the above configuration, the diffused output signal input to the error detection circuit 35 and the memory 38 shown in FIG.
The difference between the stepwise data and the stepwise data is obtained by the subtraction circuit 39 to obtain an error output signal. This error output signal is, for example, as shown in FIG. This error output signal becomes an error weight output signal weighted by the weight circuits 40 and 41. This weighting is dispersed so that the total is 1, such as 0.5 and 0.5 and 0.4 and 0.6. The error weighted output from the weighting circuit 40 weighted in this way is input to the h-line delay circuit 36, and the reproduction error Ej generated in the past by h lines from the original pixel Ai, j.
-H is corrected and the original pixel is set to A in the vertical direction addition circuit 31.
i, j. Next, the weighted error weight output from the weighting circuit 41 is input to the d-dot delay circuit 37 to correct the reproduction error Ei-d generated by d dots in the past from the original pixel Ai, j and add in the horizontal direction. The circuit 32 incorporates it into the original pixel Ai, j.

The diffused output signal in which the error is incorporated and diffused is sent to the bit conversion circuit 33, and this bit conversion circuit 33 is transmitted.
The spread output signal quantized with n bits at m (≤n
-1) Converted to bits and output from the video output terminal 34. In this way, the original video input signal is diffused by incorporating an error, and a signal having a bit number smaller than that of the original video input signal allows a smooth response to be obtained without lowering the emission brightness.

As described above, FIG. 5 shows the error detection output = corrected luminance line-light emission luminance level. In the error detection circuit 35 shown in FIG. 1, these calculations are performed by the subtraction circuit 39. The data can also be stored in the memory 38. In this case, the memory 38 of 2 8 = 256 words is needed when 2 n, specifically, n = 8. However, the subtraction circuit 39 can be omitted. If weighted data is stored in the memory 38, the weight circuits 40 and 41 can be omitted.

(2) When the corrected luminance line is not a straight line When it is desired to correct the luminance as shown in FIG. 6 in a curved shape (gamma correction, etc.), the corrected luminance line is set to a desired curve and the emission luminance level and Error value is obtained and stored in the memory 38 in the same manner as described above. Other functions are the same as above.

When the video signal processing LSI circuit is operated near the processing speed limit, the calculation is performed while synchronizing with the system clock in order to absorb the delay time of the adder circuit and the like. The calculation in the horizontal direction is addition with the pixel one clock before in the case of d = 1 dot, which is the minimum processing unit, and all calculations must be completed in one clock. If an extra circuit is inserted in this operation loop, the increase in the delay makes the circuit construction impossible.

Therefore, in the present invention, as shown in FIG.
Since the processing in the h-line delay circuit 36 has a sufficient time margin from the input of the original pixel Ai, j, the video signal input terminal 3
Insert the vertical adder circuit 31 immediately after 0, and then d
Since the processing in the dot delay circuit 37 has no time margin from the input of the original pixel Ai, j, the horizontal direction addition circuit 32 is inserted. Specifically, the h line delay circuit 36
The h-line delay is 1 to 3 lines before, and the d-dot delay in the d-dot delay circuit 37 is 1 to 3 dots before. Preferably, h = 1 and d = 1.

[0020]

【The invention's effect】

(1) Since the error detection circuit 35 includes the memory 38 that stores the corrected brightness level data, it is possible to improve the image quality by making the shading error between the input signal and the light emission brightness substantially linear. It can be achieved with a simple circuit configuration.

(2) Since the error detection circuit 35 has the subtraction circuit 39 for obtaining an error output from the difference between the diffusion output signal input to the error detection circuit 35 and the data of the memory 38, the storage of the memory 38. The capacity can be set to the minimum.

(3) The error detection circuit 35 outputs a subtraction circuit 39 for obtaining an error output from the difference between the diffusion output signal input to the error detection circuit 35 and the data in the memory 38, and the output of the subtraction circuit 39. , H line delay data and d dot delay data are weighted by a weighting circuit 40 and a weighting circuit 41.
Since it is provided with, it is possible to change the shading error more precisely and in a natural state.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a PDP driving circuit according to the present invention.

FIG. 2 is an explanatory diagram of coordinate positions of pixels.

FIG. 3 is an actual measurement diagram of drive signal vs. emission luminance level.

FIG. 4 is a characteristic diagram of a corrected brightness level.

FIG. 5 is a characteristic diagram of error output.

FIG. 6 is a characteristic diagram when the corrected luminance line is a curve.

FIG. 7 is a perspective view of a PDP used in a 256 gradation method.

FIG. 8 is a drive sequence diagram and a drive waveform diagram in the 256 gradation method.

[Explanation of symbols]

10 ... PDP (plasma display panel), 1
1 ... Surface glass substrate, 12 ... X sustain electrode, 13 ...
Y sustain electrode, 14 ... Dielectric layer, 15 ... Protective layer, 1
6 ... Back glass substrate, 17 ... Address electrode, 18 ... Strip-shaped rib, 19 ... R (red) phosphor, 20 ... G (green)
Fluorescent material, 21 ... B (blue) fluorescent material, 22 ... Discharge space, 23
... bus electrodes, 30 ... video signal input terminal, 31 ... vertical direction addition circuit, 32 ... horizontal direction addition circuit, 33 ... bit conversion circuit, 34 ... video output terminal, 35 ... error detection circuit, 36
... h line delay circuit, 37 ... d dot delay circuit, 38 ...
Memory, 39 ... Subtraction circuit, 40 ... Weight circuit, 41 ... Weight circuit.

Claims (3)

[Claims] 1. The error output obtained by the error detection circuit 35 is
In addition to the h line delay circuit 36 and the d dot delay circuit 37,
In the PDP drive circuit configured to incorporate the reproduction error into the original pixel video signal input to the video signal input terminal 30, the error detection circuit 35 includes a memory 38 for storing the corrected brightness level data. A PDP drive circuit characterized by the following. 2. The error detection circuit 35 includes a subtraction circuit 39 for obtaining an error output from the difference between the diffused output signal input to the error detection circuit 35 and the corrected brightness level data of the memory 38. The PDP drive circuit according to claim 1. 3. The error detection circuit 35 includes a subtraction circuit 39 for obtaining an error output from the difference between the diffusion output signal input to the error detection circuit 35 and the corrected luminance level data of the memory 38, and the subtraction circuit 39. 2. The PDP drive circuit according to claim 1, wherein the output of the circuit 39 is provided with weighting circuits 40 and 41 for weighting the h line delay data and the d dot delay data.