JP2982575B2 - PDP drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PDP driving circuit provided with a circuit for performing processing for performing pseudo halftone display without deteriorating the R, G, B color balance.

[0002]

2. Description of the Related Art Recently, as a thin and lightweight display device, P
DP (plasma display panel) has attracted attention. The driving method of this PDP is completely different from the conventional CRT driving method, and is a direct driving method using digitized video input signals. Therefore, the luminance gradation emitted from the panel surface is determined by the number of bits of the signal to be handled. PDPs are divided into two types, AC type and DC type, which have different basic characteristics. For DC type PDPs, there have been reports on methods for improving luminance and lifetime, which have already been issues, and progress is being made toward practical use. is there.

[0003] In the AC type PDP, sufficient characteristics have been obtained with respect to luminance and life. However, as for gradation display, only a maximum of 64 gradation display has been reported at the prototype level. A method of 256 gradations in the future using a pattern driving method (ADS subfield method) has been proposed. The panel structure of a PDP (plasma display panel) 10 used in this method is shown in FIG.
The driving sequence and the driving waveform are shown in FIGS.

In FIG. 8, a pair of an X sustain electrode 12 and a Y sustain electrode 13 are formed on the lower surface of a front surface glass substrate 11 on the display surface side by a transparent electrode and an auxiliary electrode. In the auxiliary electrode, the bus electrode 23 is formed in a part of the transparent electrode in order to prevent a voltage drop due to the resistance of the transparent electrode. A dielectric layer 14 is provided on the X-sustain electrode 12 and the Y-sustain electrode 13, and strip-like ribs 18 are formed thereon to separate coupling between cells. Further, a protective layer 15 made of an MgO film is deposited. An address electrode 17 is formed on the opposite back glass substrate 16. A stripe-shaped rib 18 on the stripe is provided between the address electrodes 17, and the address electrodes 17 are further covered.
A (red) phosphor 19, a G (green) phosphor 20, and a B (blue) phosphor 21 are separately formed. In the discharge space 22, Ne +
Xe mixed gas is sealed.

In FIG. 9A, one frame has a relative luminance ratio of 1, 2, 4, 8, 16, 32, 64, 128.
, And 256 gradations are displayed by the combination of the luminances of the eight screens. In FIG. 9 (b), each subfield has a refreshed 1
It consists of an address period for writing data for the screen and a sustain period for determining the luminance level of the subfield. In the address period, first, wall charges are initially formed on each pixel at the same time for the entire screen, and then a sustain pulse is applied to the entire screen to perform display. The brightness of the subfield is proportional to the number of sustain pulses and is set to a predetermined brightness. In this way, 256 gradation display is realized.

[0006]

In the above-described AC drive system, as the number of gradations is increased, the number of bits in the address period as a preparation period for lighting and emitting the panel within one frame period increases. In addition, the sustain period as a light emitting period is relatively short, and the maximum luminance is reduced. Thus, the luminance gradation emitted from the panel surface is
Since it is determined by the number of bits of the signal to be handled, if the number of bits of the signal to be handled is increased, the image quality will be improved, but the emission luminance will be reduced. Conversely, if the number of bits of the signal to be handled is reduced, the emission brightness will be increased, but the gradation The display is reduced, and the image quality is reduced.
Therefore, in the field of printing, electronic copying, etc., research and development in which halftone is represented by two grayscales, white and black, as a method of continuously and naturally changing shades with a small number of grayscales-a pseudo halftone display. And many methods have been proposed, but in the field of video, there is no definitive method of this type of pseudo halftone display at present.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit which enables pseudo halftone display without deteriorating the color balance of each color of the three primary color signals.

[0008]

According to the present invention, each of the color signals input to the R, G, and B video signal input terminals 30R, 30G, and 30B is converted into an error diffusion circuit 2 for each of R, G, and B.
9R, 29G, and 29B, the R, G, and B error diffusion circuits 29R, 29G, and 29B output their respective error outputs as h.
In addition to the line delay circuit 36 and the d-dot delay circuit 37, an error detection circuit 35 for incorporating this reproduction error into the original pixel video signals of each color input to the R, G, and B video signal input terminals 30R, 30G, and 30B. The error detection circuit 35 includes a driving signal to the PDP 10.
Measured luminance line data representing the actual emission luminance level or
Correct the measured luminance line data so that it approaches the ideal line.
A memory 38 for storing the luminance line data is provided.
More natural state of the PDP using the data of the memory 38
A PDP drive circuit characterized in that the display is performed by the following.

[0009]

The memory 38 in the error detection circuit 35 stores the PDP1
Expressed the actual light emission luminance level for the drive signal to 0
Ideally measured luminance line data or this measured luminance line data
To store the luminance line data corrected so as to approach the line
Therefore, a PDP is created by using the data in the memory 38.
Display in a more natural state, pseudo-halftone display
Means that the color balance is lost for each of the R, G, and B colors.
And not. Moreover, it can be achieved with a simple circuit configuration.
Wear. Further, if a random correction value that does not degrade the original image quality is added and / or subtracted, the pseudo halftone display does not generate a regular pattern, and the pseudo pattern is eliminated. Therefore, R, G, B Is performed without losing the color balance of.

[0010]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit for performing error diffusion on each of the three primary color signals of red (R), green (G), and blue (B). 29R is an R error diffusion circuit, and 29G is a G error diffusion circuit. , 29B are B error diffusion circuits. Since the internal configuration is the same, the R error diffusion circuit 29R will be described below. This R error diffusion circuit 29
In R, an R video signal input terminal 30R is an R video signal input terminal of an n-bit original pixel _{Ai, j} , and the R video signal input terminal 30R is a vertical direction addition circuit 31, a correction addition circuit 44, a horizontal direction After passing through the addition circuit 32, the bit conversion circuit 33 further performs processing for reducing the number of bits, and is connected to the R video output terminal 34R. An error detection circuit 35 is connected to the output side of the horizontal addition circuit 32. The error detection circuit 35, a memory 38 for storing data, a subtraction circuit 39 for outputting an error signal by taking the difference between the spread output signal and the output of the memory 38, to a predetermined weighting on the error signal , And load circuits 40 and 41 for outputting the error load.

The load circuits 40, 4 of the error detection circuit 35
1 is on the output side by h lines past the original pixel A _{i, j}
A is connected to the vertical adder circuit 31 via the h line delay circuit 36 for outputting a reproduction error E _j-h generated, the original pixel A _i, raw only past d dot pixels from _j
D dot delay circuit 37 to output a reproduction error _{E i-d} Flip was
Is connected to the horizontal addition circuit 32 via the.

The G connected to the G video signal input terminal 30G
As described above, the internal circuit configurations of the error diffusion circuit 29G and the B error diffusion circuit 29B connected to the B video signal input terminal 30B are the same. R video output terminal 34R, G video output terminal 34G, B video output terminal 3
4B is connected to PDP10.

Next, the correction addition circuit 44 of each of the R, G, and B error diffusion circuits 29R, 29G, and 29B has a function of eliminating a pseudo pattern generated in an image obtained by pseudo halftone display. For the purpose, a correction amount control unit 42, a correction amount output unit 43, and a correction addition circuit 44 are added as means for adding and / or subtracting a random correction value that does not deteriorate the original image quality. That is, the correction addition circuit 44
At an appropriate position in the circuit.
Is connected to a correction amount output unit 43 that outputs a correction value equal to or less than the error load output value without deteriorating the original image quality. If the correction value output unit 43 has a constant correction value, a regular pattern is repeatedly generated again to form a pseudo pattern, so that the correction value control unit 42 determines that the correction value of the correction amount output unit 43 is large or small.
Control is performed so that random values such as small, positive, negative, and mixed positive and negative are obtained.

The insertion position of the correction addition circuit 44 is not limited to the case where the correction addition circuit 44 is inserted between the vertical direction addition circuit 31 and the horizontal direction addition circuit 32 as shown in FIG. , The horizontal addition circuit 32
, The subtraction circuit 39 and the load circuit 4
0, or may be inserted between the load circuits 41.

The operation of the circuit having the above configuration will be described for the case of the R signal, but the same applies to the case of the G signal and the B signal. (1) When the luminance line to be corrected is a straight line The emission luminance level for the drive signal to the PDP 10 is actually measured. It is assumed that the step-like characteristic line shown in FIG. 3 is an actually measured luminance line obtained by normalizing the actually measured light emission luminance level with its maximum value. In this example, an example in which the R video input signal is 8 bits and the drive signal is 4 bits is shown. Based on the actually measured luminance line, y = ax +
A luminance line to be corrected represented by b is obtained. Since the luminance line to be corrected is slightly deviated from the ideal line of y = x, it is necessary to perform correction. FIG. 4 shows a luminance line obtained by correcting the actually measured luminance line so as to be closer to an ideal line, and is obtained by correcting the diffused output signal level by the following equation. (Gradient a-1 of luminance line to be corrected) -tangent b of luminance line to be corrected FIG. 4 shows a case where the luminance line to be corrected is corrected so that ideal line y = x. The stepped data is stored in the memory 38.

When the corrected luminance line is y = x, the corrected luminance level becomes the same as the emission luminance level. Accordingly, if the number of drive output bits is m, the power of 2 m, specifically, if m = 4, the data of the luminance level of 2 4 = 16 words may be stored in the memory 38. Note that FIG.
, The luminance line y = ax + b to be corrected is the ideal line y
= X, the measured luminance line data shown in FIG. 3 may be stored in the memory 38 without performing the processing shown in FIG.

The principle of the error diffusion method in the above-described configuration is that density modulation is performed by two luminance gradations to create a visually pseudo gradation in a small area having a certain spread, and to perform multi-gradation. It is something that you get. This will be described in more detail with reference to FIG. A _{i, j} : input pixel value of the current processing target A _{i, j-1} : input pixel value of one line before A _{i-1, j} : input pixel value of one dot before δ _v : diffusion output from one line before Pixel error load value δ _h : Assuming that the error output value of the diffusion output pixel from one dot before is the difference between the diffusion output signal input to the error detection circuit 35 and the data from the memory 38, An operation is performed to obtain an error output signal. The error output signals are weighted error load output signals δ _v , δ _{h of} K _v , K _{h by} the load circuits 40 and 41, respectively, and are input to the h line delay circuit 36 and the d dot delay circuit 37, The original pixel A is calculated by the adder 31 and the horizontal adder 32.
_{i, j} , C _{i, j} = A _{i, j} + δ _v + δ
_h . C _{i, j} : the diffusion output pixel value of the current processing target δ _v = K _v × ｛f (C _{i, j−1} ) −B _r δδ _h = K _h × ｛f (C _{i−1, j} ) −B _r ｆ f (C _{i, j} ): Corrected luminance for C _{i, j} B _r : Emission luminance level. In this way, an error is incorporated into the original video input signal and diffused, and a signal having a smaller number of bits than the original video input signal can obtain a smooth response without lowering the light emission luminance.

In the pseudo halftone display as described above, the pseudo halftone display can be performed by adding and / or subtracting a random correction value that does not degrade the original image quality to the R video signal input or the reproduction error value. No regular pattern is generated, and the pseudo pattern is eliminated. The load, that is, the weighting is, for example, 0.5 and 0.5,
Disperse so that the total is 1, such as 0.4 and 0.6.

The spread output signal obtained by incorporating the error and the correction value and spreading is sent to a bit conversion circuit 33, and the spread output signal quantized by the n-bit by the bit conversion circuit 33 is
It is converted into m (≦ n−1) bits and output from the R video output terminal R video output terminal 34R. Similarly, the outputs of the G video output terminal 34G and the B video output terminal 34B are G, B
The error and the correction value are incorporated into each of the original video input signals to be diffused, and are converted to a smaller number of bits than the original video input signal and sent to the PDP 10, and the light emission luminance is not reduced by the PDP 10; It is displayed without any.

FIG. 5 shows increase (+) and decrease (-) of the error detection output with respect to the drive signal to the PDP 10. Here, the error detection output is expressed by the following equation as described above. Error detection output = luminance level to be corrected-luminance luminance level In the error detection circuit 35 shown in FIG. 1, these calculations are performed by the subtraction circuit 39.
8 can also be stored. In this case, n of 2
In the case of the power, specifically, n = 8, the memory 38 of 2 8 = 256 words is required. However, the subtraction circuit 39 can be omitted. If the data in the memory 38 is stored in the memory 38 with weighted data in advance, the load circuits 40 and 41 can be omitted.

(2) When the luminance line to be corrected is not a straight line When it is desired to correct the luminance as a curve as shown in FIG. 6 (such as gamma correction), the luminance line to be corrected is set to a desired curve . The luminance level to be corrected and the actual measurement in (1) above
An error value between the luminance line data and the corrected luminance line data in (2) is obtained and stored in the memory 38 in the same manner as described above. Other operations are the same as described above.

As described above, the data to be stored in the memory 38 is
Stopping is as follows. (1) Actual light emission luminance for drive signal to PDP 10
Measured luminance line data representing the level (2) Corrected the measured luminance line data so that it approaches the ideal line
A brightness level to be the luminance-ray data (3) correction, and bright actually measured in the above (1)
The difference between the line data or the luminance line data corrected in (2)
And error detection output data (4) obtained by the weighted error detection output data of the (3)
Data (5) If you want to correct the brightness in a curved line (such as gamma correction)
Correction) with the luminance curve to be corrected set to the desired curve
Luminance level to be measured and measured luminance line data in (1) above
Or, an error value with the corrected luminance line data of (2) was obtained.
data

[0023]

(1) In the present invention, the error detection circuit 35
Next, the actual light emission luminance level with respect to the drive signal to the PDP 10 will be described.
Measured luminance line data representing the bell or this measured luminance line
Luminance line data corrected so that the data approaches the ideal line
Is provided, the memory 38 for storing
Displaying PDP in a more natural state using data
And pseudo-halftone display is performed for each of R, G, and B colors.
It does not break the color balance. And simple circuit
This can be achieved with a configuration.

(2) In the error detection circuit 35, all corrections should be made.
Brightness level and the actual driving signal to the PDP 10
Measured luminance line data representing the emission luminance level of
Brightness corrected from the measured luminance line data so that it approaches the ideal line
Error detection output data calculated as the difference from the stitch line data
Is calculated by the subtraction circuit 39 or stored in the memory 38.
I used this error detection output data
R, G, B video input signals and luminescence in PDP
The change of the target characteristic line such as linear or curved
And image quality can be improved. Also,
The subtraction circuit 39 calculates the error detection output data.
Then, the storage capacity of the memory 38 can be set to a minimum.

(3) In the error detection circuit 35,
The brightness level to be corrected and the drive signal to PDP 10 are
Measured luminance line data representing the actual light emission luminance level
Alternatively, supplement the measured luminance line data so that it approaches the ideal line.
Error detection output data is calculated from the difference from the corrected luminance line data.
Therefore, the data obtained by weighting the error detection output data is
Determined by the load circuits 40 and 41 or stored in the memory 38
So, using this weighted data,
PDP can be displayed in a more natural state.
The density error more precisely and naturally
be able to.

(4) R, G, B video signal input or
The reproduction error value is random enough not to degrade the original image quality.
As means for adding and / or subtracting a correction value,
Amount output unit 43, correction amount control unit 42, and correction addition circuit 4
Since 4 was added, a regular pattern was not generated.
Thus, a pseudo pattern can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a PDP drive circuit according to the present invention.

FIG. 2 is an explanatory diagram of a coordinate position of a pixel.

FIG. 3 is an actual measurement diagram of a driving signal versus a light emission luminance level.

FIG. 4 is a characteristic diagram of a corrected luminance level.

FIG. 5 is a characteristic diagram of an error output.

FIG. 6 is a characteristic diagram when the correction luminance line is a curve.

FIG. 7 is an enlarged view in which an actual measurement line of the drive signal versus the light emission luminance level shown in FIG. 3 is partially extracted.

FIG. 8 is a perspective view of a PDP used in a 256 gradation method.

FIG. 9 is a diagram showing a driving sequence and driving waveforms in a 256-gradation method.

[Explanation of symbols]

10 PDP (plasma display panel), 1
DESCRIPTION OF SYMBOLS 1 ... Surface glass substrate, 12 ... X sustain electrode, 13 ...
Y sustain electrode, 14: dielectric layer, 15: protective layer, 1
6 ... back glass substrate, 17 ... address electrode, 18 ... stripe-shaped rib, 19 ... R (red) phosphor, 20 ... G (green)
Phosphor, 21 ... B (blue) phosphor, 22 ... discharge space, 23
... bus electrode, 29R ... R error diffusion circuit, 29G ... G error diffusion circuit, 29B ... B error diffusion circuit, 30R ... R video signal input terminal, 30G ... G video signal input terminal, 30B ... B
Video signal input terminal, 31 vertical addition circuit, 32 horizontal addition circuit, 33 bit conversion circuit, 34R R video output terminal, 34G G video output terminal, 34B B video output terminal, 35 error detection Circuit, 36 h line delay circuit, 37 d dot delay circuit, 38 memory, 39 subtraction circuit, 40 load circuit, 41 load circuit, 42 correction amount control unit, 43 correction amount output unit, 44 ... Correction addition circuit.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FIG06F 15/68 320A

Claims (6)

(57) [Claims] 1. R, G, B video signal input terminals 30
Each of the color signals input to R, 30G and 30B is converted to R,
G, B error diffusion circuits 29R, 29G, 29B
Error diffusion and display on PDP10,
Each of the R, G, and B error diffusion circuits 29R, 29G, 29
B applies the respective error outputs to the h-line delay circuit 36 and the d-dot delay circuit 37, and outputs the reproduction error to R,
G and B video signal input terminals 30R, 30G, 3
Comprising an error detection circuit 35 incorporated in the color original pixel image signal inputted to 0B, this error detection circuit 35, before
The actual light emission luminance level for the drive signal to the PDP 10
Measured luminance line data or the measured luminance line data
The provided memory 38 for storing the luminance line data corrected over data so as to approach the ideal line, the data of the memory 38
To display the PDP in a more natural state
A PDP drive circuit, characterized in that: 2. R, G, B video signal input terminals 30
Each of the color signals input to R, 30G and 30B is converted to R,
G, B error diffusion circuits 29R, 29G, 29B
Error diffusion and display on PDP10,
Each of the R, G, and B error diffusion circuits 29R, 29G, 29
B applies the respective error outputs to the h-line delay circuit 36 and the d-dot delay circuit 37, and outputs the reproduction error to R,
G and B video signal input terminals 30R, 30G, 3
Comprising an error detection circuit 35 incorporated in the color original pixel image signal inputted to 0B, this error detection circuit 35, the auxiliary
The luminance level to be corrected and the drive signal to the PDP 10
Measured luminance line data representing the actual light emission luminance level
Or the measured luminance line data so that it approaches the ideal line.
Error detection calculated as difference from corrected luminance line data
A memory 38 for storing output data is provided.
The PDP is displayed in a more natural state using the data of FIG.
A PDP drive circuit characterized in that: 3. Each of R, G, and B video signal input terminals 30.
Each of the color signals input to R, 30G and 30B is converted to R,
G, B error diffusion circuits 29R, 29G, 29B
Error diffusion and display on PDP10,
Each of the R, G, and B error diffusion circuits 29R, 29G, 29
B applies the respective error outputs to the h-line delay circuit 36 and the d-dot delay circuit 37, and outputs the reproduction error to R,
G and B video signal input terminals 30R, 30G, 3
Comprising an error detection circuit 35 incorporated in the color original pixel image signal inputted to 0B, this error detection circuit 35, before
The actual light emission luminance level for the drive signal to the PDP 10
Measured luminance line data or the measured luminance line data
A memory 38 for storing luminance line data corrected so that the data approaches an ideal line; a luminance level to be corrected;
Measured luminance line data or corrected luminance line data in the memory 38
And a subtraction circuit 39 for calculating error detection output data from the difference between the data and the data in the memory 38.
The PDP is calculated in a more natural state using the calculation result of the path 39.
A PDP drive circuit characterized in that the display is performed in a state of being displayed . 4. A weighting circuit 4 for weighting h-line delay data and d-dot delay data in an error detection circuit 35.
0 and 41 are provided to display PDP in a more natural state
PDP of claim 2 or 3, wherein the was Unishi
Drive circuit. 5. R, G and B video signal input terminals 30
Each of the color signals input to R, 30G and 30B is converted to R,
G, B error diffusion circuits 29R, 29G, 29B
Error diffusion and display on PDP10,
Each of the R, G, and B error diffusion circuits 29R, 29G, 29
B applies the respective error outputs to the h-line delay circuit 36 and the d-dot delay circuit 37, and outputs the reproduction error to R,
G and B video signal input terminals 30R, 30G, 3
Comprising an error detection circuit 35 incorporated in the color original pixel image signal inputted to 0B, this error detection circuit 35, the auxiliary
The luminance level to be corrected and the drive signal to the PDP 10
Measured luminance line data representing the actual light emission luminance level
Or the measured luminance line data so that it approaches the ideal line.
Error detection output data is calculated from the difference with the corrected luminance line data.
Determined, a memory 38 for storing data weighted respectively and h line delay data and d-dot delay data in the error detection output data provided, data of the memory 38
Display the PDP in a more natural state using data
PDP drive circuit, characterized in that had Unishi. 6. In addition to the error detection circuit 35, R, G, B
Each video signal input or reproduction error value may degrade the original image quality.
Adds and / or subtracts random correction values to a lesser extent
Means for adding the random correction value and
And / or means for subtracting the correction value from the correction amount output unit 43.
Correction amount control unit 42 for controlling the correction value of positive amount output unit 43
And the correction value of the correction amount output unit 43 for each of R, G, and B.
From the correction adding circuit 44 which adds the error to the error detecting circuit 35,
In the pseudo halftone display using a random correction value.
To prevent the occurrence of regular patterns
The PDP drive circuit according to claim 4 or 5, wherein