JPH0764108A - Semiconductor device and its production - Google Patents

Semiconductor device and its production

Info

Publication number
JPH0764108A
JPH0764108A JP20971193A JP20971193A JPH0764108A JP H0764108 A JPH0764108 A JP H0764108A JP 20971193 A JP20971193 A JP 20971193A JP 20971193 A JP20971193 A JP 20971193A JP H0764108 A JPH0764108 A JP H0764108A
Authority
JP
Japan
Prior art keywords
film
source
insulating
layer
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20971193A
Other languages
Japanese (ja)
Inventor
Yoshiko Mino
美子 美濃
Ikunori Kobayashi
郁典 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP20971193A priority Critical patent/JPH0764108A/en
Publication of JPH0764108A publication Critical patent/JPH0764108A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the exposure of an Al film to a resist developer by an insulating protective film serving as protection at the time of working a source- drain film by forming source-drain electrodes into a laminated structure of a metallic layer and insulating layer. CONSTITUTION:The Al film is patterned and formed as gate electrodes 2 on one main plane of a transparent substrate 1 and a semiconductor layer is so formed as to overlap on a part of the gate electrodes via an insulating thin-film layer 3. An ITO film is then patterned and formed as pixel electrodes 4. A laminated layer 5a of Ti and Al as a metallic film and an SiNx film as an insulating film 6 are thereafter laminated and formed and are patterned and formed to obtain the source-drain electrodes 5. A TFT array substrate 7 is completed in such a manner. The gate insulating thin film 3 is preferably made to remain on the gate drawing out electrodes at this time. The metallic film 5a and the insulating film 6 are formed as the source-drain electrodes in such a manner, by which the insulating film 6 is acted as the protective film at the time of processing the source-drain film and the exposure of the Al to the resist developer is prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、液晶表示装置を駆動す
る薄膜トランジスタ(以下TFT略す)等の半導体装置
及びその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a thin film transistor (hereinafter abbreviated as TFT) for driving a liquid crystal display device and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来法について図3のTFTアレイ形成
工程図及び図4、図5のTFTアレイと液晶表示装置の
概略構成図を用い以下に説明する。
2. Description of the Related Art A conventional method will be described below with reference to the TFT array forming process diagram of FIG. 3 and the schematic configuration diagrams of the TFT array and liquid crystal display device of FIGS.

【0003】TFTアレイは、透明基板1の一主面上に
ゲート電極2としてAl膜がパターン形成され(図3
工程1、2)、絶縁薄膜層3を介して半導体層が前記ゲー
ト電極の一部と重なるように形成されている(図3 工
程3〜8)。そして、画素電極4としてITO膜がパター
ン形成され(図3 工程9、10)、ソース・ドレイン電
極5となるTiとAlの金属積層膜5aをパターン形成
する(図3 工程11、12)。最後に絶縁保護膜6をパタ
ーン形成し(図3 工程13、14)、TFTアレイ7が完
成する(図4参照)。
In the TFT array, an Al film is patterned as a gate electrode 2 on one main surface of the transparent substrate 1 (see FIG. 3).
In steps 1 and 2), the semiconductor layer is formed so as to overlap a part of the gate electrode with the insulating thin film layer 3 interposed therebetween (steps 3 to 8 in FIG. 3). Then, an ITO film is patterned as the pixel electrode 4 (steps 9 and 10 in FIG. 3), and a metal laminated film 5a of Ti and Al to be the source / drain electrodes 5 is patterned (steps 11 and 12 in FIG. 3). Finally, the insulating protection film 6 is patterned (steps 13 and 14 in FIG. 3) to complete the TFT array 7 (see FIG. 4).

【0004】このようにして得られたTFTアレイ基板
7はその性能を検査の後、図5に示すように、前記TF
Tアレイ基板と透明電極を配置した対向基板8の間に液
晶9を狭じて貼合わせ、その後のTFT性能を検査して
液晶表示装置10を得る。
After the performance of the TFT array substrate 7 thus obtained is inspected, as shown in FIG.
The liquid crystal 9 is sandwiched and stuck between the T array substrate and the counter substrate 8 on which the transparent electrodes are arranged, and the subsequent TFT performance is inspected to obtain the liquid crystal display device 10.

【0005】液晶表示装置の組立工程として基板の分
割、面取り、TFTアレイ基板および対向基板への配向
膜形成、液晶配向制御処理、前記両基板の貼合わせ用シ
ール材印刷、基板間ギャップ制御のためのスペーサ材配
置、前記両基板のアライメント貼合わせ、液晶注入およ
び注入口封止、静電気によるTFT破壊防止用のショー
トリング除去などがある。その後TAB実装が施される
(図6参照)。
As a process of assembling the liquid crystal display device, for dividing the substrate, chamfering, forming an alignment film on the TFT array substrate and the counter substrate, liquid crystal alignment control processing, printing a sealing material for bonding the both substrates, and controlling a gap between the substrates. The spacer material arrangement, the alignment and bonding of the both substrates, the liquid crystal injection and the injection port sealing, and the removal of the short ring for preventing the destruction of the TFT due to static electricity. Thereafter, TAB mounting is performed (see FIG. 6).

【0006】これら工程に於て、図中破線で囲む4つの
工程は基板汚染が懸念されるところである。
In these steps, the four steps surrounded by broken lines in the figure are concerned about substrate contamination.

【0007】最後に、TFTを構成する導電体層に接続
された電極と、対向電極(図示せず)との間に電圧を印
加することにで液晶を駆動させ画像を表示する。
Finally, by applying a voltage between the electrode connected to the conductor layer forming the TFT and the counter electrode (not shown), the liquid crystal is driven to display an image.

【0008】[0008]

【発明が解決しようとする課題】TFTアレイは工程数
を削減し、歩留まり向上を図り、コストダウンを進めて
いかなくてはならない。ところで、コストダウンを制約
するものの1つにフォト工程がある。上述のTFT構成
では最終工程である絶縁保護膜は、液晶画像表示装置の
組立工程において、導電物質からなる異物の混入よる、
ソース電極と対向電極との短絡防止を目的としている重
要な工程であるが、工程数の増加の一因となっている。
さらには液晶表示装置の組立において、ゲート・ソース
電極の引出し部がTFTアレイ工程ですでに露出してい
るため、組立工程中に汚れるなどの問題があった。
In the TFT array, it is necessary to reduce the number of steps, improve the yield, and promote the cost reduction. By the way, one of the things that restrict the cost reduction is the photo process. In the above-mentioned TFT configuration, the insulating protection film, which is the final step, is caused by the inclusion of foreign substances made of a conductive material in the assembly process of the liquid crystal image display device.
This is an important step aimed at preventing a short circuit between the source electrode and the counter electrode, but this is one of the causes of the increase in the number of steps.
Further, in assembling the liquid crystal display device, the gate / source electrode lead-out portions have already been exposed in the TFT array process, so that there is a problem such as contamination during the assembling process.

【0009】本発明は、このような従来のTFT製造方
法の課題を考慮し、工程数を少なくでき、また、ゲート
・ソース電極の引出し部が組立工程中に汚れることのな
い半導体装置及びその製造方法を提供することを目的と
するものである。
In consideration of the above problems of the conventional TFT manufacturing method, the present invention can reduce the number of steps, and the semiconductor device and its manufacturing in which the lead-out portion of the gate / source electrode is not contaminated during the assembly process. It is intended to provide a method.

【0010】[0010]

【課題を解決するための手段】本発明は、ソース・ドレ
イン電極として金属膜と絶縁膜を製膜後、ソース・ドレ
イン電極パターンのレジストマスクを形成し、ソース・
ドレイン電極の絶縁膜と金属膜を順次エッチングするも
のである。
According to the present invention, after a metal film and an insulating film are formed as source / drain electrodes, a resist mask having a source / drain electrode pattern is formed to form a source / drain electrode.
The insulating film of the drain electrode and the metal film are sequentially etched.

【0011】[0011]

【作用】ソース・ドレイン電極として金属膜と絶縁膜を
製膜することで、絶縁膜がソース・ドレイン膜の加工時
に保護膜となって、Al膜がレジスト現像液に曝される
ことを防止できる。
By forming a metal film and an insulating film as the source / drain electrodes, the insulating film serves as a protective film when processing the source / drain film, and the Al film can be prevented from being exposed to the resist developing solution. .

【0012】また、金属膜と絶縁膜を一括加工すること
でフォト工程およびエッチング工程を削減できる。そし
て、絶縁膜はソース・ドレイン電極上に保護膜として同
パターンで存在することから、液晶表示装置として組立
た際にソース電極と対向電極との短絡を防止でき、輝度
むらのない液晶画像表示装置を確保できる。
Further, the photo process and the etching process can be reduced by collectively processing the metal film and the insulating film. Further, since the insulating film exists as a protective film on the source / drain electrodes in the same pattern, it is possible to prevent a short circuit between the source electrode and the counter electrode when the liquid crystal display device is assembled, and a liquid crystal image display device without uneven brightness. Can be secured.

【0013】さらには、外部引出し電極上に絶縁薄膜を
残した状態でアレイプロセスを終了し、液晶表示装置と
しての組立工程で前記残存絶縁薄膜を除去することによ
って、前記外部引出し電極をTAB実装直前まで清浄な
状態に保つことができる。
Furthermore, the array process is terminated with the insulating thin film left on the external extraction electrode, and the residual insulating thin film is removed in the assembly process as a liquid crystal display device, so that the external extraction electrode is immediately before TAB mounting. Can be kept up to clean.

【0014】[0014]

【実施例】以下、本発明の実施例について図面を参照し
て説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0015】図1は、本発明の一実施例であるTFTア
レイの形成工程図、図2は、本発明の一実施例であるT
FTの断面図である。
FIG. 1 is a process chart of forming a TFT array which is an embodiment of the present invention, and FIG. 2 is a T which is an embodiment of the present invention.
It is sectional drawing of FT.

【0016】本発明のTFTアレイは、前記従来例と同
様に透明基板1の一主面上にゲート電極2としてAl膜
がパターン形成され、絶縁薄膜層3を介して半導体層が
前記ゲート電極の一部と重なるように形成され、そし
て、画素電極4としてITO膜がパターン形成される。
その後、金属膜としてTiとAlの積層膜5a、絶縁膜
6としてSiNx膜を積層製膜し(図1 工程11、1
2)、パターン形成してソース・ドレイン電極5を得る
(図1 工程13)。このようにしてTFTアレイ基板7
が完成する(図2参照)。
In the TFT array of the present invention, an Al film is patterned as the gate electrode 2 on one main surface of the transparent substrate 1 as in the conventional example, and the semiconductor layer is the gate electrode via the insulating thin film layer 3. An ITO film is formed as a pixel electrode 4 so as to overlap with a part thereof.
After that, a laminated film 5a of Ti and Al is formed as a metal film, and a SiNx film is formed as an insulating film 6 (see steps 11 and 1 in FIG. 1).
2), pattern formation is performed to obtain the source / drain electrodes 5 (step 13 in FIG. 1). In this way, the TFT array substrate 7
Is completed (see FIG. 2).

【0017】この時ゲート引出し電極上にはゲート絶縁
薄膜3を残存させておくことが望ましい。そして、前記
ゲート電極2上及び前記ソース・ドレイン電極5の最上
層には絶縁体層が存在する。そこで、前記液晶表示装置
の組立工程前後の検査には、前記絶縁体層を貫通させて
プローブ針をゲート電極及びソース・ドレイン電極5の
金属膜5aに接触させる。このようにしてTFTアレイ
の性能検査を行なう。そして、TAB実装の際に前記保
護膜をエッチング除去するものである。
At this time, it is desirable to leave the gate insulating thin film 3 on the gate extraction electrode. An insulator layer exists on the gate electrode 2 and the uppermost layer of the source / drain electrodes 5. Therefore, in the inspection before and after the assembly process of the liquid crystal display device, the probe needle is brought into contact with the metal film 5a of the gate electrode and the source / drain electrode 5 by penetrating the insulating layer. In this way, the performance of the TFT array is inspected. Then, the protective film is removed by etching when the TAB is mounted.

【0018】なお、前記ソース・ドレイン電極膜および
絶縁保護膜の成膜は、連続でもまた個々に行なってもよ
い。そして、フォトレジストはアレイ構成や作業環境に
よりネガでもポジでもよい。さらに、ソース・ドレイン
電極膜および絶縁保護膜の加工においては、アレイ構成
や作業環境によりウェットエッチでもドライエッツでも
よい。
The source / drain electrode film and the insulating protective film may be formed continuously or individually. The photoresist may be negative or positive depending on the array structure and work environment. Further, in processing the source / drain electrode film and the insulating protective film, either wet etching or dry etching may be performed depending on the array configuration and the working environment.

【0019】また、SiNxとTiとAlの一括ドライ
エッチングであれば、エッチング工程も簡略できる。
Further, if the dry etching of SiNx, Ti and Al is carried out at the same time, the etching process can be simplified.

【0020】また、本実施例では画素電極をソース・ド
レイン電極の前工程に設けた構成となっているが、本発
明は、そのような構成に限定されるものではない。
Further, in the present embodiment, the pixel electrode is provided in the pre-process of the source / drain electrodes, but the present invention is not limited to such a configuration.

【0021】[0021]

【発明の効果】以上述べたところから明らかなように、
本発明によれば、ソース・ドレイン電極を金属膜と絶縁
膜の積層膜で構成することで、絶縁保護膜がソース・ド
レイン膜加工時の保護膜となって、Al膜がレジスト現
像液に曝されることを防止する。これによって、ポジレ
ジストを用いたフォトプロセスで、レジスト現像液が電
解液となって生じるITOとAl間の酸化還元反応によ
るAl溶出を回避できる。
As is apparent from the above description,
According to the present invention, by forming the source / drain electrode with a laminated film of a metal film and an insulating film, the insulating protective film serves as a protective film during processing of the source / drain film, and the Al film is exposed to the resist developing solution. To be prevented. As a result, in a photoprocess using a positive resist, it is possible to avoid elution of Al due to a redox reaction between ITO and Al that occurs when the resist developing solution serves as an electrolytic solution.

【0022】また、ソース・ドレイン電極膜として金属
膜と絶縁膜を一括加工することでフォトおよびエッチン
グ工程を削減できる。それに伴って、レジスト除去や基
板清浄工程も削減できる。
Further, by collectively processing the metal film and the insulating film as the source / drain electrode film, the photo and etching steps can be reduced. Along with this, the steps of resist removal and substrate cleaning can be reduced.

【0023】また、絶縁膜はソース・ドレイン電極上に
同パターンで存在することから、液晶表示装置として組
立た場合にソース電極と対向電極との短絡を防止でき、
輝度むらのない液晶画像表示装置を確保できる。
Further, since the insulating film exists on the source / drain electrodes in the same pattern, it is possible to prevent a short circuit between the source electrode and the counter electrode when assembled as a liquid crystal display device,
It is possible to secure a liquid crystal image display device without uneven brightness.

【0024】また、前記TFTアレイにおいて、ゲート
・ソース電極上の絶縁体層を貫通触針させてトランジス
タ機能を検査した後、液晶表示装置として組立時に前記
ゲート・ソース電極上の絶縁体層を除去できることか
ら、前記組立工程での電極汚染を防止できる。その結
果、実装引出し電極はTAB実装直前まで清浄な状態に
保つことができる。従って、TAB実装後の信頼性向上
を図ることができる。
In the TFT array, after the insulator layer on the gate / source electrodes is pierced by stylus to inspect the transistor function, the insulator layer on the gate / source electrode is removed at the time of assembly as a liquid crystal display device. Therefore, the electrode contamination in the assembling process can be prevented. As a result, the mounting lead-out electrode can be kept in a clean state until just before TAB mounting. Therefore, reliability after TAB mounting can be improved.

【0025】また、本実施例ではITO膜とソース・ド
レイン電極にAlとTiの積層膜とポジレジスト現像液
との相関に於て述べているが、電極電位の相関で電食が
生じる危険性のある金属膜に対しては特に有効であり、
いかなる金属膜でもフォト工程簡略効果のあることは言
うまでもない。
Further, in the present embodiment, the correlation between the laminated film of Al and Ti on the ITO film and the source / drain electrodes and the positive resist developing solution is described. Especially effective for metallic films with
It goes without saying that any metal film has the effect of simplifying the photo process.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のTFTアレイ形成工程図で
ある。
FIG. 1 is a process diagram of forming a TFT array according to an embodiment of the present invention.

【図2】本発明の一実施例のTFT構成断面図である。FIG. 2 is a cross-sectional view of a TFT configuration according to an embodiment of the present invention.

【図3】従来のTFTアレイ形成工程図である。FIG. 3 is a process diagram of a conventional TFT array formation process.

【図4】従来のTFT構成断面図である。FIG. 4 is a sectional view of a conventional TFT configuration.

【図5】従来の液晶表示装置構成断面図である。FIG. 5 is a cross-sectional view of a configuration of a conventional liquid crystal display device.

【図6】液晶表示装置組立・実装工程図である。FIG. 6 is an assembly / mounting process diagram of a liquid crystal display device.

【符号の説明】[Explanation of symbols]

1 透明基板 2 ゲート電極 3 絶縁薄膜層 4 画素電極 5 ソース・ドレイン電極 5a 金属積層膜 6 絶縁保護膜 7 TFTアレイ基板 8 対向基板 9 液晶 10 液晶表示装置 1 Transparent Substrate 2 Gate Electrode 3 Insulating Thin Film Layer 4 Pixel Electrode 5 Source / Drain Electrode 5a Metal Laminated Film 6 Insulation Protective Film 7 TFT Array Substrate 8 Counter Substrate 9 Liquid Crystal 10 Liquid Crystal Display Device

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】基板の一主面上に形成されたゲート電極
と、絶縁薄膜層を介して前記ゲート電極の一部と重なる
ように形成された半導体層と、ソース・ドレイン電極を
少なくとも含み、前記ソース・ドレイン電極が金属層お
よび絶縁体層の積層構造であることを特徴とする半導体
装置。
1. A gate electrode formed on one main surface of a substrate, a semiconductor layer formed so as to overlap a part of the gate electrode with an insulating thin film layer interposed therebetween, and a source / drain electrode. A semiconductor device, wherein the source / drain electrodes have a laminated structure of a metal layer and an insulator layer.
【請求項2】絶縁性基板上にゲート電極となる第1の金
属膜を被着パターン形成する工程と、ゲート絶縁膜、シ
リコン半導体層を被着する工程と、前記シリコン半導体
層を島状にパターニングする工程と、透明電極膜を被着
パターン形成する工程と、ソース・ドレイン電極となる
第2の金属膜と絶縁膜を積層構造で被着した後、そのソ
ース・ドレイン電極のエッチングマスクを用いて前記絶
縁膜をエッチング後、続いて第2の金属膜をエッチング
する工程とを備えたことを特徴とする半導体装置の製造
方法。
2. A step of forming a deposition pattern of a first metal film to be a gate electrode on an insulating substrate, a step of depositing a gate insulating film and a silicon semiconductor layer, and forming the silicon semiconductor layer in an island shape. A step of patterning, a step of forming a deposition pattern of a transparent electrode film, a step of depositing a second metal film to be a source / drain electrode and an insulating film in a laminated structure, and then using an etching mask of the source / drain electrode. And a step of subsequently etching the second metal film after etching the insulating film.
JP20971193A 1993-08-24 1993-08-24 Semiconductor device and its production Pending JPH0764108A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20971193A JPH0764108A (en) 1993-08-24 1993-08-24 Semiconductor device and its production

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20971193A JPH0764108A (en) 1993-08-24 1993-08-24 Semiconductor device and its production

Publications (1)

Publication Number Publication Date
JPH0764108A true JPH0764108A (en) 1995-03-10

Family

ID=16577385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20971193A Pending JPH0764108A (en) 1993-08-24 1993-08-24 Semiconductor device and its production

Country Status (1)

Country Link
JP (1) JPH0764108A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8735231B2 (en) 2010-08-26 2014-05-27 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of dual-gate thin film transistor
US9257561B2 (en) 2010-08-26 2016-02-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8735231B2 (en) 2010-08-26 2014-05-27 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of dual-gate thin film transistor
US9257561B2 (en) 2010-08-26 2016-02-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof

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