JPH0758920B2 - Decoder circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital signal processing circuit for processing a digital signal such as a PCM (Pulse Code Modulation) signal, and particularly to a data signal compressed by using a prediction filter or the like. The present invention relates to a decoder circuit that can reduce the influence of a code error when it occurs during decoding.

[Outline of Invention]

According to the present invention, in a decoder circuit to which mode information data including at least a straight PCM mode and information data compressed using a plurality of prediction filters including at least a straight PCM are supplied, a code error occurs in the straight PCM mode. In this case, by correcting the sample value of the word in which the code error has occurred to 0, the deterioration of the SN ratio of the reproduced signal of the high frequency is reduced.

[Conventional technology]

In recent years, along with the progress of digital technology, analog signals such as audio signals and video signals have been digitized,
It is often used as a PCM signal.

Generally, in order to digitize and process an analog signal with a wide band and a wide dynamic range, it is necessary to increase the sampling frequency and increase the number of quantizations. As a result, when a wideband analog signal such as an image signal is digitized, the bit rate of the obtained digital signal becomes extremely high, and a wideband transmission line for transmitting this is required. Further, if the digital signal is to be recorded on a recording medium, the capacity of the recording medium becomes enormous, which is not practical.

Therefore, various information compression methods for reducing the bit rate have been proposed.

The information-compressed data transmitted or recorded is expanded and decoded at the time of reproduction.

The applicant of the present invention has previously proposed a digital signal transmission method for transmitting data in block units using a plurality of predictive films to perform such information compression (Japanese Patent Application No. 58-97687 and Japanese Patent Application No. 58-97688, Japanese Patent Application No. 58-
No. 97689).

Next, FIG. 3 shows an example of an encoder circuit that performs information compression on an audio signal using a predictive filter.
In this example, two types of prediction filters are used: a temporary high-pass filter (prediction value = prefix) and an all-pass filter (prediction value = 0). Where the first-order high-pass filter is DP
It corresponds to CM (Differen-tial Pulse Code Modulation), and the all-pass filter corresponds to straight PCM.

In the figure, the data of the digitized audio signal is supplied to the DPCM unit 31 and the PCM memory 33 via the pre-emphasis circuit 30. The DPCM unit 31 performs difference processing on the input data with the first word of each block as a reference, and the resulting data is stored in the DPCM memory 32. The output of the DPCM memory 32 becomes the output of the above-mentioned primary high-pass filter, and the output of the PCM memory 33 becomes the output of the above-mentioned all-pass filter.

The outputs of these two types of filters are supplied to the absolute value detection circuit 34 and the mode selection circuit 36. The output of the absolute value detection circuit 34 is supplied to the mode / range processing circuit 35, which controls the mode / selection circuit 36 so that one of the two types of prediction filters described above can be used. The predictive filter output is selected. The prediction filter output selected here is the mode range processing circuit described above.
The shift circuit 37 controlled by 35, the quantization circuit 38, the error feedback circuit 39, etc., perform requantization and noise shaping processing, and simultaneously perform block floating processing.

The output of the encoder circuit is the 7-bit compressed data output from the quantizing circuit 38 and the 1-bit mode data and 3-bit range data output from the mode / range processing circuit 35.

With the above configuration, the encoder circuit obtains highly efficient compression characteristics.

A decoder circuit that decodes the data compressed by the encoder circuit is configured as shown in FIG. 4, for example. In the figure, the block expansion circuit 40 is supplied with the above-mentioned 7-bit compressed data and 3-bit range data. The block expansion circuit 40 performs block expansion using the range data, and the output data is supplied to the inverse prediction filter 41.

The inverse prediction filter circuit 41 includes two kinds of inverse prediction filters corresponding to the two kinds of prediction filters in the encoder circuit, and selects these two kinds of inverse prediction filters by using the above mode data. To decrypt. The decoded data is output via the de-emphasis circuit 42.

By the way, when a transmission line or a recording medium is interposed between the encoder circuit and the decoder circuit, a code error may occur due to the characteristics of the transmission line or the recording medium. When a code error occurs, the reproduced signal output from the decoder circuit has a poor SN ratio. In order to avoid this, processing such as code error detection and code error correction is generally performed in a decoder circuit.

Usually, in the decoder circuit as described above, the average value interpolation method in which the arithmetic mean value of the sample values of the words before and after the word in which the code error occurs is used as the sample value of the word in which the code error occurs is irrelevant to the inverse prediction filter. It is used without.

[Problems to be solved by the invention]

The average value interpolation method described above can effectively correct in a frequency region that is considerably lower than the sampling frequency. However, noise becomes large in a high frequency region.
The reason for this is considered as follows. That is, as shown in FIG. 5, the sample value of the signal f (t) at time t ₀ is f (t ₀ ),
The sample value at time t ₁ is f (t ₁ ) and the sample value at time t ₂ is f
(T ₂ ).

Here, the average value interpolation method with a code error has occurred at time t ₁ the sample value at _{(f (t 0) + f} (t 2)) / 2 becomes the time t ₁ to f '. Therefore, the reproduced signal has a waveform indicated by a broken line, which causes a problem that distortion occurs and the SN ratio deteriorates.

The present invention has been made to solve such a problem, and an object thereof is to provide a decoder circuit that can effectively reduce the degradation of the SN ratio due to the influence of a code error even in a high frequency region.

[Means for solving problems]

In order to solve the above problems, the present invention provides a decoder circuit to which mode information data including at least a straight PCM mode and information data compressed using a plurality of prediction filters including at least straight PCM are supplied. A code error detection circuit for input data, a mode determination circuit for input data, an interpolation circuit for interpolating a sample value of a word in which a code error has occurred according to the output of the code error detection circuit and the mode determination circuit, and the code And a correction circuit including a 0-replacement circuit for setting the sample value of a word in which a code error has occurred to 0 according to the outputs of the error detection circuit and the mode determination circuit. When it is detected that the mode is straight PCM mode, the sample value of the word in which the code error has occurred is added to the above. Instead of the interpolation value from the circuit,
It is characterized in that error correction is performed by setting 0 from the 0 replacement circuit.

[Work]

In the decoder circuit according to the present invention, when a code error is detected in the straight PCM mode, correction is performed to set the sample value of the word in which the code error has occurred to 0, and noise in the high frequency region is reduced.

〔Example〕

An embodiment of a decoder circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block circuit diagram showing the configuration of this embodiment,
In the figure, for example, mode data, range data, compressed data, etc. relating to an audio signal reproduced from a recording medium are serially supplied to the input terminal 1. These data are input to the multiplexer 3 via the error detection circuit 2 and separated by the multiplexer 3. The mode data separated here is supplied to the straight PCM detection circuit 4 and the mode switching processing circuit 7, the range data is supplied to the adaptive decoding processing circuit 6, and the compressed data is supplied to the correction circuit 5. When an error is detected by the error detection circuit 2, an error signal is supplied from the multiplexer 3 to the correction circuit 5.

The correction circuit 5 comprises an average value interpolation circuit 5b and a zero replacement circuit 5a. When the average value interpolating circuit 5b receives the error signal, the average value interpolating circuit 5b performs a process of taking the arithmetic mean value of the sample values of the words before and after the word in which the code error has occurred as the sample value of the word, and the 0 replacement circuit 5a causes the code error. The sample value of the generated word is set to 0.

The output of the correction circuit 5 is the straight PCM detection circuit 4 described above.
Is supplied to the switch 10 controlled by.

The straight PCM detection circuit 4 is the multiplexer 3
When the straight PCM mode is detected from the mode data supplied from the switch 10, the switch 10 is replaced with the 0 replacement circuit 5a.
Switch to the side. Therefore, in the straight PCM mode, the data corrected by the 0 replacement circuit 5a is selected.

The output of the switch 10 is supplied to the adaptive decoding processing circuit 6. Based on the range data supplied from the multiplexer 3, the adaptive decoding processing circuit 6 carries out a process of releasing the block floating from the data supplied from the switch 10, that is, a block expansion.

The output of the adaptive decoding processing circuit 6 is subjected to inverse prediction filtering processing by an inverse prediction filter according to the mode data supplied from the multiplexer 3 in the mode switching processing circuit 7 and supplied to the de-emphasis circuit 8.

The de-emphasis circuit 8 performs processing for lowering high frequency noise on the input data to improve the SN ratio in the sense of hearing. The output of the de-emphasis circuit 8 is supplied to the output terminal 9, and the output data of the decoder circuit is obtained from the output terminal 9.

In the decoder circuit of this embodiment, when the straight PCM detection circuit 4 detects the straight PCM mode,
The output of the 0 replacement circuit 5a of the correction circuit 5 is selected. In the straight PCM mode, since the frequency to be handled is high, noise generation can be reduced by interpolation by zero replacement rather than by using average value interpolation. The reason is considered as follows. That is, if a code error occurs at time t ₁ of the signal f (t) as shown in FIG. 2, the sample value of this word is set to 0. Therefore, the reproduced signal has a waveform shown by a broken line. Comparing this with the case of using the sampled value f '(f' = (f (t ₀ ) + f (t ₂ )) / 2) obtained by the mean value interpolation (shown by the one-dot chain line), the waveform distortion is reduced. Is clear.

In this way, since the 0-replacement circuit 5a is used as the correction circuit in the straight PCM mode, when a code error occurs in the high frequency region, the reproduction signal due to the influence of the code error occurs.
SN subordination can be reduced.

〔The invention's effect〕

As described above, according to the present invention, in the straight PCM mode, the correction is performed so that the sample value of the word in which the code error has occurred is 0. Therefore, the code error in the high frequency can be corrected effectively, and the SN ratio is inferior. A decoder circuit that can be reduced can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a decoder circuit according to the present invention. FIG. 2 is a waveform diagram for explaining a correction process for a high frequency signal in this embodiment. FIG. 3 is a block diagram showing an example of an encoder circuit that performs information compression using a plurality of prediction filters, and FIG. 4 is a block diagram showing an example of a decoder circuit that decodes compressed data. FIG. 5 is a waveform diagram for explaining that distortion occurs when the average value interpolation method is applied to a high frequency signal. 2 …… Error detection circuit 3 …… Multiplexer 4 …… Straight PCM detection circuit 5 …… Correction circuit 5a …… 0 replacement circuit 5b …… Average value interpolation circuit 6 …… Adaptive decoding processing circuit 7 …… Mode switching processing circuit 8 ...... De-emphasis circuit 10 ...... Switch

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-55-157114 (JP, A) JP-A-55-157116 (JP, A) JP-A-55-158711 (JP, A) JP-B 5- 74253 (JP, B2) JP-B 5-74252 (JP, B2) JP-B 4-73333 (JP, B2)

Claims (1)

[Claims] 1. A code error detection of input data in a decoder circuit to which mode information data including at least a straight PCM mode and information data compressed using a plurality of prediction filters including at least a straight PCM mode are supplied. A circuit, an input data mode discrimination circuit, an interpolation circuit for interpolating a sample value of a word in which a code error has occurred according to the output of the code error detection circuit and the mode discrimination circuit, the code error detection circuit and the mode discrimination circuit And a correction circuit including a 0-replacement circuit for setting the sample value of the word in which a code error has occurred to 0 according to the output of the above-mentioned. In the correction circuit, the mode of the input data is the straight PCM mode. Is detected, the sample value of the word in which the code error occurred is interpolated from the above interpolation circuit. Replace the value with 0 from the 0 replacement circuit above.
A decoder circuit characterized by performing error correction by