JPH0758917B2 - Data processing method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an electronic device such as a magnetic disk or an optical disk, which records a binary data in a recording medium or reproduces a binary data sequence from the recording medium for data processing. The present invention relates to a data processing method for converting into a suitable binary code sequence.

2. Description of the Related Art Conventionally, in electronic devices such as magnetic disks and optical disks, it has been necessary to record enormous amounts of information, and it has been essential to improve the recording density when recording binary data on a recording medium.

Generally, the encoding method is such that the original data m bits are the minimum number of bits "0" that enter between adjacent bits "1",
A recording waveform pattern is obtained by converting the code into an n-bit code limited by a maximum of k and performing NRZI conversion of this code. In other words, the recorded waveform pattern corresponds to the code bit "1" inverted and the signal bit "0" corresponded without inversion. The encoding method is generally expressed by four parameters (m, n, d, k).

Next, terms using the above parameters will be described.

T: Data bit interval DSV (Digital Sum Variation): Sign N
RZI converted recording waveform pattern High level +1 Low l
The integrated value for the recorded waveform pattern when evel is -1.

When the DSV can be infinitely large, its code has a DC component. DC when the range of DSV fluctuation is finite
It's free.

CDS (Codeword Digital Sum): DSV from the beginning to the end of one code.

In addition, below, it demonstrates using the said symbol.

In addition, as a typical encoding method from the past, (1) AMPatel, “Encoder and Decoder for a Byte
−Oriented (0,3) 8 / 9code ", IBM Technical Disclosure
Bulletin, Vol.18, No.1 June1975 (p248) (2) AMPatel, “Charge-Constrained Byte-Orie
nted (0,3) Code ", IBM Technical Disclosure Bulleti
n, Vol.19, No.7, December1976 (p2715). (1) is an (8,9,0,3) coding method, and (2) adds two connection bits after connecting two (8,9,0,3) codes of (1). Therefore, the DC-free code is used, and as a result, the DC-free code (8,10,0,
3) Signed.

It is also DC-free. However, in this method, after connecting two codes, that is, after 18 bits, and a connection bit for making DC free cannot be added, the fluctuation range of DSV becomes large though it is finite.

The important thing about the encoding system is Tm.
For in, it is preferable that Tmin is large in order not to include a high frequency component and to be less susceptible to the influence of band limitation. Also, Tw
Is preferably large so that it is difficult to distinguish between the pulses. Also, Tmax should be as small as possible, and the difference between Tmin and Tmax should be small so that synchronization can be easily achieved and low frequency components should be small.

Therefore, an object of the present invention is to convert m-bit data into an n-bit (n <m) code, and convert this n-bit code into NRZI.
At the time of conversion, the fluctuation range of DSV is small, and DC-free encoding with high DC fluctuation suppression effect can be performed on the magnetic disk,
An object of the present invention is to provide a data processing method suitable for recording / reproduction of an optical disc or the like.

Hereinafter, the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram of a configuration of an electronic device that performs a digital modulation method such as a magnetic disk or an optical disk. Reference numeral 1 is an information source or an input unit thereof, and 2 is an information source coding unit for suppressing the redundancy of information of the information source 1. Band compression is for compressing the transmission frequency band in an analog manner, and high-efficiency coding is digitally for one pixel (sample value).
It is intended to reduce the average number of bits per hit, and in that sense, it is close to amplitude compression. Reference numeral 3 denotes a channel and transmission channel coding unit, which includes error correction, digital modulation and the like.
Reference numeral 4 is a recording / reproducing system such as the magnetic disk or the optical disk. Denoted at 5 and 6 are decoding units for decoding the encoded data at the encoding units 2 and 3. An output unit 7 outputs the information obtained by the above processing.

FIG. 2 is a block diagram showing an example of the recording / reproducing system 4 and is an example applied to a video disk.

First, the signal recording system will be described. The light source 9, for example, a semiconductor laser, blinks and emits light by a drive signal from the signal source 8 based on the input data. The signal source 8 includes the coding units 2 and 3 shown in FIG. The light beam emitted by the light source 9 is converted into a parallel light beam by the collimator lens 10, and passes through the optical element 13 having a polarization reflectivity of the grating 11 and the polarizing plate 12. A point image is formed on the perpendicular magnetic recording body 15 by the objective lens 14. The semiconductor laser light is approximately P-polarized with respect to the optical element 13, but the polarizing plate 12 is also installed with the polarization direction in the P-direction.

The grating 11 performs light beam angle separation for connecting a sub spot for detecting tracking to the perpendicular magnetic recording medium 15 by the objective lens 14.

At this time, the effect of the grating 11 causes 3 on the recording medium 15.
You can make individual point images. Of these three point images, the two point images used for tracking signal detection during reproduction are the ± 1st-order diffracted light of the grating 11, and the other one is the non-diffracted light (zero-order light).
Is. Due to the setting of the diffraction efficiency by the grating 11, it is easy to perform signal recording with these two point images and not with non-diffracted light.

The combination of the cylindrical lens 16 and the four-division detector 17 is for obtaining an autofocus signal for adjusting the position of the objective lens 14 in order to focus the point image correctly.

The signal from the four-division detector 17 is divided into two systems by the signal distributor 18, one of which is an autofocus signal and the other of which is a recording signal output and a monitor signal. This output includes the decoding units 5 and 6 and the information output unit 7 described in FIG.

Also, during recording, detectors 19 and 20 for detecting tracking signals
The differential signal from is turned off.

Next, the signal reproducing system will be described.

A signal of a constant level is given from the signal source 8 to bring the light source 9 into a constant light quantity emitting state. Further, the light quantity at this time is adjusted to such an extent that the recorded magnetic domain pattern is not inverted as described above. Collimator 10, grating 11, polarizing plate
12, the light flux transmitted through the optical element 13 forms three point images on the recording medium by the objective lens 14. The light flux from the recording body 15 is modulated in the plane of polarization by the Kerr effect, and enters the detectors 17, 19, 20 in a light-dark modulation state by the system of the light splitting optical element 13 and the analyzer 21. The signal from detector 17 is 2
The signals are distributed to the systems, one system for the autofocus signal and the other for the reproduction signal.

Moreover, the signals of the detectors 19 and 20 are differentiated by the differential AMP 22, and the tracking is performed by swinging the objective lens to the left or right by holding the signal.

By the action of the optical element 13, a bright / dark pattern with high contrast can be detected in the reproducing system.

A Faraday circuit element may be inserted between the optical element 13 and the recording medium 15 as a light amount adjusting means between recording and reproducing.

The Faraday rotating element is, for example, YIG (yttrium.
It is made of iron / garnet) crystal, glass doped with rare earth, or the like, and the plane of polarization of the light flux can be rotated by applying a magnetic field. The reason for using this Faraday rotating element is as follows.

The polarization direction of the reflected light from the recording body 15 at the time of recording is different from the polarization direction of the reflected light subjected to the Kerr rotation at the time of reproduction. Therefore, the reflected light flux is separated from the incident light flux by the light splitting optical element 13, and the amount of light transmitted through the analyzer 21 is different.

Further, at the time of reproduction, the amount of light emitted from the light source must be lower than that at the time of recording so that the recorded magnetic domain pattern is not reversed. Different.

If the light quantity of the light flux guided to the 4-division detector 17 for detecting the recording signal and the autofocus signal through the cylindrical lens 16 is significantly different, it is necessary to switch the sensitivity of the detector 17 during recording and during reproduction. Occurs.

The Faraday rotation element applies a magnetic field appropriately at the time of recording, and rotates the polarization plane of the recording light flux to adjust the amount of light entering the detector 17 by the combination of the optical element 13 and the analyzer 21,
The above problem is solved.

In this example, the video disk was mentioned,
The present invention is not limited to this, and can be applied to data processing in a network constructed by a work station, a printer, a host computer, a disk device and the like.

Next, the encoding method of the present invention (1, 2, 3 in FIG.
Equivalent to) will be described.

DTTang and LRBahl, “Block Codes for a Class of
Constrained Noiseless Channels ", Information and C
According to ontrol, Vol.17, 1970, p436, the number of k limited codes of length n bits, that is, the number of codes of which d = 0 and k is a finite value is Nk
It has been proved that it can be obtained by (n).

Nk (n) = 2 ⁿ (0 <n ≦ k) The results calculated using this formula are shown in Table 1.

It can be seen from Table 1 that the number of codes for n = 10 and k = 2 (d = 0) is 504. However, when these codes are connected, the restriction of k = 2 may be broken at the connecting portion between the codes as shown in FIG. However, if the 10-bit code can be constructed as shown in FIG. 4, the concatenation of codes does not break the restriction of k = 2.

That is, in FIG. 4 (a), the first bit is always 1, and the last bit is 1 and the middle 8 bits are k-limited codes of k = 2. From Table 1, there are 149 of these. In FIG. 4 (b), the first bit is always 1, and the last 2 bits are 10 and the middle 7 bits are k = 2. There are 81 of these in Table 1. FIG. 4 (c) is a code in which the last bit is always 1, the last 3 bits are 100, and the middle 6 bits are k = 2. There are 44 of these from Table 1.

From the above, there are 274 k-restricted codes that do not break the restriction of k = 2 even if they are concatenated as shown in FIG.

Consider separating the data every 8 bits and converting this to a 10-bit code. Then, 8 bit data is 2 ⁸ =
There are 256 patterns, which are smaller than the number of 274 10-bit codes in FIG. Therefore, 256 out of 274 codes
Select one piece, and use this one-to-one with 256 8-bit data.
By corresponding to (m, n, d, k) ＝ (8,10,0,2)
It can be seen that the code can be realized. Next, as shown in FIG.
An example of specific creation of the codes (b) and (c) will be described. This should follow the state transition diagram of FIG. Where S
1, S2, S3 are three states, and S1 is the initial state. D of D / C indicates a data bit, and C indicates a code bit. FIG. 6 shows a method of creating a 6-bit k-limited k = 2 code shown in FIG. 4 (c). The same applies to FIGS. 4 (a) and 4 (b).
FIG. 6 will be specifically described. First, 6-bit data (D ₁ ...
Prepare D ₆ . (D ₁ ... D ₆₎ is (0 ... 0), (0 ... 1),
(0 ... 10) ... are arranged in the order of increasing by 1. The 6-bit code is represented by (C ₁ ... C ₆ ). First (D ₁ ... D ₆ ) = (0 ... 0)
I will describe the time. From the state transition diagram of Fig. 5, D ₁ = 0 and C ₁ =
1 is generated. Next, C ₂ = 1 is generated when D ₂ = 0, and similarly, C ₆ = 1 is generated when D ₆ = 0, and the first code is completed. The same applies to the following, but when (D ₁ ... D ₆ ) = (000111), the last bit 1 goes to stop. This means that no code can be created from (000111).

Similarly, create codes, and repeat this operation until 44 codes are created. And (D _{1 to} D ₆ ) = (11011
(C ₁ ... C ₆ ) = (001001) is created in 0), and all 44 pieces are extracted. In the case of FIG. 4 (a) or (b), the data is converted into (D ₁ ... D ₇ ) (D ₁ ... D ₈ ) and coded (C ₁
C ₇₎ it is sufficient to create a (C ₁ ... C _8). Of the 274 concatenations extracted as described above, 256 of the codes that do not violate the k-limit are appropriately selected, and 256 8-bit data and 1: 1
The (8,10,0,2) coding method can be realized by supporting the above. As described above, (m, n, d, k) = (8,10,
0,2). Write the selected 256 codes to ROM look
Corresponding to the data by up table method.

Next, the operation for making DC free for each code, that is, every 10 bits, is performed, the fluctuation range of DSV (Digital Sum Variation) is reduced, and a DC-free code with a large DC fluctuation suppression effect is created. . FIG. 7 is a block diagram of a coding block diagram of a portion corresponding to 1, 2, and 3 in FIG. First, the encoding algorithm performed in the block diagram will be described below.

STEP1: Set DSV = 0, P = 0 STEP2: Use the above-mentioned encoding method to convert 8 bit data to 10
Bits of code (designated as W The W of the top bit of the (which is always 1) designated as W ₁₎ to convert.

STEP3: Calculate CDS.

STEP4: (i) If P = 0 and sign DSV = sign CDS
Invert W ₁ and set DSV = DSV-CDS.

(Ii) If P = 0 and sign DSV ≠ sign CDS, W ₁ is non-inverted and set as DSV = DSV + CDS.

(Iii) If P = 1 and sign DSV = sign CDS, W ₁ is non-inverted and set as DSV = DSV-CDS.

(Iv) If P = 1 and sign DSV ≠ sign CDS, invert W ₁ and set DSV = DSV + CDS.

The code W after the operation of STEP 4 is named W '.

The flag is set to 0 if the number of "1" is an even number, and to 1 if it is an odd number. Also, the binary signal Hi obtained by NRZI conversion of the code W
gh level (1) is set to +1 and Low level (0) is set to -1, and the value obtained by summing these is the CDS (Codeword Digital Sustain).
m). However, the binary signal obtained by NRZI conversion of W is Low lev
Let's start from el. It also indicates the polarity of sign CDS (+ or −). However, when CDS is 0, sign CDS is +.

STEP5: P = P (P of W ') However, shows exclusive OR. W'is output as a code.

STEP6: Jump to STEP2 for the next encoding.

Based on the description of the above algorithm, FIG. 7 will be described. Data of every 8 bits input from the input terminal of FIG. 7 is input to 30 shift registers, from which the corresponding 10-bit code is read from the ROM 31 by the look-up table method described above and input in parallel to the 32 shift registers. (STEP3 of the above algorithm). This 10-bit code is also input to 33 shift registers at the same time. The 10-bit code loaded in 33 is passed through the NRZI converter in 34 to be NRZI converted. The number of "1" s in this NRZI converted code is set by 35 CDS counter A, and the number of "0" s is set by 36 CDS.
Counted by counter B, the respective values are 37 and 38
It is stored in the register A and the register B of the above (STEP3 of the above algorithm). 34 NRZI converters are configured in Figure 8,
In FIG. 8, the input terminal 39 is the exclusive OR circuit 40, and the 1-bit delay element is the output terminal. Further, the CDS calculation is obtained by subtracting the contents of the register B of 38 from the contents of the register A of 37 by the subtracter 4 of FIG. 7, and this result is obtained.
Stored in 42 CDS registers.

Next, in STEP 4 of the above algorithm, (i) to (i
In case of v) Is the same value as, and this determination is performed by 43 logic circuits. However, P is a value of FIG. 7 and is 1 or 0. Cq is 42 CDS
Is the MSB of the register and dq is the MSB of the 45 DSV registers. The MSB is 1 because the register contents are in 2's complement notation.
DSV and CDS to indicate a positive number when 0 and a positive number when 0
The comparison of the polarities of cq and dq is sufficient. Indicates exclusive OR. Based on the above four flag signals, the logic circuit of 43, if the flag of (i) is present, invert the bit of W ₁ of 46 and let the operation of DSV = DSV-CDS be performed by the adder / subtractor of 47, The operation result is stored in 45 DSV registers. FIG. 9 shows a specific example of the above-mentioned four flag signal generating circuits. Details are omitted. STEP4 ends as described above. Next, in STEP 5, the code W'is output from the shift register 32 and output from the output terminal of 48, and 48
At P flip-flop A, the even number of 1's in W'is identified. That is, 48 is 0 when the number of 1s is even and 1 when it is odd. This can be done by setting the initial value of 48 flip-flops to 0 and inverting each time 1 comes. This content is stored in 49 buffers. And it is buffered by 50 exclusive OR circuits.
The contents of 49 and P44 are exclusive-ORed and the result is stored in P of 44. With the above, STEP5 ends, and the process returns to STEP2 again and the same thing is repeated.

As described above in detail, according to the system (8,10,0,2) code of the present invention, And in the typical (8,9,0,3) in the conventional method, For example, comparing this method with this method, Tmax can be greatly reduced with a slight decrease in Tmin and Tw in this method, which is easy to synchronize and has the effect of becoming a method with less low frequency components. is there. The same applies when compared to other methods. Moreover, the DC-free code is realized by using the (8,10,0,2) code. Also, when selecting 256 from the 274 codes shown in FIG. 2, the code 194 of FIG.
By selecting 26 from among the 81 and the codes shown in FIG. 4 (b) and the codes shown in FIG. 4 (c), the number of cases where the k limit is violated at the concatenated part of the codes can be minimized and the efficient codes There is an effect that can be converted.

Further, since this system is made based on the (8,10,0,2) code, there is a possibility that k = 2 will be broken only in the concatenated part of the 10-bit code. Therefore, it has the effect of producing a DC-free code with less low-frequency components and easier synchronization than the conventional method.

In this method, the operation for making DC free is performed for each code, that is, for every 10 bits (operation of inverting or non-inverting the leading bit W ₁ of the code). Therefore, DSV (Digital Sum Variatio)
n) fluctuation range is small and DC fluctuation suppression effect is large.
This has the effect of creating a C-free code. The present invention is not limited to encoding from 8 bits to 10 bits, and can be similarly applied to decoding thereof even if the present invention is used in reverse, and is not limited to 8 bits and encoding from 4 bits to 5 bits. The same applies to encoding or decoding other than the above, for example, 3 bits to 7 bits.

As described above, according to the present invention, when m-bit data is converted into an n-bit (n <m) code and the n-bit code is NRZI-converted, the fluctuation range of DSV is small and the DC fluctuation is small. It is possible to perform DC-free coding with a high suppression effect of.

[Brief description of drawings]

FIG. 1 is a block diagram of a configuration of an electronic device, FIG. 2 is a configuration diagram showing an example of a recording / reproducing system, FIG. 3 is an explanatory diagram of a connecting portion between symbols, and FIG. 4 is a symbol of a 10-bit configuration. 5 and 5 are state transition diagrams, and FIG. 6 is a diagram showing a method of creating a k-restricted code with k = 2 in the 6-bit configuration of FIG. 4 (c). FIG. 7 is a block diagram of the encoding configuration. FIG. 8 is a block diagram showing the configuration of an exclusive OR circuit, and FIG. 9 is a diagram showing a concrete example of a flag signal generating circuit. 1 …… Information source 2 …… Information source coding 3 …… Channel coding 31 …… ROM table 34 …… NRZI converter 32,33 …… Shift register 35,36 …… CDS counter

Claims (1)

[Claims] 1. A data processing method for converting m-bit data into an n-bit (n <m) code and performing NRZI conversion on the n-bit code, characterized by using the following STEP1 to STEP6 algorithms. Data processing method. STEP1 Set DSV = 0 and P = 0. STEP2 Convert m-bit data to an n-bit code, set this code to W, and set the _first bit of the code W to W ₁ . Step 3 The sum is calculated by setting the high level of the waveform pattern of the NRZI-converted binary signal so that the code W starts from the low level to +1 and the low level to -1, to obtain CDS. STEP4 Set the polarity at 0 to +, and set the polarity (+ or-) to sig.
When expressed in n, 1. If if P = 0 and signDSV = signCDS, by inverting the W _1, and sets the DSV-CDS. 2. If If P = 0 and signDSV ≠ signCDS, W ₁ is no inversion, it sets the DSV = DSV + CDS. 3. If If P = 1 and signDSV = signCDS, W ₁ is no inversion, sets the DSV = DSV-CDS. 4. If If P = 1 and signDSV ≠ signCDS, W ₁ is no inversion, it sets the DSV = DSV + CDS. The symbol W after the above operation is designated as W '. In STEP5 W ', 0 if the number of bits with value "1" is even,
If it is an odd number, 1 is set as P ′, and P = P + P ′ (+
Represents an exclusive OR.). W'is output as a code. STEP6 Jump to STEP2 for encoding the next data.